diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
3 files changed, 3874 insertions, 3849 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index d26a43093..370583b3e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144266 # Number of seconds simulated -sim_ticks 5144265998000 # Number of ticks simulated -final_tick 5144265998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.152315 # Number of seconds simulated +sim_ticks 5152314519000 # Number of ticks simulated +final_tick 5152314519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171354 # Simulator instruction rate (inst/s) -host_op_rate 338701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2161855241 # Simulator tick rate (ticks/s) -host_mem_usage 817304 # Number of bytes of host memory used -host_seconds 2379.56 # Real time elapsed on the host -sim_insts 407746267 # Number of instructions simulated -sim_ops 805959101 # Number of ops (including micro ops) simulated +host_inst_rate 171705 # Simulator instruction rate (inst/s) +host_op_rate 339400 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2173929918 # Simulator tick rate (ticks/s) +host_mem_usage 815744 # Number of bytes of host memory used +host_seconds 2370.05 # Real time elapsed on the host +sim_insts 406948645 # Number of instructions simulated +sim_ops 804394656 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1040896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10728128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1035840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10724032 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11801664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1040896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1040896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9535488 # Number of bytes written to this memory -system.physmem.bytes_written::total 9535488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11792640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1035840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1035840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9542144 # Number of bytes written to this memory +system.physmem.bytes_written::total 9542144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16264 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167563 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 184401 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148992 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148992 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 184260 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149096 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149096 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 202341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2085454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2294140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 202341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 202341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1853615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1853615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1853615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2081401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2288804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 202341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2085454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4147754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 184401 # Number of read requests accepted -system.physmem.writeReqs 148992 # Number of write requests accepted -system.physmem.readBursts 184401 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148992 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11790400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11264 # Total number of bytes read from write queue -system.physmem.bytesWritten 9534208 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11801664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9535488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 201044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2081401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4140816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184260 # Number of read requests accepted +system.physmem.writeReqs 149096 # Number of write requests accepted +system.physmem.readBursts 184260 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149096 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11779776 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12864 # Total number of bytes read from write queue +system.physmem.bytesWritten 9541120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11792640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9542144 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 201 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48430 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11512 # Per bank write bursts -system.physmem.perBankRdBursts::1 10865 # Per bank write bursts -system.physmem.perBankRdBursts::2 12624 # Per bank write bursts -system.physmem.perBankRdBursts::3 11646 # Per bank write bursts -system.physmem.perBankRdBursts::4 11360 # Per bank write bursts -system.physmem.perBankRdBursts::5 11063 # Per bank write bursts -system.physmem.perBankRdBursts::6 11424 # Per bank write bursts -system.physmem.perBankRdBursts::7 11380 # Per bank write bursts -system.physmem.perBankRdBursts::8 11354 # Per bank write bursts -system.physmem.perBankRdBursts::9 10854 # Per bank write bursts -system.physmem.perBankRdBursts::10 10623 # Per bank write bursts -system.physmem.perBankRdBursts::11 11335 # Per bank write bursts -system.physmem.perBankRdBursts::12 12163 # Per bank write bursts -system.physmem.perBankRdBursts::13 12460 # Per bank write bursts -system.physmem.perBankRdBursts::14 11874 # Per bank write bursts -system.physmem.perBankRdBursts::15 11688 # Per bank write bursts -system.physmem.perBankWrBursts::0 9762 # Per bank write bursts -system.physmem.perBankWrBursts::1 9087 # Per bank write bursts -system.physmem.perBankWrBursts::2 9770 # Per bank write bursts -system.physmem.perBankWrBursts::3 9357 # Per bank write bursts -system.physmem.perBankWrBursts::4 9485 # Per bank write bursts -system.physmem.perBankWrBursts::5 8994 # Per bank write bursts -system.physmem.perBankWrBursts::6 9154 # Per bank write bursts -system.physmem.perBankWrBursts::7 8718 # Per bank write bursts -system.physmem.perBankWrBursts::8 8812 # Per bank write bursts -system.physmem.perBankWrBursts::9 9056 # Per bank write bursts -system.physmem.perBankWrBursts::10 8954 # Per bank write bursts -system.physmem.perBankWrBursts::11 9300 # Per bank write bursts -system.physmem.perBankWrBursts::12 9801 # Per bank write bursts -system.physmem.perBankWrBursts::13 9709 # Per bank write bursts -system.physmem.perBankWrBursts::14 9528 # Per bank write bursts -system.physmem.perBankWrBursts::15 9485 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 58140 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11261 # Per bank write bursts +system.physmem.perBankRdBursts::1 10600 # Per bank write bursts +system.physmem.perBankRdBursts::2 12322 # Per bank write bursts +system.physmem.perBankRdBursts::3 11592 # Per bank write bursts +system.physmem.perBankRdBursts::4 11482 # Per bank write bursts +system.physmem.perBankRdBursts::5 10950 # Per bank write bursts +system.physmem.perBankRdBursts::6 11082 # Per bank write bursts +system.physmem.perBankRdBursts::7 11124 # Per bank write bursts +system.physmem.perBankRdBursts::8 10622 # Per bank write bursts +system.physmem.perBankRdBursts::9 11032 # Per bank write bursts +system.physmem.perBankRdBursts::10 11540 # Per bank write bursts +system.physmem.perBankRdBursts::11 11373 # Per bank write bursts +system.physmem.perBankRdBursts::12 12384 # Per bank write bursts +system.physmem.perBankRdBursts::13 12480 # Per bank write bursts +system.physmem.perBankRdBursts::14 11990 # Per bank write bursts +system.physmem.perBankRdBursts::15 12225 # Per bank write bursts +system.physmem.perBankWrBursts::0 9586 # Per bank write bursts +system.physmem.perBankWrBursts::1 9015 # Per bank write bursts +system.physmem.perBankWrBursts::2 9694 # Per bank write bursts +system.physmem.perBankWrBursts::3 9483 # Per bank write bursts +system.physmem.perBankWrBursts::4 9592 # Per bank write bursts +system.physmem.perBankWrBursts::5 9320 # Per bank write bursts +system.physmem.perBankWrBursts::6 9057 # Per bank write bursts +system.physmem.perBankWrBursts::7 9053 # Per bank write bursts +system.physmem.perBankWrBursts::8 8752 # Per bank write bursts +system.physmem.perBankWrBursts::9 9410 # Per bank write bursts +system.physmem.perBankWrBursts::10 9210 # Per bank write bursts +system.physmem.perBankWrBursts::11 8755 # Per bank write bursts +system.physmem.perBankWrBursts::12 9657 # Per bank write bursts +system.physmem.perBankWrBursts::13 9381 # Per bank write bursts +system.physmem.perBankWrBursts::14 9483 # Per bank write bursts +system.physmem.perBankWrBursts::15 9632 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 5144265948500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5152314469500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 184401 # Read request sizes (log2) +system.physmem.readPktSize::6 184260 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148992 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 169976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149096 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 169844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,112 +156,114 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 73109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.681517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.230147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.360710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28156 38.51% 38.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17755 24.29% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7676 10.50% 73.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4351 5.95% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2926 4.00% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2405 3.29% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1356 1.85% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1112 1.52% 89.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7372 10.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 73109 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.343238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.383377 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7268 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73146 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.483225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.242867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.005738 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28143 38.48% 38.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17778 24.30% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7759 10.61% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4281 5.85% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2977 4.07% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2397 3.28% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1373 1.88% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1102 1.51% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7336 10.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73146 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7286 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.261872 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.739811 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7285 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7269 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7269 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.494153 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.676401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.977803 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6209 85.42% 85.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 177 2.43% 87.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.43% 88.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 190 2.61% 90.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 15 0.21% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.08% 93.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 110 1.51% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.12% 94.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 21 0.29% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 27 0.37% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.07% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 236 3.25% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.11% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 36 0.50% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.07% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.21% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7269 # Writes before turning the bus around for reads -system.physmem.totQLat 2113024695 # Total ticks spent queuing -system.physmem.totMemAccLat 5567243445 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 921125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11469.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7286 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.461158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.651895 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.024155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6243 85.68% 85.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 165 2.26% 87.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.54% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 177 2.43% 90.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.30% 91.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.07% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 106 1.45% 94.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.15% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.33% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 33 0.45% 95.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.10% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 220 3.02% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.05% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.12% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.40% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.08% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 18 0.25% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7286 # Writes before turning the bus around for reads +system.physmem.totQLat 2105191048 # Total ticks spent queuing +system.physmem.totMemAccLat 5556297298 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 920295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11437.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30219.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30187.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s @@ -271,298 +273,298 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.39 # Average write queue length when enqueuing -system.physmem.readRowHits 150283 # Number of row buffer hits during reads -system.physmem.writeRowHits 109804 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes -system.physmem.avgGap 15430035.87 # Average gap between requests -system.physmem.pageHitRate 78.05 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 271774440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 148289625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 716609400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 481638960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 133079069070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2969819271000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3440514616095 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.806670 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4940481054222 # Time in different power states -system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states +system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing +system.physmem.readRowHits 150243 # Number of row buffer hits during reads +system.physmem.writeRowHits 109749 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.61 # Row buffer hit rate for writes +system.physmem.avgGap 15455892.41 # Average gap between requests +system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 269634960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 147122250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 705213600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 484704000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 132970948335 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2974744703250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3445846141035 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.796378 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4948677575724 # Time in different power states +system.physmem_0.memoryStateTime::REF 172046940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32006683778 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31589843276 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 280929600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 153285000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 720337800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 483699600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 133106515425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2969795195250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3440537926275 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4940433568236 # Time in different power states -system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states +system.physmem_1.actEnergy 283348800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 154605000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 730438800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 481334400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 133265512935 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2974486313250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3445925367825 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811755 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4948236275986 # Time in different power states +system.physmem_1.memoryStateTime::REF 172046940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32047173014 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32026607764 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86512376 # Number of BP lookups -system.cpu.branchPred.condPredicted 86512376 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 844809 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79880541 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77944216 # Number of BTB hits +system.cpu.branchPred.lookups 86360408 # Number of BP lookups +system.cpu.branchPred.condPredicted 86360408 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844738 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79711483 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77808056 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.575974 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1537356 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178131 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.612104 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1540361 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177639 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 465431904 # number of cpu cycles simulated +system.cpu.numCycles 465551291 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27316222 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427457339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86512376 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79481572 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433294653 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1774328 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 174290 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 61780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 197089 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 797 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8939505 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 424296 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5201 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 461932056 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.826209 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.017418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27284501 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426653476 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86360408 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79348417 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433446162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1774418 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 139394 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 62229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 198576 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 774 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8943748 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 426371 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4516 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 462018901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.822492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.015475 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 297044979 64.30% 64.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2134462 0.46% 64.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72126640 15.61% 80.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1546779 0.33% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2100235 0.45% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2289900 0.50% 81.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1474676 0.32% 81.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1857009 0.40% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81357376 17.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 297432046 64.38% 64.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2127313 0.46% 64.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72010980 15.59% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1540927 0.33% 80.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2092821 0.45% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2281981 0.49% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1471602 0.32% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1847080 0.40% 82.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81214151 17.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 461932056 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185875 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.918410 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23107773 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 281695317 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 147794197 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8447605 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 887164 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 835787144 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 887164 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26441875 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 229504552 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14337084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152214834 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 38546547 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 832466923 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 458085 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12798467 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 221946 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22321415 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 994552862 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1807469855 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1111168371 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 379 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963838514 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30714343 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460142 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463176 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43334873 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17067493 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10022220 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1319734 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1116337 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 827242342 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1181786 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 822485271 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 216558 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22465018 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33877646 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 141871 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 461932056 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.780533 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400914 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 462018901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185501 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.916448 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22519839 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 281050355 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150243576 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7317922 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 887209 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 834205750 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 887209 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25305856 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 229987183 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14520771 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154096496 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 37221386 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 830901673 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 454414 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12058066 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 208457 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22294259 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 992600987 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1804085973 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1109069164 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 286 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 961883524 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30717461 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 460427 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463529 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38187587 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17040256 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10018392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1266986 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1072258 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825691253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1151613 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820808364 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 215045 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22448205 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33824600 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 141893 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 462018901 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.776569 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278202681 60.23% 60.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13844974 3.00% 63.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9781174 2.12% 65.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7532969 1.63% 66.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 73227075 15.85% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4827596 1.05% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72754467 15.75% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1183000 0.26% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578120 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278841075 60.35% 60.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13664119 2.96% 63.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9689206 2.10% 65.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6979280 1.51% 66.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74151695 16.05% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4284933 0.93% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72644295 15.72% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1183606 0.26% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 580692 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 461932056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 462018901 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2482095 76.42% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 605940 18.66% 95.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160087 4.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1922566 72.06% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 586085 21.97% 94.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159449 5.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 284904 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 794458238 96.59% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149904 0.02% 96.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126188 0.02% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 113 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18188915 2.21% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9277009 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 284230 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 792921370 96.60% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149961 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126332 0.02% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18051625 2.20% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9274757 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 822485271 # Type of FU issued -system.cpu.iq.rate 1.767144 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3248122 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2110366769 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 850901074 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818087590 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 508 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 586 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 178 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825448239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1862376 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820808364 # Type of FU issued +system.cpu.iq.rate 1.763089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2668100 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003251 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2106518335 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 849303097 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 816525348 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 438 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823192025 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1863548 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3081864 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14686 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14021 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1600056 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3085191 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14446 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1597044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2207186 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2095832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68625 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 887164 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205274699 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15795611 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 828424128 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 165882 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17067493 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10022220 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 692366 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 393655 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14549719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14021 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 476392 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506422 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 982814 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 820971747 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17818623 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1389098 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 887209 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 206158213 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15645218 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826842866 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 165190 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17040277 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10018392 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 682629 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 383889 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14436572 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 477389 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506444 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 983833 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819298071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17680302 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1386078 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26886211 # number of memory reference insts executed -system.cpu.iew.exec_branches 83147027 # Number of branches executed -system.cpu.iew.exec_stores 9067588 # Number of stores executed -system.cpu.iew.exec_rate 1.763892 # Inst execution rate -system.cpu.iew.wb_sent 820497311 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818087768 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639862073 # num instructions producing a value -system.cpu.iew.wb_consumers 1048693225 # num instructions consuming a value +system.cpu.iew.exec_refs 26745461 # number of memory reference insts executed +system.cpu.iew.exec_branches 82993620 # Number of branches executed +system.cpu.iew.exec_stores 9065159 # Number of stores executed +system.cpu.iew.exec_rate 1.759845 # Inst execution rate +system.cpu.iew.wb_sent 818824421 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 816525502 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638690631 # num instructions producing a value +system.cpu.iew.wb_consumers 1046712832 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.757696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610152 # average fanout of values written-back +system.cpu.iew.wb_rate 1.753889 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610187 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22343285 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1039914 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 855258 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 458562995 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.757576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.649246 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22323770 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1009720 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 855337 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 458653605 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.753817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.647498 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 287777749 62.76% 62.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11132608 2.43% 65.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3641047 0.79% 65.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74579710 16.26% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2448796 0.53% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1627078 0.35% 83.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1001834 0.22% 83.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70969693 15.48% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5384480 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 288196518 62.84% 62.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11088839 2.42% 65.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3639702 0.79% 66.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74471288 16.24% 82.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2429938 0.53% 82.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1624365 0.35% 83.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000566 0.22% 83.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70851536 15.45% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5350853 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 458562995 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407746267 # Number of instructions committed -system.cpu.commit.committedOps 805959101 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 458653605 # Number of insts commited each cycle +system.cpu.commit.committedInsts 406948645 # Number of instructions committed +system.cpu.commit.committedOps 804394656 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22407791 # Number of memory references committed -system.cpu.commit.loads 13985627 # Number of loads committed -system.cpu.commit.membars 468163 # Number of memory barriers committed -system.cpu.commit.branches 82155343 # Number of branches committed +system.cpu.commit.refs 22376433 # Number of memory references committed +system.cpu.commit.loads 13955085 # Number of loads committed +system.cpu.commit.membars 448031 # Number of memory barriers committed +system.cpu.commit.branches 82000673 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734813827 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155420 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171757 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783115943 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144574 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 733377152 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155590 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171815 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 781582591 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144575 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121813 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -589,230 +591,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13983042 1.73% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8422164 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13952498 1.73% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8421348 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 805959101 # Class of committed instruction -system.cpu.commit.bw_lim_events 5384480 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1281402583 # The number of ROB reads -system.cpu.rob.rob_writes 1659991505 # The number of ROB writes -system.cpu.timesIdled 284256 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3499848 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9823097505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407746267 # Number of Instructions Simulated -system.cpu.committedOps 805959101 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.141474 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.141474 # CPI: Total CPI of All Threads -system.cpu.ipc 0.876060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.876060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1090398458 # number of integer regfile reads -system.cpu.int_regfile_writes 654801015 # number of integer regfile writes -system.cpu.fp_regfile_reads 178 # number of floating regfile reads -system.cpu.cc_regfile_reads 415698435 # number of cc regfile reads -system.cpu.cc_regfile_writes 321644299 # number of cc regfile writes -system.cpu.misc_regfile_reads 264872577 # number of misc regfile reads +system.cpu.commit.op_class_0::total 804394656 # Class of committed instruction +system.cpu.commit.bw_lim_events 5350853 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1279942872 # The number of ROB reads +system.cpu.rob.rob_writes 1656820485 # The number of ROB writes +system.cpu.timesIdled 287895 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3532390 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9839075158 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 406948645 # Number of Instructions Simulated +system.cpu.committedOps 804394656 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.144005 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.144005 # CPI: Total CPI of All Threads +system.cpu.ipc 0.874122 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.874122 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088092002 # number of integer regfile reads +system.cpu.int_regfile_writes 653524498 # number of integer regfile writes +system.cpu.fp_regfile_reads 154 # number of floating regfile reads +system.cpu.cc_regfile_reads 414883395 # number of cc regfile reads +system.cpu.cc_regfile_writes 320972082 # number of cc regfile writes +system.cpu.misc_regfile_reads 264296844 # number of misc regfile reads system.cpu.misc_regfile_writes 400155 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1656886 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993571 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18963252 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657398 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.441580 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1656669 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.992170 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18961321 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657181 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.441913 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993571 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.992170 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999985 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per 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18960354 # number of overall hits -system.cpu.dcache.overall_hits::total 18960354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1800618 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1800618 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 335187 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 335187 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406619 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406619 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2135805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2135805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2542424 # number of overall misses -system.cpu.dcache.overall_misses::total 2542424 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29915350500 # number of ReadReq miss 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average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909 # average overall mshr uncacheable latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077177 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077177 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14776.592265 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14776.592265 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66077.034672 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66077.034672 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16875.266797 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16875.266797 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26634.959522 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26634.959522 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24265.296467 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24265.296467 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.298853 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.298853 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199895.734427 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199895.734427 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.732301 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.732301 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 86946 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.839570 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92503 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 86961 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.063730 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.839570 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.989973 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.989973 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 70093 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.821930 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 109512 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70108 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.562047 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 199860126500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821930 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988871 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988871 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 449092 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 449092 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92507 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92507 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92507 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92507 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92507 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92507 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 88026 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 88026 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 88026 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 88026 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 88026 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 88026 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1095128000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1095128000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1095128000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1095128000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1095128000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1095128000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180533 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 180533 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180533 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 180533 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180533 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 180533 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.487590 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.487590 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.487590 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.487590 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.487590 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.487590 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 432670 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 432670 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 109535 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 109535 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 109535 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 109535 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 109535 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 109535 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71200 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71200 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71200 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71200 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71200 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71200 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 922231500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 922231500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 922231500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 922231500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 922231500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 922231500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180735 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 180735 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180735 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 180735 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180735 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 180735 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.393947 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.393947 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.393947 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.393947 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.393947 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.393947 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12952.689607 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12952.689607 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12952.689607 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12952.689607 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12952.689607 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12952.689607 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -821,180 +824,183 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22750 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22750 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 88026 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 88026 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 88026 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 88026 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 88026 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 88026 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1007102000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1007102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1007102000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.487590 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.487590 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.487590 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21274 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21274 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71200 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71200 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71200 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71200 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71200 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71200 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 851031500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 851031500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 851031500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 851031500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 851031500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 851031500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.393947 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.393947 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.393947 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.393947 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.393947 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.393947 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11952.689607 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11952.689607 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11952.689607 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 979952 # number of replacements -system.cpu.icache.tags.tagsinuse 509.399185 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7892668 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 980464 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.049931 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 150322947500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.399185 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994920 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994920 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 977286 # number of replacements +system.cpu.icache.tags.tagsinuse 509.169987 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7899726 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 977798 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.079098 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 150383300500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.169987 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id 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number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1046827 # number of overall misses -system.cpu.icache.overall_misses::total 1046827 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15679887484 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15679887484 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15679887484 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15679887484 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15679887484 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15679887484 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8939495 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8939495 # number of ReadReq accesses(hits+misses) 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ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15040.908878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15040.908878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15040.908878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15040.908878 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15272 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 489 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.231084 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 91.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66288 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66288 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66288 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66288 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66288 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66288 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980539 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980539 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980539 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980539 # number of demand (read+write) MSHR misses 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-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38541 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38541 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38541 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38541 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374997 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374997 # miss rate for ReadReq accesses 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+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12208.448658 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1003,183 +1009,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3197 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3197 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 20167 # number of ReadReq MSHR misses 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miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161984500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.374997 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.374997 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.374977 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.374977 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.374977 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.374977 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11208.448658 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11208.448658 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11208.448658 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111670 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64798.131266 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4919632 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175949 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.960557 # Average number of references to valid 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+system.cpu.l2cache.overall_mshr_misses::total 184762 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13902 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13902 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587362 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587362 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 105285000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 105285000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15659734500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15659734500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2012557000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2012557000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 615000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4444414500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4453627500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8598000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 615000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2012557000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20104149000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22125919000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8598000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 615000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2012557000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20104149000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22125919000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90977838000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90977838000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2619015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2619015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93596853000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93596853000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808628 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808628 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024496 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067764 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.067764 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125900 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818687 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818687 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460694 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460694 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016554 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026079 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068142 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068142 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71525.135870 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71525.135870 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117898.380564 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117898.380564 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124347.049737 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124347.049737 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124549.223742 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124566.539871 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124347.049737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119306.792556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119753.623581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124347.049737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119306.792556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119753.623581 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.225613 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.225613 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.238671 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.238671 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.222926 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.222926 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5491514 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2726446 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 94920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1211 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1211 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5440647 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2708460 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1238 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 602897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3061240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13882 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13882 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1734407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1095490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 980539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1478351 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3006256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1731980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 976140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 117314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 288324 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288324 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 977872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1455461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2939753 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6208049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 41124 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 194511 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9383437 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207643157 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1196736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 6311744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 277897109 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 226924 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6316816 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.030269 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.203509 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2931742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6148479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31127 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 166003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9277351 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125047680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207509531 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 939712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5524480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 339021403 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 218907 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3519115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019900 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.161788 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6163711 97.58% 97.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 115005 1.82% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 38100 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3460821 98.34% 98.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 46556 1.32% 99.67% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 11738 0.33% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6316816 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4646513967 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3519115 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5581131973 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 659789 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 669284 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1472350908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1468639319 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3097364534 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3067775714 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 30265969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 21694467 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 132091893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 106870358 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 222097 # Transaction distribution -system.iobus.trans_dist::ReadResp 222097 # Transaction distribution -system.iobus.trans_dist::WriteReq 57711 # Transaction distribution -system.iobus.trans_dist::WriteResp 57711 # Transaction distribution -system.iobus.trans_dist::MessageReq 1645 # Transaction distribution -system.iobus.trans_dist::MessageResp 1645 # Transaction distribution +system.iobus.trans_dist::ReadReq 212021 # Transaction distribution +system.iobus.trans_dist::ReadResp 212021 # Transaction distribution +system.iobus.trans_dist::WriteReq 57726 # Transaction distribution +system.iobus.trans_dist::WriteResp 57726 # Transaction distribution +system.iobus.trans_dist::MessageReq 1647 # Transaction distribution +system.iobus.trans_dist::MessageResp 1647 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1384,21 +1395,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 464358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 562906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 542788 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1408,67 +1419,67 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 238456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3272852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3921096 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3262802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3986644 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10458500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 146500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 1029000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 94000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 58500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 300003000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1174000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 212500 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 24569000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 241306768 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 241170809 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 1085500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 453367000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47574 # number of replacements -system.iocache.tags.tagsinuse 0.116041 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.140720 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4999338704000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116041 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007253 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007253 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4999394542000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.140720 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008795 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.008795 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1482,14 +1493,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 909 system.iocache.demand_misses::total 909 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses system.iocache.overall_misses::total 909 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144457672 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144457672 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6056832096 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6056832096 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144457672 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144457672 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144457672 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144457672 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150240673 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 150240673 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6073165136 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6073165136 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 150240673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 150240673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 150240673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 150240673 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1506,19 +1517,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158919.331133 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 158919.331133 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 158919.331133 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165281.268427 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129990.692123 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129990.692123 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 165281.268427 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 165281.268427 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1090 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 52 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 104 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.615385 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.480769 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1532,14 +1543,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99007672 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3720832096 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3720832096 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 99007672 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 99007672 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104790673 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3737165136 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3737165136 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 104790673 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 104790673 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1548,77 +1559,77 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115281.268427 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79990.692123 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79990.692123 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115281.268427 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115281.268427 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 602897 # Transaction distribution -system.membus.trans_dist::ReadResp 655826 # Transaction distribution -system.membus.trans_dist::WriteReq 13882 # Transaction distribution -system.membus.trans_dist::WriteResp 13882 # Transaction distribution -system.membus.trans_dist::Writeback 148992 # Transaction distribution -system.membus.trans_dist::CleanEvict 9700 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2190 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1729 # Transaction distribution -system.membus.trans_dist::ReadExReq 132608 # Transaction distribution -system.membus.trans_dist::ReadExResp 132605 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52937 # Transaction distribution -system.membus.trans_dist::MessageReq 1645 # Transaction distribution -system.membus.trans_dist::MessageResp 1645 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.trans_dist::ReadReq 573460 # Transaction distribution +system.membus.trans_dist::ReadResp 626303 # Transaction distribution +system.membus.trans_dist::WriteReq 13902 # Transaction distribution +system.membus.trans_dist::WriteResp 13902 # Transaction distribution +system.membus.trans_dist::WritebackDirty 149096 # Transaction distribution +system.membus.trans_dist::CleanEvict 9693 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2236 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1746 # Transaction distribution +system.membus.trans_dist::ReadExReq 132555 # Transaction distribution +system.membus.trans_dist::ReadExResp 132550 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52847 # Transaction distribution +system.membus.trans_dist::MessageReq 1647 # Transaction distribution +system.membus.trans_dist::MessageResp 1647 # Transaction distribution +system.membus.trans_dist::BadAddressError 4 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769200 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1717730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1862834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538397 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20098965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730488 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484035 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1803876 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460973 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20009115 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23120585 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1616 # Total snoops (count) -system.membus.snoop_fanout::samples 1012128 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001625 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040282 # Request fanout histogram +system.membus.pkt_size::total 23030743 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1647 # Total snoops (count) +system.membus.snoop_fanout::samples 982714 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001676 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040904 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1010483 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1645 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 981067 99.83% 99.83% # Request fanout histogram +system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1012128 # Request fanout histogram -system.membus.reqLayer0.occupancy 355014500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 982714 # Request fanout histogram +system.membus.reqLayer0.occupancy 338956500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388301500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 369067500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3986356 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1012808227 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1013629759 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 5500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2339356 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2201176288 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2140696281 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 86060868 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85836693 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 41cabb250..aa0c99096 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.225369 # Number of seconds simulated -sim_ticks 5225368810000 # Number of ticks simulated -final_tick 5225368810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.221365 # Number of seconds simulated +sim_ticks 5221365015000 # Number of ticks simulated +final_tick 5221365015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187606 # Simulator instruction rate (inst/s) -host_op_rate 364338 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6433833901 # Simulator tick rate (ticks/s) -host_mem_usage 1111300 # Number of bytes of host memory used -host_seconds 812.17 # Real time elapsed on the host -sim_insts 152367765 # Number of instructions simulated -sim_ops 295904443 # Number of ops (including micro ops) simulated +host_inst_rate 248453 # Simulator instruction rate (inst/s) +host_op_rate 482434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8587928983 # Simulator tick rate (ticks/s) +host_mem_usage 826144 # Number of bytes of host memory used +host_seconds 607.99 # Real time elapsed on the host +sim_insts 151056354 # Number of instructions simulated +sim_ops 293314765 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11604096 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11604096 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9356928 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9356928 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 181314 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 181314 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 146202 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 146202 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2220723 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2220723 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1790673 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1790673 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 4011396 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 4011396 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 181314 # Number of read requests accepted -system.mem_ctrls.writeReqs 146202 # Number of write requests accepted -system.mem_ctrls.readBursts 181314 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 146202 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11574784 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 29312 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9353152 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11604096 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9356928 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 458 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 37 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11629312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11629312 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9426176 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9426176 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 181708 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 181708 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 147284 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 147284 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2227255 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2227255 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805309 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1805309 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 4032564 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4032564 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 181708 # Number of read requests accepted +system.mem_ctrls.writeReqs 147284 # Number of write requests accepted +system.mem_ctrls.readBursts 181708 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 147284 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11602944 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 26368 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9422144 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11629312 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9426176 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 412 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 11244 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 11728 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 11414 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11249 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11189 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 11530 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 10984 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10623 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 11116 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 11643 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 12156 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 12345 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 11109 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10877 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11117 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10532 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 9114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 9153 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 9190 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9432 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9109 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9160 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 8858 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8355 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8936 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 9402 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 9134 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9662 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 9149 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 9001 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9507 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 11315 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10810 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10914 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11597 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11232 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 10763 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11930 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10887 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 12498 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 12229 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 11811 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 12012 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 11054 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10768 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10809 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10667 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 10064 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 9276 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8835 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9280 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9017 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9023 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 9283 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8385 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 9360 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 9330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 9168 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9776 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 9055 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 9211 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9312 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8846 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5225368708000 # Total gap between requests +system.mem_ctrls.totGap 5221364905500 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 181314 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 181708 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 146202 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 180784 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 72 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 147284 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 181190 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 106 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2042 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2789 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8700 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9297 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8795 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9401 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9400 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8618 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9266 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9253 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8672 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8773 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8544 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8651 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8275 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8310 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8383 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 8185 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 136 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 112 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 98 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 85 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 69 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 65 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 46 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 30 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 18 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 10 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2024 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2744 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8771 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9315 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8851 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9482 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9472 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8660 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9268 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9345 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8736 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8808 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8668 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8747 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8343 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8394 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8477 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 8268 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 147 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 120 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 118 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 107 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 92 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 78 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 67 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 52 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 21 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,349 +184,355 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 59375 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 352.469423 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 208.459416 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 350.191620 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 19259 32.44% 32.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 13965 23.52% 55.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6118 10.30% 66.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3675 6.19% 72.45% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2603 4.38% 76.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1985 3.34% 80.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1578 2.66% 82.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1346 2.27% 85.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8846 14.90% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 59375 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 8143 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.209014 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 312.827272 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 8137 99.93% 99.93% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 59927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 350.843927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 206.536657 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 350.281857 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 19886 33.18% 33.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 13813 23.05% 56.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6078 10.14% 66.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3680 6.14% 72.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2560 4.27% 76.79% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2039 3.40% 80.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1649 2.75% 82.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1406 2.35% 85.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8816 14.71% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 59927 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 8212 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.072577 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 311.491456 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 8206 99.93% 99.93% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 8143 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 8143 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.947071 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.618146 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 3.900856 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 6047 74.26% 74.26% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 20 0.25% 74.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 162 1.99% 76.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 25 0.31% 76.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 47 0.58% 77.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 486 5.97% 83.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 180 2.21% 85.56% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 58 0.71% 86.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 619 7.60% 93.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 107 1.31% 95.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 5 0.06% 95.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 26 0.32% 95.57% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 281 3.45% 99.02% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 5 0.06% 99.16% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 4 0.05% 99.21% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.30% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 4 0.05% 99.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.36% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 2 0.02% 99.39% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 5 0.06% 99.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 7 0.09% 99.53% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 4 0.05% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 8 0.10% 99.68% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 5 0.06% 99.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 1 0.01% 99.75% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 2 0.02% 99.78% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 4 0.05% 99.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 4 0.05% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 3 0.04% 99.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 1 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 8143 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1912369249 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5303419249 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 904280000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10573.99 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 8212 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 8212 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.927545 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.596423 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 3.937922 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 6145 74.83% 74.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 16 0.19% 75.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 149 1.81% 76.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.24% 77.08% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 39 0.47% 77.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 481 5.86% 83.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 195 2.37% 85.79% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 59 0.72% 86.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 612 7.45% 93.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 113 1.38% 95.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 6 0.07% 95.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 284 3.46% 99.03% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 4 0.05% 99.07% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 6 0.07% 99.15% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 4 0.05% 99.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.28% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.35% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 1 0.01% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 6 0.07% 99.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 2 0.02% 99.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 6 0.07% 99.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 1 0.01% 99.60% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 8 0.10% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 2 0.02% 99.76% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 6 0.07% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 4 0.05% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::50 1 0.01% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 4 0.05% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 8212 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1926712996 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5326012996 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 906480000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10627.44 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29323.99 # Average memory access latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29377.44 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1.79 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1.79 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.23 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 146726 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 120897 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.13 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 82.71 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 15954544.84 # Average gap between requests -system.mem_ctrls.pageHitRate 81.84 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 218060640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 118981500 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 701688000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 468964080 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 341295633120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 139733284410 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3012647859750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3495184471500 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 668.887692 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5011696826000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 174486520000 # Time in different power states +system.mem_ctrls.avgWrQLen 25.95 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 146991 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 121598 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 81.08 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.58 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 15870795.96 # Average gap between requests +system.mem_ctrls.pageHitRate 81.75 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 221946480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 121101750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 697686600 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 474096240 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 341033724720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 139619979810 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3010341298500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3492509834100 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 668.889138 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5007866146000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 174352620000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 39185363500 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 39146148500 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 230814360 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 125940375 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 708981000 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 478042560 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 341295633120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 140499040365 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3011976144000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3495314595780 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 668.912595 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5010570381500 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 174486520000 # Time in different power states +system.mem_ctrls_1.actEnergy 231101640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 126097125 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 716414400 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 479895840 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 341033724720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 139466264490 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3010476136500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3492529634715 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 668.892930 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5008078591499 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 174352620000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 40311306000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 38927077251 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10450737620 # number of cpu cycles simulated +system.cpu0.numCycles 10442730030 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 133878612 # Number of instructions committed -system.cpu0.committedOps 261396254 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 242945035 # Number of integer alu accesses +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu0.committedInsts 100536790 # Number of instructions committed +system.cpu0.committedOps 194797787 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 182088702 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu0.num_func_calls 2097767 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 24690965 # number of instructions that are conditional controls -system.cpu0.num_int_insts 242945035 # number of integer instructions +system.cpu0.num_func_calls 1786032 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 17861740 # number of instructions that are conditional controls +system.cpu0.num_int_insts 182088702 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 449858957 # number of times the integer registers were read -system.cpu0.num_int_register_writes 208812254 # number of times the integer registers were written +system.cpu0.num_int_register_reads 340614933 # number of times the integer registers were read +system.cpu0.num_int_register_writes 155369927 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 139838702 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 101442019 # number of times the CC registers were written -system.cpu0.num_mem_refs 19926036 # number of memory refs -system.cpu0.num_load_insts 12901049 # Number of load instructions -system.cpu0.num_store_insts 7024987 # Number of store instructions -system.cpu0.num_idle_cycles 9874541194.502110 # Number of idle cycles -system.cpu0.num_busy_cycles 576196425.497890 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055135 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944865 # Percentage of idle cycles -system.cpu0.Branches 27504240 # Number of branches fetched -system.cpu0.op_class::No_OpClass 196451 0.08% 0.08% # Class of executed instruction -system.cpu0.op_class::IntAlu 241068901 92.22% 92.30% # Class of executed instruction -system.cpu0.op_class::IntMult 118906 0.05% 92.34% # Class of executed instruction -system.cpu0.op_class::IntDiv 91754 0.04% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatCvt 16 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::MemRead 12896145 4.93% 97.31% # Class of executed instruction -system.cpu0.op_class::MemWrite 7024987 2.69% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 104545094 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 75102328 # number of times the CC registers were written +system.cpu0.num_mem_refs 18441277 # number of memory refs +system.cpu0.num_load_insts 11598406 # Number of load instructions +system.cpu0.num_store_insts 6842871 # Number of store instructions +system.cpu0.num_idle_cycles 9945203438.030096 # Number of idle cycles +system.cpu0.num_busy_cycles 497526591.969905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047643 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952357 # Percentage of idle cycles +system.cpu0.Branches 20259437 # Number of branches fetched +system.cpu0.op_class::No_OpClass 186593 0.10% 0.10% # Class of executed instruction +system.cpu0.op_class::IntAlu 175972173 90.34% 90.43% # Class of executed instruction +system.cpu0.op_class::IntMult 117562 0.06% 90.49% # Class of executed instruction +system.cpu0.op_class::IntDiv 85263 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::MemRead 11594262 5.95% 96.49% # Class of executed instruction +system.cpu0.op_class::MemWrite 6842871 3.51% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 261397160 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu0.op_class::total 194798740 # Class of executed instruction system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10450371427 # number of cpu cycles simulated +system.cpu1.numCycles 10442397548 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18489153 # Number of instructions committed -system.cpu1.committedOps 34508189 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 33584697 # Number of integer alu accesses +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 50519564 # Number of instructions committed +system.cpu1.committedOps 98516978 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 91922994 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu1.num_func_calls 723193 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2490900 # number of instructions that are conditional controls -system.cpu1.num_int_insts 33584697 # number of integer instructions +system.cpu1.num_func_calls 994306 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9151225 # number of instructions that are conditional controls +system.cpu1.num_int_insts 91922994 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 67969193 # number of times the integer registers were read -system.cpu1.num_int_register_writes 27166606 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171998955 # number of times the integer registers were read +system.cpu1.num_int_register_writes 78483891 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 18719213 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 11481778 # number of times the CC registers were written -system.cpu1.num_mem_refs 7779481 # number of memory refs -system.cpu1.num_load_insts 4611241 # Number of load instructions -system.cpu1.num_store_insts 3168240 # Number of store instructions -system.cpu1.num_idle_cycles 10364265637.965616 # Number of idle cycles -system.cpu1.num_busy_cycles 86105789.034384 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008239 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991761 # Percentage of idle cycles -system.cpu1.Branches 3500131 # Number of branches fetched -system.cpu1.op_class::No_OpClass 130271 0.38% 0.38% # Class of executed instruction -system.cpu1.op_class::IntAlu 26481859 76.74% 77.12% # Class of executed instruction -system.cpu1.op_class::IntMult 73611 0.21% 77.33% # Class of executed instruction -system.cpu1.op_class::IntDiv 48640 0.14% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatCvt 16 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::MemRead 4606243 13.35% 90.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 3168240 9.18% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 52229827 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 37031962 # number of times the CC registers were written +system.cpu1.num_mem_refs 8648347 # number of memory refs +system.cpu1.num_load_insts 5505950 # Number of load instructions +system.cpu1.num_store_insts 3142397 # Number of store instructions +system.cpu1.num_idle_cycles 10281439289.330288 # Number of idle cycles +system.cpu1.num_busy_cycles 160958258.669712 # Number of busy cycles +system.cpu1.not_idle_fraction 0.015414 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.984586 # Percentage of idle cycles +system.cpu1.Branches 10509152 # Number of branches fetched +system.cpu1.op_class::No_OpClass 118845 0.12% 0.12% # Class of executed instruction +system.cpu1.op_class::IntAlu 89646727 91.00% 91.12% # Class of executed instruction +system.cpu1.op_class::IntMult 68401 0.07% 91.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 39477 0.04% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 16 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::MemRead 5501755 5.58% 96.81% # Class of executed instruction +system.cpu1.op_class::MemWrite 3142397 3.19% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 34508880 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 907238 # Transaction distribution -system.iobus.trans_dist::ReadResp 907238 # Transaction distribution -system.iobus.trans_dist::WriteReq 37562 # Transaction distribution -system.iobus.trans_dist::WriteResp 37562 # Transaction distribution -system.iobus.trans_dist::MessageReq 1829 # Transaction distribution -system.iobus.trans_dist::MessageResp 1829 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1740 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3426 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 46 # Packet count per connected master and slave (bytes) +system.cpu1.op_class::total 98517618 # Class of executed instruction +system.iobus.trans_dist::ReadReq 883857 # Transaction distribution +system.iobus.trans_dist::ReadResp 883857 # Transaction distribution +system.iobus.trans_dist::WriteReq 36766 # Transaction distribution +system.iobus.trans_dist::WriteResp 36766 # Transaction distribution +system.iobus.trans_dist::MessageReq 1833 # Transaction distribution +system.iobus.trans_dist::MessageResp 1833 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3418 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 712 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 74 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 943400 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 178 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1422 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 21370 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 831224 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 178 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1807714 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4706 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 32826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 674 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 32826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 5996 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 68 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4602 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 82118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1893258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3372 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4059 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 23 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1754122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12896 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 70 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 87372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1844912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6836 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 356 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 37 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 471700 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 89 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2844 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 10685 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1662442 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7234 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622534 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 356 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2157234 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2653 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 202 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16413 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1348 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 16413 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 2998 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 136 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9201 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 49372 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2213458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2100077 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 326 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15825 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15869 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52465 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2159378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9139000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9039000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 158000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 159000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 936500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 945000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 82500 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 52500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 21911000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 21127500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 471701000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1769984 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1770984 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 33004000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 31828500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 20528000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 20526000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -534,24 +540,24 @@ system.iobus.reqLayer16.occupancy 9500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 420342217 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 410368779 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 7349150 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7668139 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 1592000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2491416 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2481464 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2005792963 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1948163500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 55581972 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 60411500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -561,48 +567,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 11126779 # delay histogram for all message -system.ruby.delayHist::mean 0.431812 # delay histogram for all message -system.ruby.delayHist::stdev 1.814704 # delay histogram for all message -system.ruby.delayHist | 10527775 94.62% 94.62% | 6617 0.06% 94.68% | 590092 5.30% 99.98% | 473 0.00% 99.98% | 1712 0.02% 100.00% | 18 0.00% 100.00% | 91 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 11126779 # delay histogram for all message +system.ruby.delayHist::samples 11180744 # delay histogram for all message +system.ruby.delayHist::mean 0.431770 # delay histogram for all message +system.ruby.delayHist::stdev 1.809571 # delay histogram for all message +system.ruby.delayHist | 10577839 94.61% 94.61% | 2056 0.02% 94.63% | 600268 5.37% 99.99% | 190 0.00% 100.00% | 314 0.00% 100.00% | 12 0.00% 100.00% | 62 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 11180744 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 200336264 -system.ruby.outstanding_req_hist::mean 1.000143 -system.ruby.outstanding_req_hist::gmean 1.000099 -system.ruby.outstanding_req_hist::stdev 0.011958 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 200307614 99.99% 99.99% | 28650 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 200336264 +system.ruby.outstanding_req_hist::samples 197955014 +system.ruby.outstanding_req_hist::mean 1.000129 +system.ruby.outstanding_req_hist::gmean 1.000089 +system.ruby.outstanding_req_hist::stdev 0.011356 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 197929484 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 197955014 system.ruby.latency_hist::bucket_size 128 system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 200336263 -system.ruby.latency_hist::mean 1.335134 -system.ruby.latency_hist::gmean 1.041246 -system.ruby.latency_hist::stdev 5.048100 -system.ruby.latency_hist | 200300902 99.98% 99.98% | 26494 0.01% 100.00% | 2841 0.00% 100.00% | 3411 0.00% 100.00% | 1684 0.00% 100.00% | 871 0.00% 100.00% | 17 0.00% 100.00% | 21 0.00% 100.00% | 19 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.latency_hist::total 200336263 +system.ruby.latency_hist::samples 197955013 +system.ruby.latency_hist::mean 1.340863 +system.ruby.latency_hist::gmean 1.042158 +system.ruby.latency_hist::stdev 5.086284 +system.ruby.latency_hist | 197919444 99.98% 99.98% | 26717 0.01% 100.00% | 2924 0.00% 100.00% | 3327 0.00% 100.00% | 1642 0.00% 100.00% | 886 0.00% 100.00% | 9 0.00% 100.00% | 33 0.00% 100.00% | 23 0.00% 100.00% | 8 0.00% 100.00% +system.ruby.latency_hist::total 197955013 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 197654640 +system.ruby.hit_latency_hist::samples 195243076 system.ruby.hit_latency_hist::mean 1 system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 197654640 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 197654640 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 195243076 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 195243076 system.ruby.miss_latency_hist::bucket_size 128 system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 2681623 -system.ruby.miss_latency_hist::mean 26.036867 -system.ruby.miss_latency_hist::gmean 20.481431 -system.ruby.miss_latency_hist::stdev 35.851511 -system.ruby.miss_latency_hist | 2646262 98.68% 98.68% | 26494 0.99% 99.67% | 2841 0.11% 99.78% | 3411 0.13% 99.90% | 1684 0.06% 99.97% | 871 0.03% 100.00% | 17 0.00% 100.00% | 21 0.00% 100.00% | 19 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.miss_latency_hist::total 2681623 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 17463573 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 1589391 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 19052964 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 149306597 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 484179 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 149790776 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2711937 +system.ruby.miss_latency_hist::mean 25.880928 +system.ruby.miss_latency_hist::gmean 20.371838 +system.ruby.miss_latency_hist::stdev 35.746268 +system.ruby.miss_latency_hist | 2676368 98.69% 98.69% | 26717 0.99% 99.67% | 2924 0.11% 99.78% | 3327 0.12% 99.90% | 1642 0.06% 99.96% | 886 0.03% 100.00% | 9 0.00% 100.00% | 33 0.00% 100.00% | 23 0.00% 100.00% | 8 0.00% 100.00% +system.ruby.miss_latency_hist::total 2711937 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 16386658 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 1208703 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17595361 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 114457594 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 551051 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 115008645 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -612,13 +618,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 10 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 7462230 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 305828 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 7768058 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 23422240 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 302225 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 23724465 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 14 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 7947911 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 682965 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8630876 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 56450913 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 269218 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 56720131 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -628,605 +634,606 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2423981 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 257642 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2681623 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 14 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2479106 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 232831 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2711937 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.069248 -system.ruby.network.routers0.msg_count.Control::0 2073570 -system.ruby.network.routers0.msg_count.Request_Control::2 69104 -system.ruby.network.routers0.msg_count.Response_Data::1 2116140 -system.ruby.network.routers0.msg_count.Response_Control::1 1556339 -system.ruby.network.routers0.msg_count.Response_Control::2 1546945 -system.ruby.network.routers0.msg_count.Writeback_Data::0 396332 -system.ruby.network.routers0.msg_count.Writeback_Data::1 202 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1087870 -system.ruby.network.routers0.msg_bytes.Control::0 16588560 -system.ruby.network.routers0.msg_bytes.Request_Control::2 552832 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-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58968 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.routers4.throttle1.link_utilization 0.000227 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47550 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers4.throttle1.link_utilization 0.000228 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47555 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380440 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.096045 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 69104 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 2053248 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 1526583 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 552832 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 147833856 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 12212664 -system.ruby.network.routers6.throttle1.link_utilization 0.026791 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 63486 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 586006 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 262162 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 507888 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 42192432 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 2097296 -system.ruby.network.routers6.throttle2.link_utilization 0.060891 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2681623 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 227487 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 129144 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1826202 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 541982 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 636 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1159116 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21452984 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 16379064 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 1033152 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14609616 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 39022704 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 45792 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 9272928 -system.ruby.network.routers6.throttle3.link_utilization 0.005550 -system.ruby.network.routers6.throttle3.msg_count.Control::0 180859 -system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 101908 -system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 14542 -system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47550 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1446872 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7337376 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 116336 -system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers6.throttle0.link_utilization 0.081037 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 45501 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 1747073 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 1155797 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 364008 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 125789256 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 9246376 +system.ruby.network.routers6.throttle1.link_utilization 0.043775 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 41487 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 940552 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 636259 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 331896 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 67719744 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 5090072 +system.ruby.network.routers6.throttle2.link_utilization 0.061593 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2711937 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 208720 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+system.ruby.network.routers6.throttle3.msg_count.Control::0 181234 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 103288 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 13460 +system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47555 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1449872 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7436736 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 107680 +system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380440 system.ruby.network.routers6.throttle4.link_utilization 0.000259 -system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 814 +system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 819 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58968 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6208923 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.706330 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.282369 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5663471 91.22% 91.22% | 1771 0.03% 91.24% | 541397 8.72% 99.96% | 469 0.01% 99.97% | 1705 0.03% 100.00% | 18 0.00% 100.00% | 91 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6208923 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6276073 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.731694 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.309515 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5702895 90.87% 90.87% | 563 0.01% 90.88% | 572045 9.11% 99.99% | 184 0.00% 99.99% | 309 0.00% 100.00% | 12 0.00% 100.00% | 62 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6276073 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4785266 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.087581 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.822703 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4729884 98.84% 98.84% | 1830 0.04% 98.88% | 2212 0.05% 98.93% | 2634 0.06% 98.98% | 48164 1.01% 99.99% | 531 0.01% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4785266 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4817683 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.048845 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.619508 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4787335 99.37% 99.37% | 621 0.01% 99.38% | 650 0.01% 99.40% | 843 0.02% 99.41% | 27983 0.58% 99.99% | 240 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4817683 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 132590 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000272 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.023301 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 132572 99.99% 99.99% | 0 0.00% 99.99% | 18 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 132590 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 86988 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000184 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.019179 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 86980 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 86988 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15790582 -system.ruby.LD.latency_hist::mean 2.812687 -system.ruby.LD.latency_hist::gmean 1.304256 -system.ruby.LD.latency_hist::stdev 8.986997 -system.ruby.LD.latency_hist | 15775646 99.91% 99.91% | 12869 0.08% 99.99% | 830 0.01% 99.99% | 776 0.00% 100.00% | 352 0.00% 100.00% | 97 0.00% 100.00% | 3 0.00% 100.00% | 7 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 15790582 +system.ruby.LD.latency_hist::samples 15432046 +system.ruby.LD.latency_hist::mean 2.853578 +system.ruby.LD.latency_hist::gmean 1.313269 +system.ruby.LD.latency_hist::stdev 9.014347 +system.ruby.LD.latency_hist | 15417213 99.90% 99.90% | 12849 0.08% 99.99% | 809 0.01% 99.99% | 750 0.00% 100.00% | 322 0.00% 100.00% | 89 0.00% 100.00% | 3 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.LD.latency_hist::total 15432046 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 14360870 +system.ruby.LD.hit_latency_hist::samples 13998284 system.ruby.LD.hit_latency_hist::mean 1 system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 14360870 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 14360870 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 13998284 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13998284 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1429712 -system.ruby.LD.miss_latency_hist::mean 21.020380 -system.ruby.LD.miss_latency_hist::gmean 18.799074 -system.ruby.LD.miss_latency_hist::stdev 22.967453 -system.ruby.LD.miss_latency_hist | 1414776 98.96% 98.96% | 12869 0.90% 99.86% | 830 0.06% 99.91% | 776 0.05% 99.97% | 352 0.02% 99.99% | 97 0.01% 100.00% | 3 0.00% 100.00% | 7 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1429712 +system.ruby.LD.miss_latency_hist::samples 1433762 +system.ruby.LD.miss_latency_hist::mean 20.950658 +system.ruby.LD.miss_latency_hist::gmean 18.787895 +system.ruby.LD.miss_latency_hist::stdev 22.661921 +system.ruby.LD.miss_latency_hist | 1418929 98.97% 98.97% | 12849 0.90% 99.86% | 809 0.06% 99.92% | 750 0.05% 99.97% | 322 0.02% 99.99% | 89 0.01% 100.00% | 3 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1433762 system.ruby.ST.latency_hist::bucket_size 128 system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 9817325 -system.ruby.ST.latency_hist::mean 3.175435 -system.ruby.ST.latency_hist::gmean 1.140318 -system.ruby.ST.latency_hist::stdev 17.634571 -system.ruby.ST.latency_hist | 9803433 99.86% 99.86% | 8125 0.08% 99.94% | 1485 0.02% 99.96% | 2325 0.02% 99.98% | 1191 0.01% 99.99% | 723 0.01% 100.00% | 13 0.00% 100.00% | 12 0.00% 100.00% | 15 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.ST.latency_hist::total 9817325 +system.ruby.ST.latency_hist::samples 9612989 +system.ruby.ST.latency_hist::mean 3.237181 +system.ruby.ST.latency_hist::gmean 1.143928 +system.ruby.ST.latency_hist::stdev 17.959095 +system.ruby.ST.latency_hist | 9598428 99.85% 99.85% | 8674 0.09% 99.94% | 1607 0.02% 99.96% | 2294 0.02% 99.98% | 1185 0.01% 99.99% | 751 0.01% 100.00% | 6 0.00% 100.00% | 22 0.00% 100.00% | 16 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist::total 9612989 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9465664 +system.ruby.ST.hit_latency_hist::samples 9259406 system.ruby.ST.hit_latency_hist::mean 1 system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9465664 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9465664 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9259406 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9259406 system.ruby.ST.miss_latency_hist::bucket_size 128 system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 351661 -system.ruby.ST.miss_latency_hist::mean 61.731653 -system.ruby.ST.miss_latency_hist::gmean 39.083293 -system.ruby.ST.miss_latency_hist::stdev 71.591745 -system.ruby.ST.miss_latency_hist | 337769 96.05% 96.05% | 8125 2.31% 98.36% | 1485 0.42% 98.78% | 2325 0.66% 99.44% | 1191 0.34% 99.78% | 723 0.21% 99.99% | 13 0.00% 99.99% | 12 0.00% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 351661 +system.ruby.ST.miss_latency_hist::samples 353583 +system.ruby.ST.miss_latency_hist::mean 61.823054 +system.ruby.ST.miss_latency_hist::gmean 38.699181 +system.ruby.ST.miss_latency_hist::stdev 72.148162 +system.ruby.ST.miss_latency_hist | 339022 95.88% 95.88% | 8674 2.45% 98.34% | 1607 0.45% 98.79% | 2294 0.65% 99.44% | 1185 0.34% 99.77% | 751 0.21% 99.99% | 6 0.00% 99.99% | 22 0.01% 99.99% | 16 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 353583 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 173515241 -system.ruby.IFETCH.latency_hist::mean 1.084205 -system.ruby.IFETCH.latency_hist::gmean 1.013120 -system.ruby.IFETCH.latency_hist::stdev 1.878946 -system.ruby.IFETCH.latency_hist | 173509156 100.00% 100.00% | 5109 0.00% 100.00% | 498 0.00% 100.00% | 299 0.00% 100.00% | 130 0.00% 100.00% | 45 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 173515241 +system.ruby.IFETCH.latency_hist::samples 171728776 +system.ruby.IFETCH.latency_hist::mean 1.087723 +system.ruby.IFETCH.latency_hist::gmean 1.013813 +system.ruby.IFETCH.latency_hist::stdev 1.876064 +system.ruby.IFETCH.latency_hist | 171723049 100.00% 100.00% | 4816 0.00% 100.00% | 477 0.00% 100.00% | 266 0.00% 100.00% | 120 0.00% 100.00% | 39 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 171728776 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 172728837 +system.ruby.IFETCH.hit_latency_hist::samples 170908507 system.ruby.IFETCH.hit_latency_hist::mean 1 system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 172728837 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 172728837 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 170908507 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 170908507 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 786404 -system.ruby.IFETCH.miss_latency_hist::mean 19.579326 -system.ruby.IFETCH.miss_latency_hist::gmean 17.745067 -system.ruby.IFETCH.miss_latency_hist::stdev 20.864873 -system.ruby.IFETCH.miss_latency_hist | 780319 99.23% 99.23% | 5109 0.65% 99.88% | 498 0.06% 99.94% | 299 0.04% 99.98% | 130 0.02% 99.99% | 45 0.01% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 786404 +system.ruby.IFETCH.miss_latency_hist::samples 820269 +system.ruby.IFETCH.miss_latency_hist::mean 19.365461 +system.ruby.IFETCH.miss_latency_hist::gmean 17.675024 +system.ruby.IFETCH.miss_latency_hist::stdev 20.029392 +system.ruby.IFETCH.miss_latency_hist | 814542 99.30% 99.30% | 4816 0.59% 99.89% | 477 0.06% 99.95% | 266 0.03% 99.98% | 120 0.01% 99.99% | 39 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 820269 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 523939 -system.ruby.RMW_Read.latency_hist::mean 4.129191 -system.ruby.RMW_Read.latency_hist::gmean 1.527796 -system.ruby.RMW_Read.latency_hist::stdev 10.162632 -system.ruby.RMW_Read.latency_hist | 523754 99.96% 99.96% | 145 0.03% 99.99% | 18 0.00% 100.00% | 9 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 523939 +system.ruby.RMW_Read.latency_hist::samples 500824 +system.ruby.RMW_Read.latency_hist::mean 4.015684 +system.ruby.RMW_Read.latency_hist::gmean 1.504004 +system.ruby.RMW_Read.latency_hist::stdev 10.245462 +system.ruby.RMW_Read.latency_hist | 500634 99.96% 99.96% | 144 0.03% 99.99% | 19 0.00% 99.99% | 11 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 500824 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 452465 +system.ruby.RMW_Read.hit_latency_hist::samples 434823 system.ruby.RMW_Read.hit_latency_hist::mean 1 system.ruby.RMW_Read.hit_latency_hist::gmean 1 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 452465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 452465 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 434823 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 434823 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 71474 -system.ruby.RMW_Read.miss_latency_hist::mean 23.938481 -system.ruby.RMW_Read.miss_latency_hist::gmean 22.350533 -system.ruby.RMW_Read.miss_latency_hist::stdev 17.398088 -system.ruby.RMW_Read.miss_latency_hist | 71289 99.74% 99.74% | 145 0.20% 99.94% | 18 0.03% 99.97% | 9 0.01% 99.98% | 8 0.01% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 71474 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.latency_hist::samples 344588 -system.ruby.Locked_RMW_Read.latency_hist::mean 3.637196 -system.ruby.Locked_RMW_Read.latency_hist::gmean 1.457387 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.622051 -system.ruby.Locked_RMW_Read.latency_hist | 344325 99.92% 99.92% | 246 0.07% 100.00% | 10 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 344588 +system.ruby.RMW_Read.miss_latency_hist::samples 66001 +system.ruby.RMW_Read.miss_latency_hist::mean 23.883396 +system.ruby.RMW_Read.miss_latency_hist::gmean 22.130353 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.490127 +system.ruby.RMW_Read.miss_latency_hist | 65811 99.71% 99.71% | 144 0.22% 99.93% | 19 0.03% 99.96% | 11 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 66001 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.latency_hist::samples 340189 +system.ruby.Locked_RMW_Read.latency_hist::mean 3.322441 +system.ruby.Locked_RMW_Read.latency_hist::gmean 1.405056 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.375867 +system.ruby.Locked_RMW_Read.latency_hist | 339841 99.90% 99.90% | 90 0.03% 99.92% | 233 0.07% 99.99% | 1 0.00% 99.99% | 4 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 340189 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 302216 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301867 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 1 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 1 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 302216 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 302216 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 42372 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.446852 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 21.392577 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.183059 -system.ruby.Locked_RMW_Read.miss_latency_hist | 42109 99.38% 99.38% | 246 0.58% 99.96% | 10 0.02% 99.98% | 2 0.00% 99.99% | 3 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 42372 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 301867 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38322 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 21.616591 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 20.468877 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.672180 +system.ruby.Locked_RMW_Read.miss_latency_hist | 37974 99.09% 99.09% | 90 0.23% 99.33% | 233 0.61% 99.93% | 1 0.00% 99.94% | 4 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 38322 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 344588 +system.ruby.Locked_RMW_Write.latency_hist::samples 340189 system.ruby.Locked_RMW_Write.latency_hist::mean 1 system.ruby.Locked_RMW_Write.latency_hist::gmean 1 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 344588 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 344588 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 340189 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 344588 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 340189 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 1 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 1 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 344588 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 344588 -system.ruby.Directory_Controller.Fetch 180859 0.00% 0.00% -system.ruby.Directory_Controller.Data 101908 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 181314 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 146202 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 340189 +system.ruby.Directory_Controller.Fetch 181234 0.00% 0.00% +system.ruby.Directory_Controller.Data 103288 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 181708 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 147284 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 819 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 14542 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 180859 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 455 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 44294 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 455 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 44294 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 99107 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 359 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 2442 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 14542 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 180859 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 99107 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 359 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 359 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 2442 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2442 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 814 +system.ruby.Directory_Controller.CleanReplacement 13460 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 181234 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 474 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 43996 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 474 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 43996 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 100203 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 2740 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 13460 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 181234 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 100203 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 2740 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2740 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 819 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 814 +system.ruby.DMA_Controller.Data | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 819 system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 814 +system.ruby.DMA_Controller.READY.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 819 system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 814 +system.ruby.DMA_Controller.BUSY_RD.Data | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 819 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 11499254 72.82% 72.82% | 4291328 27.18% 100.00% -system.ruby.L1Cache_Controller.Load::total 15790582 -system.ruby.L1Cache_Controller.Ifetch | 149790779 86.33% 86.33% | 23724467 13.67% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 173515246 -system.ruby.L1Cache_Controller.Store | 7553710 68.48% 68.48% | 3476730 31.52% 100.00% -system.ruby.L1Cache_Controller.Store::total 11030440 -system.ruby.L1Cache_Controller.Inv | 29958 53.68% 53.68% | 25849 46.32% 100.00% -system.ruby.L1Cache_Controller.Inv::total 55807 -system.ruby.L1Cache_Controller.L1_Replacement | 2028024 78.37% 78.37% | 559829 21.63% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2587853 -system.ruby.L1Cache_Controller.Fwd_GETX | 15400 51.07% 51.07% | 14755 48.93% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 30155 -system.ruby.L1Cache_Controller.Fwd_GETS | 23742 50.92% 50.92% | 22882 49.08% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 46624 +system.ruby.L1Cache_Controller.Load | 10196157 66.07% 66.07% | 5235889 33.93% 100.00% +system.ruby.L1Cache_Controller.Load::total 15432046 +system.ruby.L1Cache_Controller.Ifetch | 115008649 66.97% 66.97% | 56720132 33.03% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 171728781 +system.ruby.L1Cache_Controller.Store | 7399204 68.55% 68.55% | 3394987 31.45% 100.00% +system.ruby.L1Cache_Controller.Store::total 10794191 +system.ruby.L1Cache_Controller.Inv | 18502 52.28% 52.28% | 16889 47.72% 100.00% +system.ruby.L1Cache_Controller.Inv::total 35391 +system.ruby.L1Cache_Controller.L1_Replacement | 1730094 65.23% 65.23% | 922339 34.77% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2652433 +system.ruby.L1Cache_Controller.Fwd_GETX | 12336 51.16% 51.16% | 11775 48.84% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 24111 +system.ruby.L1Cache_Controller.Fwd_GETS | 14659 53.34% 53.34% | 12823 46.66% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 27482 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 1737 59.71% 59.71% | 1172 40.29% 100.00% -system.ruby.L1Cache_Controller.Data::total 2909 -system.ruby.L1Cache_Controller.Data_Exclusive | 1207088 91.86% 91.86% | 106979 8.14% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1314067 -system.ruby.L1Cache_Controller.DataS_fromL1 | 22882 49.07% 49.07% | 23746 50.93% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 46628 -system.ruby.L1Cache_Controller.Data_all_Acks | 821541 64.40% 64.40% | 454109 35.60% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1275650 -system.ruby.L1Cache_Controller.Ack | 20322 47.96% 47.96% | 22047 52.04% 100.00% -system.ruby.L1Cache_Controller.Ack::total 42369 -system.ruby.L1Cache_Controller.Ack_all | 22059 48.72% 48.72% | 23219 51.28% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 45278 -system.ruby.L1Cache_Controller.WB_Ack | 1484202 87.25% 87.25% | 216896 12.75% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1701098 -system.ruby.L1Cache_Controller.NP.Load | 1255942 89.89% 89.89% | 141182 10.11% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1397124 -system.ruby.L1Cache_Controller.NP.Ifetch | 483731 61.58% 61.58% | 301770 38.42% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 785501 -system.ruby.L1Cache_Controller.NP.Store | 289373 71.05% 71.05% | 117901 28.95% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 407274 -system.ruby.L1Cache_Controller.NP.Inv | 6783 68.15% 68.15% | 3170 31.85% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 9953 -system.ruby.L1Cache_Controller.I.Load | 16474 50.55% 50.55% | 16114 49.45% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 32588 -system.ruby.L1Cache_Controller.I.Ifetch | 448 49.61% 49.61% | 455 50.39% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 903 -system.ruby.L1Cache_Controller.I.Store | 7275 45.88% 45.88% | 8582 54.12% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 15857 -system.ruby.L1Cache_Controller.I.L1_Replacement | 14373 54.06% 54.06% | 12212 45.94% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 26585 -system.ruby.L1Cache_Controller.S.Load | 942765 61.54% 61.54% | 589150 38.46% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1531915 -system.ruby.L1Cache_Controller.S.Ifetch | 149306597 86.44% 86.44% | 23422240 13.56% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 172728837 -system.ruby.L1Cache_Controller.S.Store | 20327 47.97% 47.97% | 22049 52.03% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 42376 -system.ruby.L1Cache_Controller.S.Inv | 22933 51.00% 51.00% | 22033 49.00% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 44966 -system.ruby.L1Cache_Controller.S.L1_Replacement | 529449 61.55% 61.55% | 330721 38.45% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 860170 -system.ruby.L1Cache_Controller.E.Load | 2977799 80.56% 80.56% | 718721 19.44% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3696520 -system.ruby.L1Cache_Controller.E.Store | 117327 77.49% 77.49% | 34087 22.51% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 151414 -system.ruby.L1Cache_Controller.E.Inv | 35 14.29% 14.29% | 210 85.71% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 245 -system.ruby.L1Cache_Controller.E.L1_Replacement | 1087870 93.85% 93.85% | 71246 6.15% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1159116 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 218 60.56% 60.56% | 142 39.44% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 360 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 1426 54.02% 54.02% | 1214 45.98% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2640 -system.ruby.L1Cache_Controller.M.Load | 6306274 69.05% 69.05% | 2826161 30.95% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 9132435 -system.ruby.L1Cache_Controller.M.Store | 7119408 68.37% 68.37% | 3294111 31.63% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10413519 -system.ruby.L1Cache_Controller.M.Inv | 202 31.76% 31.76% | 434 68.24% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 636 -system.ruby.L1Cache_Controller.M.L1_Replacement | 396332 73.13% 73.13% | 145650 26.87% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 541982 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 15182 50.95% 50.95% | 14613 49.05% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 29795 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 22316 50.74% 50.74% | 21668 49.26% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 43984 +system.ruby.L1Cache_Controller.Data | 528 32.39% 32.39% | 1102 67.61% 100.00% +system.ruby.L1Cache_Controller.Data::total 1630 +system.ruby.L1Cache_Controller.Data_Exclusive | 840504 62.87% 62.87% | 496438 37.13% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1336942 +system.ruby.L1Cache_Controller.DataS_fromL1 | 12823 46.65% 46.65% | 14663 53.35% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 27486 +system.ruby.L1Cache_Controller.Data_all_Acks | 893218 67.59% 67.59% | 428349 32.41% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1321567 +system.ruby.L1Cache_Controller.Ack | 12681 52.16% 52.16% | 11631 47.84% 100.00% +system.ruby.L1Cache_Controller.Ack::total 24312 +system.ruby.L1Cache_Controller.Ack_all | 13209 50.92% 50.92% | 12733 49.08% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 25942 +system.ruby.L1Cache_Controller.WB_Ack | 1129907 64.87% 64.87% | 611895 35.13% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1741802 +system.ruby.L1Cache_Controller.NP.Load | 881473 62.40% 62.40% | 531116 37.60% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1412589 +system.ruby.L1Cache_Controller.NP.Ifetch | 550888 67.18% 67.18% | 269077 32.82% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 819965 +system.ruby.L1Cache_Controller.NP.Store | 298756 70.81% 70.81% | 123170 29.19% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 421926 +system.ruby.L1Cache_Controller.NP.Inv | 5771 62.78% 62.78% | 3422 37.22% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 9193 +system.ruby.L1Cache_Controller.I.Load | 10081 47.61% 47.61% | 11092 52.39% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 21173 +system.ruby.L1Cache_Controller.I.Ifetch | 163 53.62% 53.62% | 141 46.38% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 304 +system.ruby.L1Cache_Controller.I.Store | 5712 48.96% 48.96% | 5955 51.04% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11667 +system.ruby.L1Cache_Controller.I.L1_Replacement | 9111 53.32% 53.32% | 7975 46.68% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17086 +system.ruby.L1Cache_Controller.S.Load | 850617 63.10% 63.10% | 497429 36.90% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1348046 +system.ruby.L1Cache_Controller.S.Ifetch | 114457594 66.97% 66.97% | 56450913 33.03% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 170908507 +system.ruby.L1Cache_Controller.S.Store | 12681 52.16% 52.16% | 11632 47.84% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 24313 +system.ruby.L1Cache_Controller.S.Inv | 12466 48.73% 48.73% | 13117 51.27% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 25583 +system.ruby.L1Cache_Controller.S.L1_Replacement | 591076 66.15% 66.15% | 302469 33.85% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 893545 +system.ruby.L1Cache_Controller.E.Load | 2398204 64.14% 64.14% | 1340570 35.86% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3738774 +system.ruby.L1Cache_Controller.E.Store | 120081 73.14% 73.14% | 44106 26.86% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 164187 +system.ruby.L1Cache_Controller.E.Inv | 72 60.00% 60.00% | 48 40.00% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 120 +system.ruby.L1Cache_Controller.E.L1_Replacement | 718896 61.46% 61.46% | 450874 38.54% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1169770 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 233 64.01% 64.01% | 131 35.99% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 364 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 1000 46.06% 46.06% | 1171 53.94% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2171 +system.ruby.L1Cache_Controller.M.Load | 6055782 67.95% 67.95% | 2855682 32.05% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8911464 +system.ruby.L1Cache_Controller.M.Store | 6961974 68.44% 68.44% | 3210124 31.56% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10172098 +system.ruby.L1Cache_Controller.M.Inv | 193 39.07% 39.07% | 301 60.93% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 494 +system.ruby.L1Cache_Controller.M.L1_Replacement | 411011 71.85% 71.85% | 161021 28.15% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 572032 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 12103 50.97% 50.97% | 11644 49.03% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23747 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13659 53.96% 53.96% | 11652 46.04% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 25311 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 1207088 91.86% 91.86% | 106979 8.14% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1314067 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 22882 49.07% 49.07% | 23746 50.93% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 46628 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 526625 61.56% 61.56% | 328796 38.44% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 855421 -system.ruby.L1Cache_Controller.IM.Data | 1737 59.71% 59.71% | 1172 40.29% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 2909 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 294916 70.18% 70.18% | 125313 29.82% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 420229 -system.ruby.L1Cache_Controller.SM.Inv | 5 71.43% 71.43% | 2 28.57% 100.00% -system.ruby.L1Cache_Controller.SM.Inv::total 7 -system.ruby.L1Cache_Controller.SM.Ack | 20322 47.96% 47.96% | 22047 52.04% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 42369 -system.ruby.L1Cache_Controller.SM.Ack_all | 22059 48.72% 48.72% | 23219 51.28% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 45278 -system.ruby.L1Cache_Controller.M_I.Ifetch | 3 60.00% 60.00% | 2 40.00% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 840504 62.87% 62.87% | 496438 37.13% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1336942 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 12823 46.65% 46.65% | 14663 53.35% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 27486 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 589278 66.24% 66.24% | 300325 33.76% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 889603 +system.ruby.L1Cache_Controller.IM.Data | 528 32.39% 32.39% | 1102 67.61% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1630 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 303940 70.36% 70.36% | 128024 29.64% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431964 +system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.SM.Inv::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 12681 52.16% 52.16% | 11631 47.84% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 24312 +system.ruby.L1Cache_Controller.SM.Ack_all | 13209 50.92% 50.92% | 12733 49.08% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 25942 +system.ruby.L1Cache_Controller.M_I.Ifetch | 4 80.00% 80.00% | 1 20.00% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 5 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 1484202 87.25% 87.25% | 216896 12.75% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1701098 -system.ruby.L2Cache_Controller.L1_GET_INSTR 786404 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1430091 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 423139 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 42377 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1701098 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 98966 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 14683 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 180859 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 116450 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 44624 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2640 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 2261 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7632 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 46628 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1779574 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 5602 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15956 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 33107 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 131796 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 770425 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 69021 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 3068 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 42369 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 213 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7168 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 19 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1280960 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 258119 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 98446 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7182 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 2554 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 1129907 64.87% 64.87% | 611895 35.13% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1741802 +system.ruby.L2Cache_Controller.L1_GET_INSTR 820269 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1434154 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 433597 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 24313 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1741802 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 100151 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 13512 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 181234 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 116748 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 25809 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2171 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1865 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7090 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 27486 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1794848 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 6170 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15428 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 32321 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 133485 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 804811 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 69338 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1923 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 24312 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 291 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6674 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 5 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1304621 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 274075 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 99609 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6704 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 2851 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 46624 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 30155 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1701098 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 307 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 333 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 241 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 116450 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 2554 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 495 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 53 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 241 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 141 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 192 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 2043 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7168 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 218 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 219 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 6 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 33107 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 15956 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 131796 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 233 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 7 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 45437 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 146 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1734137 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 43981 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2640 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 46621 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 27482 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 24111 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1741802 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 251 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 134 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 229 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 116748 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 2851 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 442 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 38 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 229 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 52 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 82 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1570 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 6674 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 295 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 296 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 5 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 32321 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 15428 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 133485 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 235 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26235 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 157 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768613 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25310 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2170 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 27480 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 4fb206696..d9f455151 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.141985 # Number of seconds simulated -sim_ticks 5141984685500 # Number of ticks simulated -final_tick 5141984685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.140310 # Number of seconds simulated +sim_ticks 5140310078000 # Number of ticks simulated +final_tick 5140310078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264541 # Simulator instruction rate (inst/s) -host_op_rate 525842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5597553756 # Simulator tick rate (ticks/s) -host_mem_usage 1010248 # Number of bytes of host memory used -host_seconds 918.61 # Real time elapsed on the host -sim_insts 243010444 # Number of instructions simulated -sim_ops 483045307 # Number of ops (including micro ops) simulated +host_inst_rate 269101 # Simulator instruction rate (inst/s) +host_op_rate 534933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5691143534 # Simulator tick rate (ticks/s) +host_mem_usage 1043812 # Number of bytes of host memory used +host_seconds 903.21 # Real time elapsed on the host +sim_insts 243055556 # Number of instructions simulated +sim_ops 483158347 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 439936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4996672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 212288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2043456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 288960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3313664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 444224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5333440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1822656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 355648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3199424 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11325056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 439936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 212288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 288960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 941184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9131200 # Number of bytes written to this memory -system.physmem.bytes_written::total 9131200 # Number of bytes written to this memory +system.physmem.bytes_read::total 11343552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 444224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 355648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 957376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9153408 # Number of bytes written to this memory +system.physmem.bytes_written::total 9153408 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6874 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 31929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4515 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 51776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 83335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 49991 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176954 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142675 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142675 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177243 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143022 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143022 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 85558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 971740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 397406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 56196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 644433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2202468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 85558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 56196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 183039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1775812 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1775812 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1775812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 86420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1037572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 354581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 69188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 622418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2206784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 69188 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 186249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1780711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1780711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1780711 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 85558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 971740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 397406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 56196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 644433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3978280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 91559 # Number of read requests accepted -system.physmem.writeReqs 81706 # Number of write requests accepted -system.physmem.readBursts 91559 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 81706 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5853184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 5229184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5859776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5229184 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 86420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1037572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 354581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 69188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 622418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3987495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 86962 # Number of read requests accepted +system.physmem.writeReqs 83127 # Number of write requests accepted +system.physmem.readBursts 86962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83127 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5558208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 5320128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5565568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5320128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 24142 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5703 # Per bank write bursts -system.physmem.perBankRdBursts::1 4852 # Per bank write bursts -system.physmem.perBankRdBursts::2 5373 # Per bank write bursts -system.physmem.perBankRdBursts::3 5511 # Per bank write bursts -system.physmem.perBankRdBursts::4 5930 # Per bank write bursts -system.physmem.perBankRdBursts::5 4999 # Per bank write bursts -system.physmem.perBankRdBursts::6 5647 # Per bank write bursts -system.physmem.perBankRdBursts::7 5865 # Per bank write bursts -system.physmem.perBankRdBursts::8 5509 # Per bank write bursts -system.physmem.perBankRdBursts::9 5229 # Per bank write bursts -system.physmem.perBankRdBursts::10 5185 # Per bank write bursts -system.physmem.perBankRdBursts::11 5201 # Per bank write bursts -system.physmem.perBankRdBursts::12 6216 # Per bank write bursts -system.physmem.perBankRdBursts::13 6911 # Per bank write bursts -system.physmem.perBankRdBursts::14 6949 # Per bank write bursts -system.physmem.perBankRdBursts::15 6376 # Per bank write bursts -system.physmem.perBankWrBursts::0 5797 # Per bank write bursts -system.physmem.perBankWrBursts::1 4843 # Per bank write bursts -system.physmem.perBankWrBursts::2 5036 # Per bank write bursts -system.physmem.perBankWrBursts::3 5163 # Per bank write bursts -system.physmem.perBankWrBursts::4 5363 # Per bank write bursts -system.physmem.perBankWrBursts::5 4815 # Per bank write bursts -system.physmem.perBankWrBursts::6 4988 # Per bank write bursts -system.physmem.perBankWrBursts::7 5321 # Per bank write bursts -system.physmem.perBankWrBursts::8 4852 # Per bank write bursts -system.physmem.perBankWrBursts::9 4657 # Per bank write bursts -system.physmem.perBankWrBursts::10 4410 # Per bank write bursts -system.physmem.perBankWrBursts::11 4367 # Per bank write bursts -system.physmem.perBankWrBursts::12 5498 # Per bank write bursts -system.physmem.perBankWrBursts::13 5314 # Per bank write bursts -system.physmem.perBankWrBursts::14 5778 # Per bank write bursts -system.physmem.perBankWrBursts::15 5504 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 33935 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5197 # Per bank write bursts +system.physmem.perBankRdBursts::1 4660 # Per bank write bursts +system.physmem.perBankRdBursts::2 5410 # Per bank write bursts +system.physmem.perBankRdBursts::3 5303 # Per bank write bursts +system.physmem.perBankRdBursts::4 5131 # Per bank write bursts +system.physmem.perBankRdBursts::5 4781 # Per bank write bursts +system.physmem.perBankRdBursts::6 5593 # Per bank write bursts +system.physmem.perBankRdBursts::7 5451 # Per bank write bursts +system.physmem.perBankRdBursts::8 5257 # Per bank write bursts +system.physmem.perBankRdBursts::9 4895 # Per bank write bursts +system.physmem.perBankRdBursts::10 5205 # Per bank write bursts +system.physmem.perBankRdBursts::11 5208 # Per bank write bursts +system.physmem.perBankRdBursts::12 5485 # Per bank write bursts +system.physmem.perBankRdBursts::13 6574 # Per bank write bursts +system.physmem.perBankRdBursts::14 6603 # Per bank write bursts +system.physmem.perBankRdBursts::15 6094 # Per bank write bursts +system.physmem.perBankWrBursts::0 5588 # Per bank write bursts +system.physmem.perBankWrBursts::1 5124 # Per bank write bursts +system.physmem.perBankWrBursts::2 5267 # Per bank write bursts +system.physmem.perBankWrBursts::3 4836 # Per bank write bursts +system.physmem.perBankWrBursts::4 5431 # Per bank write bursts +system.physmem.perBankWrBursts::5 5206 # Per bank write bursts +system.physmem.perBankWrBursts::6 5103 # Per bank write bursts +system.physmem.perBankWrBursts::7 5105 # Per bank write bursts +system.physmem.perBankWrBursts::8 5093 # Per bank write bursts +system.physmem.perBankWrBursts::9 5184 # Per bank write bursts +system.physmem.perBankWrBursts::10 5317 # Per bank write bursts +system.physmem.perBankWrBursts::11 5091 # Per bank write bursts +system.physmem.perBankWrBursts::12 4613 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5354 # Per bank write bursts +system.physmem.perBankWrBursts::15 5452 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5140984417000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 5136428746000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 91559 # Read request sizes (log2) +system.physmem.readPktSize::6 86962 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 81706 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 86389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an 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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -161,1114 +161,1119 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 53 # What 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129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 92 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 276.476998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.125046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 300.303961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15966 39.83% 39.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9813 24.48% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4306 10.74% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2350 5.86% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1723 4.30% 85.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1131 2.82% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 740 1.85% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 595 1.48% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3460 8.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40084 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.316984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 232.117398 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4096 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39704 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 273.985896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.719261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.548634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16089 40.52% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9815 24.72% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4115 10.36% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2259 5.69% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1546 3.89% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1077 2.71% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 717 1.81% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 581 1.46% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3505 8.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39704 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4014 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.636024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.585773 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4011 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4098 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.938019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.673577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.950142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 4 0.10% 1.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.07% 1.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 4 0.10% 1.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3475 84.80% 86.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 74 1.81% 88.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.68% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 103 2.51% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 14 0.34% 92.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 88 2.15% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 1.10% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.12% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.20% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.20% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.10% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 126 3.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 13 0.32% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.05% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.37% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4098 # Writes before turning the bus around for reads -system.physmem.totQLat 1118460500 # Total ticks spent queuing -system.physmem.totMemAccLat 2833260500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 457280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12229.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4014 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4014 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.709268 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.149216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.865339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 66 1.64% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 4 0.10% 1.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.12% 1.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3286 81.86% 83.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 102 2.54% 86.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.77% 87.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 110 2.74% 89.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 16 0.40% 90.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 107 2.67% 92.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 56 1.40% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.07% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.30% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.50% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.10% 95.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 148 3.69% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.10% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 15 0.37% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.25% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4014 # Writes before turning the bus around for reads +system.physmem.totQLat 1058164225 # Total ticks spent queuing +system.physmem.totMemAccLat 2686545475 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 434235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12184.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30979.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30934.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.88 # Average write queue length when enqueuing -system.physmem.readRowHits 73104 # Number of row buffer hits during reads -system.physmem.writeRowHits 59973 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.40 # Row buffer hit rate for writes -system.physmem.avgGap 29671222.79 # Average gap between requests -system.physmem.pageHitRate 76.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 146323800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 79666125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 342256200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 267792480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96409908585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2240143266750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2587784324100 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.897651 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3686083069500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128013860000 # Time in different power states +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing +system.physmem.readRowHits 68775 # Number of row buffer hits during reads +system.physmem.writeRowHits 61495 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.98 # Row buffer hit rate for writes +system.physmem.avgGap 30198476.95 # Average gap between requests +system.physmem.pageHitRate 76.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 145461960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79191750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 323902800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 269956800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96312598470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2240118682500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2587633207560 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.890236 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3686035921978 # Time in different power states +system.physmem_0.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19995411750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19846503022 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 156711240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 371092800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 261662400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96741256995 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2232099467250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580110601720 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.145421 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3685614437250 # Time in different power states -system.physmem_1.memoryStateTime::REF 128013860000 # Time in different power states +system.physmem_1.actEnergy 154700280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 84191250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 353503800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 268706160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96598721655 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2233305647250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2581148883675 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.102542 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685636098978 # Time in different power states +system.physmem_1.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 20427995000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20213469772 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1069587616 # number of cpu cycles simulated +system.cpu0.numCycles 1072285216 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72296493 # Number of instructions committed -system.cpu0.committedOps 147472982 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 135372886 # Number of integer alu accesses +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu0.committedInsts 71949475 # Number of instructions committed +system.cpu0.committedOps 146629560 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134558001 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 990052 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14329607 # number of instructions that are conditional controls -system.cpu0.num_int_insts 135372886 # number of integer instructions +system.cpu0.num_func_calls 963710 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14252688 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134558001 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 248231827 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116398223 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246915369 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115616478 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84256506 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56232303 # number of times the CC registers were written -system.cpu0.num_mem_refs 13832544 # number of memory refs -system.cpu0.num_load_insts 10299641 # Number of load instructions -system.cpu0.num_store_insts 3532903 # Number of store instructions -system.cpu0.num_idle_cycles 1014098909.517961 # Number of idle cycles -system.cpu0.num_busy_cycles 55488706.482039 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051879 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948121 # Percentage of idle cycles -system.cpu0.Branches 15685270 # Number of branches fetched -system.cpu0.op_class::No_OpClass 94460 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 133436032 90.48% 90.55% # Class of executed instruction -system.cpu0.op_class::IntMult 61341 0.04% 90.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 50787 0.03% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::MemRead 10297804 6.98% 97.60% # Class of executed instruction -system.cpu0.op_class::MemWrite 3532903 2.40% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83804950 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55920141 # number of times the CC registers were written +system.cpu0.num_mem_refs 13826864 # number of memory refs +system.cpu0.num_load_insts 10217566 # Number of load instructions +system.cpu0.num_store_insts 3609298 # Number of store instructions +system.cpu0.num_idle_cycles 1017808473.109560 # Number of idle cycles +system.cpu0.num_busy_cycles 54476742.890440 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050804 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949196 # Percentage of idle cycles +system.cpu0.Branches 15573120 # Number of branches fetched +system.cpu0.op_class::No_OpClass 93860 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132602493 90.43% 90.50% # Class of executed instruction +system.cpu0.op_class::IntMult 58992 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 49730 0.03% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::MemRead 10215736 6.97% 97.54% # Class of executed instruction +system.cpu0.op_class::MemWrite 3609298 2.46% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 147473327 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1636478 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19597198 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1636990 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.971483 # Average number of references to valid blocks. +system.cpu0.op_class::total 146630109 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1637599 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999082 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19598772 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638111 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.964252 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.606115 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 212.665668 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 114.727666 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360559 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.415363 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.224077 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.195837 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.604771 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.198475 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359757 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.413291 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.226950 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999998 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 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-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25498.631942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21070.576359 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22327.586459 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165093.568626 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161532.150918 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163230.829407 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183188.649425 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211831.864905 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 193783.994206 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165427.585585 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162033.525890 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163659.674907 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1548077 # number of writebacks +system.cpu0.dcache.writebacks::total 1548077 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 363716 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363786 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1660 # number of WriteReq MSHR hits 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MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 673827500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 612020000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1285847500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31349278500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33610785500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64960064000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060083 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086633 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045028 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031715 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031991 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018219 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.857969 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855500 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.527018 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048793 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034382 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061648 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086356 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044992 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13641.719268 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14358.953550 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14167.589917 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57260.664202 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59756.737817 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17234.946017 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15840.999807 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.262473 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26774.032837 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22564.776866 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23760.957756 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24664.978614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20789.829109 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21846.972837 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.868883 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.203532 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212802.503477 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201859.890110 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.088453 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172666.018107 # average overall mshr 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MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2260578000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5251926966 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7512504966 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004145 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004145 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004145 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13912.123523 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608369012 # number of cpu cycles simulated +system.cpu1.numCycles 2606017772 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35935781 # Number of instructions committed -system.cpu1.committedOps 69853480 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64823976 # Number of integer alu accesses +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 35434797 # Number of instructions committed +system.cpu1.committedOps 68967057 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63950611 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 488968 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6599189 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64823976 # number of integer instructions +system.cpu1.num_func_calls 471158 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6540301 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63950611 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120030856 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55861909 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118144126 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55187106 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36569866 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27235503 # number of times the CC registers were written -system.cpu1.num_mem_refs 4739526 # number of memory refs -system.cpu1.num_load_insts 2929606 # Number of load instructions -system.cpu1.num_store_insts 1809920 # Number of store instructions -system.cpu1.num_idle_cycles 2476291441.144386 # Number of idle cycles -system.cpu1.num_busy_cycles 132077570.855614 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050636 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949364 # Percentage of idle cycles -system.cpu1.Branches 7267259 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35769 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 65023245 93.08% 93.14% # Class of executed instruction -system.cpu1.op_class::IntMult 31643 0.05% 93.18% # Class of executed instruction -system.cpu1.op_class::IntDiv 24977 0.04% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::MemRead 2928241 4.19% 97.41% # Class of executed instruction -system.cpu1.op_class::MemWrite 1809920 2.59% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36132535 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26987071 # number of times the CC registers were written +system.cpu1.num_mem_refs 4484181 # number of memory refs +system.cpu1.num_load_insts 2795215 # Number of load instructions +system.cpu1.num_store_insts 1688966 # Number of store instructions +system.cpu1.num_idle_cycles 2475079667.780020 # Number of idle cycles +system.cpu1.num_busy_cycles 130938104.219980 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050245 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949755 # Percentage of idle cycles +system.cpu1.Branches 7181908 # Number of branches fetched +system.cpu1.op_class::No_OpClass 31577 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64398957 93.38% 93.42% # Class of executed instruction +system.cpu1.op_class::IntMult 30119 0.04% 93.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 23752 0.03% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::MemRead 2793855 4.05% 97.55% # Class of executed instruction +system.cpu1.op_class::MemWrite 1688966 2.45% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69853795 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28595724 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28595724 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 274281 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 25954960 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25419524 # Number of BTB hits +system.cpu1.op_class::total 68967226 # Class of executed instruction +system.cpu2.branchPred.lookups 28923329 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28923329 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 299282 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26177543 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25594622 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.937057 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 541766 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 58217 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155590039 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.773202 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 576797 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63162 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157005453 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9827756 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141445049 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28595724 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 25961290 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144324316 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 577708 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 89529 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 4628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9926 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 52140 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 25 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1381 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3207378 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 141789 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2491 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154597903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.800587 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.004500 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10540975 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142872413 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28923329 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26171419 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 144748563 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 631577 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 103277 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7821 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 68344 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1893 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3422619 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 155063 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 155796605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.805087 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.007326 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 100285595 64.87% 64.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 850088 0.55% 65.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23359910 15.11% 80.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 558025 0.36% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 768716 0.50% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 809103 0.52% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 512827 0.33% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 703407 0.45% 82.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 26750232 17.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 100986274 64.82% 64.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 876971 0.56% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23450168 15.05% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 581136 0.37% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 798057 0.51% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 839354 0.54% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 536255 0.34% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 727896 0.47% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27000494 17.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154597903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.183789 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909088 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8590820 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95748375 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 20322096 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4023271 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 289506 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 275783905 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 289506 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10203934 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77122652 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4692669 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 22463307 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14202064 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 274713209 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 193941 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5398657 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 70031 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 7189088 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 328421156 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 598952608 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 367856783 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 202 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 317944423 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10476733 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 154897 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 156262 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19984245 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6287198 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3639298 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 400920 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 367403 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 273029174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 403661 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 271361789 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 92310 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7713990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11716947 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 58327 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154597903 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.755275 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.385225 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 155796605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184219 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.909984 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9166270 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95860787 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22254534 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3994693 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 316440 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278480395 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 316440 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10781716 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77380942 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5123914 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24366684 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13623085 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277321096 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 194260 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5340054 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 70865 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 6669514 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331396172 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605049332 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371619608 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 206 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320040545 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11355627 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 162880 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 164114 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19801512 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6563978 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3714528 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 447098 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 397095 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275506715 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 407720 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273559358 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 95175 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8352705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12694060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62726 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155796605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.755875 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.385543 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 93164208 60.26% 60.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5135729 3.32% 63.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3649233 2.36% 65.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3187928 2.06% 68.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23055647 14.91% 82.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2154571 1.39% 84.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23598215 15.26% 99.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 439899 0.28% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 212473 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 93882329 60.26% 60.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5118192 3.29% 63.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3721128 2.39% 65.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3254343 2.09% 68.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23198440 14.89% 82.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2207021 1.42% 84.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23723391 15.23% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 467418 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 224343 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154597903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155796605 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1212353 81.77% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 211907 14.29% 96.06% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 58391 3.94% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1207560 81.79% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 207213 14.03% 95.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 61669 4.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 71762 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 261142020 96.23% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 52428 0.02% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48121 0.02% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 75 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6661415 2.45% 98.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3385968 1.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 77609 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263069409 96.17% 96.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56423 0.02% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50250 0.02% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 74 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6863260 2.51% 98.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3442333 1.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 271361789 # Type of FU issued -system.cpu2.iq.rate 1.744082 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1482651 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.005464 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 698896144 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 281150786 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 269884047 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 272772537 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 697485 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273559358 # Type of FU issued +system.cpu2.iq.rate 1.742356 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1476442 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005397 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 704486629 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284271419 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272061524 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 309 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274958042 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 149 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 723498 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1044107 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5365 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4726 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 557112 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1134318 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5680 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5091 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 595155 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 749552 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 25864 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 712054 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23601 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 289506 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 69224885 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4893125 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 273432835 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 29776 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6287198 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3639298 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 235948 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 164149 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4411192 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4726 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 153905 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164065 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 317970 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 270855594 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6536848 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 455372 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 316440 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69933639 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4486006 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275914435 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 35023 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6563978 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3714528 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 243237 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 162474 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4012628 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5091 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 167077 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 180895 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347972 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273011944 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6727791 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 497508 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9843230 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27477788 # Number of branches executed -system.cpu2.iew.exec_stores 3306382 # Number of stores executed -system.cpu2.iew.exec_rate 1.740829 # Inst execution rate -system.cpu2.iew.wb_sent 270693369 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 269884157 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 210625616 # num instructions producing a value -system.cpu2.iew.wb_consumers 345602988 # num instructions consuming a value +system.cpu2.iew.exec_refs 10089541 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27708179 # Number of branches executed +system.cpu2.iew.exec_stores 3361750 # Number of stores executed +system.cpu2.iew.exec_rate 1.738869 # Inst execution rate +system.cpu2.iew.wb_sent 272840114 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272061642 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212265363 # num instructions producing a value +system.cpu2.iew.wb_consumers 348191102 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.734585 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609444 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.732817 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609623 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7711989 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 345334 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 277097 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 153447715 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.731657 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.637088 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8350016 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 344994 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 302940 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 154548999 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.731242 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.636335 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 96780970 63.07% 63.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4222028 2.75% 65.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1231000 0.80% 66.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24221852 15.79% 82.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 924771 0.60% 83.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 693299 0.45% 83.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 425605 0.28% 83.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 22935468 14.95% 98.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2012722 1.31% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 97452573 63.06% 63.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4255618 2.75% 65.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1276058 0.83% 66.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24388972 15.78% 82.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 952831 0.62% 83.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 707614 0.46% 83.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 433779 0.28% 83.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23017420 14.89% 98.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2064134 1.34% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 153447715 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 134778170 # Number of instructions committed -system.cpu2.commit.committedOps 265718845 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 154548999 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135671284 # Number of instructions committed +system.cpu2.commit.committedOps 267561730 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8325277 # Number of memory references committed -system.cpu2.commit.loads 5243091 # Number of loads committed -system.cpu2.commit.membars 153740 # Number of memory barriers committed -system.cpu2.commit.branches 27132938 # Number of branches committed +system.cpu2.commit.refs 8549033 # Number of memory references committed +system.cpu2.commit.loads 5429660 # Number of loads committed +system.cpu2.commit.membars 149565 # Number of memory barriers committed +system.cpu2.commit.branches 27339879 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 242753564 # Number of committed integer instructions. -system.cpu2.commit.function_calls 416792 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 41984 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 257254606 96.81% 96.83% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 50787 0.02% 96.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 46205 0.02% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5243061 1.97% 98.84% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3082186 1.16% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244517945 # Number of committed integer instructions. +system.cpu2.commit.function_calls 438137 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46306 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 258863559 96.75% 96.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 54521 0.02% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48345 0.02% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5429610 2.03% 98.83% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3119373 1.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 265718845 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2012722 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 424836983 # The number of ROB reads -system.cpu2.rob.rob_writes 548017282 # The number of ROB writes -system.cpu2.timesIdled 100227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 992136 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909996040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 134778170 # Number of Instructions Simulated -system.cpu2.committedOps 265718845 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.154416 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.154416 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.866239 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.866239 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 360832495 # number of integer regfile reads -system.cpu2.int_regfile_writes 216221900 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73134 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 137826475 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106107258 # number of cc regfile writes -system.cpu2.misc_regfile_reads 87959882 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137617 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3552161 # Transaction distribution -system.iobus.trans_dist::ReadResp 3552161 # Transaction distribution -system.iobus.trans_dist::WriteReq 57740 # Transaction distribution -system.iobus.trans_dist::WriteResp 57740 # Transaction distribution -system.iobus.trans_dist::MessageReq 1667 # Transaction distribution -system.iobus.trans_dist::MessageResp 1667 # Transaction distribution +system.cpu2.commit.op_class_0::total 267561730 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2064134 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 428366748 # The number of ROB reads +system.cpu2.rob.rob_writes 553077080 # The number of ROB writes +system.cpu2.timesIdled 112413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1208848 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4910585835 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135671284 # Number of Instructions Simulated +system.cpu2.committedOps 267561730 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.157249 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.157249 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.864118 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.864118 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363754203 # number of integer regfile reads +system.cpu2.int_regfile_writes 218036965 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73086 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 138800226 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106739606 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88774953 # number of misc regfile reads +system.cpu2.misc_regfile_writes 143862 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3545348 # Transaction distribution +system.iobus.trans_dist::ReadResp 3545348 # Transaction distribution +system.iobus.trans_dist::WriteReq 57726 # Transaction distribution +system.iobus.trans_dist::WriteResp 57726 # Transaction distribution +system.iobus.trans_dist::MessageReq 1644 # Transaction distribution +system.iobus.trans_dist::MessageResp 1644 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7124546 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7223136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7110880 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7209436 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540117 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533324 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13934 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3568475 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6602951 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2194728 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3561720 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6596152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2378920 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3095000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5419500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 748000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 921000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 140118000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 199977500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 340000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 507000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8907000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11026500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 119418499 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 144387981 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 1052000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 295238000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 283491000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 23500000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 31080000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 920000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 979000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47573 # number of replacements -system.iocache.tags.tagsinuse 0.105025 # Cycle average of tags in use +system.iocache.tags.replacements 47579 # number of replacements +system.iocache.tags.tagsinuse 0.099877 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000694858009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.105025 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006564 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006564 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000697713509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.099877 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006242 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006242 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428652 # Number of tag accesses -system.iocache.tags.data_accesses 428652 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.tags.tag_accesses 428706 # Number of tag accesses +system.iocache.tags.data_accesses 428706 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses +system.iocache.ReadReq_misses::total 914 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses -system.iocache.demand_misses::total 908 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses -system.iocache.overall_misses::total 908 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 17834920 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17834920 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3008484579 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3008484579 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 17834920 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 17834920 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 17834920 # number of overall miss cycles -system.iocache.overall_miss_latency::total 17834920 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses +system.iocache.demand_misses::total 914 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses +system.iocache.overall_misses::total 914 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126880276 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 126880276 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3631346705 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3631346705 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 126880276 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 126880276 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 126880276 # number of overall miss cycles +system.iocache.overall_miss_latency::total 126880276 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1277,323 +1282,327 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 19641.982379 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 64393.933626 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 64393.933626 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 19641.982379 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 19641.982379 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138818.682713 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77725.742830 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 77725.742830 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138818.682713 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138818.682713 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 745 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 69 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.797101 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 150 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 23200 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 23200 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 150 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 150 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 150 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 150 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10334920 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1848484579 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1848484579 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10334920 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10334920 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.165198 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.496575 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.496575 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.165198 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.165198 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68899.466667 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79676.059440 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79676.059440 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 756 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 756 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27936 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 27936 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 756 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 756 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 756 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 756 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 89080276 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 2234546705 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2234546705 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 89080276 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 89080276 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.827133 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.597945 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.597945 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.827133 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.827133 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.052910 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.069337 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.069337 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average overall mshr miss latency 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-system.l2c.tags.occ_blocks::cpu2.data 3917.724589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777831 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51005.596123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.135096 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1646.370611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4933.032602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 515.170721 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1886.198863 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.247587 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 884.114832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3927.326006 # Average occupied blocks per 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task id +system.l2c.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6913 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977753 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41426818 # Number of tag accesses +system.l2c.tags.data_accesses 41426818 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20684 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10937 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10806 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5737 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 57360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12726 # number of ReadReq hits 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6238 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 173626 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 248539 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 52514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 344819 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 656469 # number of demand (read+write) hits -system.l2c.demand_hits::total 2427659 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19237 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10442 # number of overall hits -system.l2c.overall_hits::cpu0.inst 323982 # number of overall hits -system.l2c.overall_hits::cpu0.data 569277 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 11603 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6238 # number of overall hits -system.l2c.overall_hits::cpu1.inst 173626 # number of overall hits -system.l2c.overall_hits::cpu1.data 248539 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 52514 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits -system.l2c.overall_hits::cpu2.inst 344819 # number of overall hits -system.l2c.overall_hits::cpu2.data 656469 # number of overall hits -system.l2c.overall_hits::total 2427659 # number of overall hits +system.l2c.WritebackDirty_hits::writebacks 1548077 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1548077 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 861736 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 861736 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 31 # number of UpgradeReq hits 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number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3494 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2876 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 6370 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 4040500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10668000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 37156500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47824500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2805520000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4488029000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7293549000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 296188500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 701637000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 997825500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 559971000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1624421500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2184392500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 296188500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3365491000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 701637000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 6112450500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10479807500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 296188500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3365491000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 701637000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 6112450500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10479807500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28471375500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30579722500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59051098000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 633646000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 578928500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1212574500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29105021500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31158651000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60263672500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000262 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829670 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.822884 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.408213 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452781 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.378810 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.212834 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.009295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021742 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.020912 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012854 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033243 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 130338.709677 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70774.285714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.301775 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119572.361059 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118240.532391 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124448.179097 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121442.420299 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127706.092767 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126039.611101 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.775870 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.153512 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201296.418637 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190357.064364 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.551431 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.852761 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5081876 # Transaction distribution -system.membus.trans_dist::ReadResp 5130307 # Transaction distribution -system.membus.trans_dist::WriteReq 13937 # Transaction distribution -system.membus.trans_dist::WriteResp 13937 # Transaction distribution -system.membus.trans_dist::Writeback 142675 # Transaction distribution -system.membus.trans_dist::CleanEvict 8457 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1667 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1667 # Transaction distribution -system.membus.trans_dist::ReadExReq 129637 # Transaction distribution -system.membus.trans_dist::ReadExResp 129637 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48432 # Transaction distribution -system.membus.trans_dist::MessageReq 1667 # Transaction distribution -system.membus.trans_dist::MessageResp 1667 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution +system.membus.trans_dist::ReadReq 5063565 # Transaction distribution +system.membus.trans_dist::ReadResp 5112222 # Transaction distribution +system.membus.trans_dist::WriteReq 13898 # Transaction distribution +system.membus.trans_dist::WriteResp 13898 # Transaction distribution +system.membus.trans_dist::WritebackDirty 143022 # Transaction distribution +system.membus.trans_dist::CleanEvict 8552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1672 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1672 # Transaction distribution +system.membus.trans_dist::ReadExReq 129713 # Transaction distribution +system.membus.trans_dist::ReadExResp 129713 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48657 # Transaction distribution +system.membus.trans_dist::MessageReq 1644 # Transaction distribution +system.membus.trans_dist::MessageResp 1644 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3067080 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10653122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142139 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142139 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10798595 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568475 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6134157 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17466624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27169256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3035200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3035200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30211124 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 409 # Total snoops (count) -system.membus.snoop_fanout::samples 5475610 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017446 # Request fanout histogram +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 462447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10617373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10762648 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6088089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17501760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27151569 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30183297 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 664 # Total snoops (count) +system.membus.snoop_fanout::samples 5457993 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000301 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017353 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5473943 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5456349 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1644 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5475610 # Request fanout histogram -system.membus.reqLayer0.occupancy 227177500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5457993 # Request fanout histogram +system.membus.reqLayer0.occupancy 219248500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 301308000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 286800000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1840000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2377080 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 538434425 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 547350354 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 920000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1398080 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1326481306 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1208209380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 41176558 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 52355698 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1815,60 +1822,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5040257 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2546109 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 319 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1148 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1148 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5045321 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2544604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1171 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1171 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5235870 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7440960 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13939 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13939 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1628762 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 950991 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1645 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1645 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289206 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289206 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 857150 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1347950 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 920 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 23200 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2570707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15105454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 66396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204903 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17947460 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54857344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213491432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 241048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 697376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 269287200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 238040 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10439686 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.005090 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.071166 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5213952 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7425084 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13900 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13900 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1631207 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 861736 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 94941 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1656 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1656 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289822 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289822 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 862602 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1349057 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 979 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 27936 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586927 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15072185 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 70382 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 205946 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17935440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110356800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213581265 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 259408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 748104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 324945577 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 226314 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8918759 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.005043 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.070832 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 10386543 99.49% 99.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 53143 0.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8873785 99.50% 99.50% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 44974 0.50% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10439686 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2709674498 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8918759 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3217757998 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 251420 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 405376 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 789952436 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 810539408 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1874874404 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1832719254 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23291487 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24003478 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 94859175 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 87328075 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |