diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2566 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3230 |
2 files changed, 2902 insertions, 2894 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 264f4c629..d26a43093 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.126140 # Number of seconds simulated -sim_ticks 5126139641000 # Number of ticks simulated -final_tick 5126139641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.144266 # Number of seconds simulated +sim_ticks 5144265998000 # Number of ticks simulated +final_tick 5144265998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128755 # Simulator instruction rate (inst/s) -host_op_rate 254500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618610313 # Simulator tick rate (ticks/s) -host_mem_usage 809248 # Number of bytes of host memory used -host_seconds 3167.00 # Real time elapsed on the host -sim_insts 407767906 # Number of instructions simulated -sim_ops 806002026 # Number of ops (including micro ops) simulated +host_inst_rate 171354 # Simulator instruction rate (inst/s) +host_op_rate 338701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2161855241 # Simulator tick rate (ticks/s) +host_mem_usage 817304 # Number of bytes of host memory used +host_seconds 2379.56 # Real time elapsed on the host +sim_insts 407746267 # Number of instructions simulated +sim_ops 805959101 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1038720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10766272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1040896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10728128 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11837632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1038720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1038720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9565696 # Number of bytes written to this memory -system.physmem.bytes_written::total 9565696 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168223 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11801664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1040896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1040896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9535488 # Number of bytes written to this memory +system.physmem.bytes_written::total 9535488 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16264 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167627 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 184963 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149464 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149464 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 202632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2100269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2309268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 202632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 202632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1866062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1866062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1866062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 202632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2100269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4175331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 184963 # Number of read requests accepted -system.physmem.writeReqs 149464 # Number of write requests accepted -system.physmem.readBursts 184963 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149464 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11826048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue -system.physmem.bytesWritten 9564672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11837632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9565696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 184401 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148992 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148992 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 202341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2085454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2294140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 202341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 202341 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1853615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1853615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1853615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 202341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2085454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4147754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184401 # Number of read requests accepted +system.physmem.writeReqs 148992 # Number of write requests accepted +system.physmem.readBursts 184401 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148992 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11790400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11264 # Total number of bytes read from write queue +system.physmem.bytesWritten 9534208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11801664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9535488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48781 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12059 # Per bank write bursts -system.physmem.perBankRdBursts::1 11374 # Per bank write bursts -system.physmem.perBankRdBursts::2 11651 # Per bank write bursts -system.physmem.perBankRdBursts::3 11200 # Per bank write bursts -system.physmem.perBankRdBursts::4 11713 # Per bank write bursts -system.physmem.perBankRdBursts::5 11071 # Per bank write bursts -system.physmem.perBankRdBursts::6 11625 # Per bank write bursts -system.physmem.perBankRdBursts::7 11816 # Per bank write bursts -system.physmem.perBankRdBursts::8 11540 # Per bank write bursts -system.physmem.perBankRdBursts::9 11598 # Per bank write bursts -system.physmem.perBankRdBursts::10 11427 # Per bank write bursts -system.physmem.perBankRdBursts::11 11449 # Per bank write bursts -system.physmem.perBankRdBursts::12 11382 # Per bank write bursts -system.physmem.perBankRdBursts::13 12463 # Per bank write bursts -system.physmem.perBankRdBursts::14 11321 # Per bank write bursts -system.physmem.perBankRdBursts::15 11093 # Per bank write bursts -system.physmem.perBankWrBursts::0 10213 # Per bank write bursts -system.physmem.perBankWrBursts::1 9339 # Per bank write bursts -system.physmem.perBankWrBursts::2 9470 # Per bank write bursts -system.physmem.perBankWrBursts::3 9072 # Per bank write bursts -system.physmem.perBankWrBursts::4 9457 # Per bank write bursts -system.physmem.perBankWrBursts::5 9178 # Per bank write bursts -system.physmem.perBankWrBursts::6 9173 # Per bank write bursts -system.physmem.perBankWrBursts::7 8997 # Per bank write bursts -system.physmem.perBankWrBursts::8 8928 # Per bank write bursts -system.physmem.perBankWrBursts::9 9204 # Per bank write bursts -system.physmem.perBankWrBursts::10 9473 # Per bank write bursts -system.physmem.perBankWrBursts::11 8827 # Per bank write bursts -system.physmem.perBankWrBursts::12 9527 # Per bank write bursts -system.physmem.perBankWrBursts::13 9857 # Per bank write bursts -system.physmem.perBankWrBursts::14 9294 # Per bank write bursts -system.physmem.perBankWrBursts::15 9439 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48430 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11512 # Per bank write bursts +system.physmem.perBankRdBursts::1 10865 # Per bank write bursts +system.physmem.perBankRdBursts::2 12624 # Per bank write bursts +system.physmem.perBankRdBursts::3 11646 # Per bank write bursts +system.physmem.perBankRdBursts::4 11360 # Per bank write bursts +system.physmem.perBankRdBursts::5 11063 # Per bank write bursts +system.physmem.perBankRdBursts::6 11424 # Per bank write bursts +system.physmem.perBankRdBursts::7 11380 # Per bank write bursts +system.physmem.perBankRdBursts::8 11354 # Per bank write bursts +system.physmem.perBankRdBursts::9 10854 # Per bank write bursts +system.physmem.perBankRdBursts::10 10623 # Per bank write bursts +system.physmem.perBankRdBursts::11 11335 # Per bank write bursts +system.physmem.perBankRdBursts::12 12163 # Per bank write bursts +system.physmem.perBankRdBursts::13 12460 # Per bank write bursts +system.physmem.perBankRdBursts::14 11874 # Per bank write bursts +system.physmem.perBankRdBursts::15 11688 # Per bank write bursts +system.physmem.perBankWrBursts::0 9762 # Per bank write bursts +system.physmem.perBankWrBursts::1 9087 # Per bank write bursts +system.physmem.perBankWrBursts::2 9770 # Per bank write bursts +system.physmem.perBankWrBursts::3 9357 # Per bank write bursts +system.physmem.perBankWrBursts::4 9485 # Per bank write bursts +system.physmem.perBankWrBursts::5 8994 # Per bank write bursts +system.physmem.perBankWrBursts::6 9154 # Per bank write bursts +system.physmem.perBankWrBursts::7 8718 # Per bank write bursts +system.physmem.perBankWrBursts::8 8812 # Per bank write bursts +system.physmem.perBankWrBursts::9 9056 # Per bank write bursts +system.physmem.perBankWrBursts::10 8954 # Per bank write bursts +system.physmem.perBankWrBursts::11 9300 # Per bank write bursts +system.physmem.perBankWrBursts::12 9801 # Per bank write bursts +system.physmem.perBankWrBursts::13 9709 # Per bank write bursts +system.physmem.perBankWrBursts::14 9528 # Per bank write bursts +system.physmem.perBankWrBursts::15 9485 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 5126139591500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5144265948500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 184963 # Read request sizes (log2) +system.physmem.readPktSize::6 184401 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149464 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148992 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 169976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see @@ -156,303 +156,298 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71880 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.588425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.048684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 320.988013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27629 38.44% 38.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17400 24.21% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7428 10.33% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4118 5.73% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2845 3.96% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1999 2.78% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1307 1.82% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1141 1.59% 88.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8013 11.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71880 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7347 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.150402 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 560.379075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7346 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.681517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.230147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.360710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28156 38.51% 38.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17755 24.29% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7676 10.50% 73.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4351 5.95% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2926 4.00% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2405 3.29% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1356 1.85% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1112 1.52% 89.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7372 10.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73109 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7269 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.343238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.383377 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7268 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7347 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.341364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.592949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.054942 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6299 85.74% 85.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 77 1.05% 86.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 192 2.61% 89.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 82 1.12% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 130 1.77% 92.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 203 2.76% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 23 0.31% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.10% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.11% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.05% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.08% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 243 3.31% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.10% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.15% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 7 0.10% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.22% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7347 # Writes before turning the bus around for reads -system.physmem.totQLat 1972823732 # Total ticks spent queuing -system.physmem.totMemAccLat 5437486232 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 923910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10676.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7269 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7269 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.494153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.676401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.977803 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6209 85.42% 85.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 177 2.43% 87.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.43% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 190 2.61% 90.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 15 0.21% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.08% 93.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 110 1.51% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.12% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 21 0.29% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 27 0.37% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 236 3.25% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 36 0.50% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.07% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.21% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7269 # Writes before turning the bus around for reads +system.physmem.totQLat 2113024695 # Total ticks spent queuing +system.physmem.totMemAccLat 5567243445 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 921125000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11469.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29426.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30219.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.70 # Average write queue length when enqueuing -system.physmem.readRowHits 152120 # Number of row buffer hits during reads -system.physmem.writeRowHits 110229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes -system.physmem.avgGap 15328127.19 # Average gap between requests -system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 270149040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 147402750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 721570200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 485345520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129415070025 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2962157471250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3428011044705 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.732438 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4927750166228 # Time in different power states -system.physmem_0.memoryStateTime::REF 171172820000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.39 # Average write queue length when enqueuing +system.physmem.readRowHits 150283 # Number of row buffer hits during reads +system.physmem.writeRowHits 109804 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes +system.physmem.avgGap 15430035.87 # Average gap between requests +system.physmem.pageHitRate 78.05 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 271774440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148289625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 716609400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 481638960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 133079069070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2969819271000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3440514616095 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.806670 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4940481054222 # Time in different power states +system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27209465022 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32006683778 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 273263760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 149102250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 719721600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 483077520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129328302060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2962233583500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3428001086610 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.730496 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4927884080230 # Time in different power states -system.physmem_1.memoryStateTime::REF 171172820000 # Time in different power states +system.physmem_1.actEnergy 280929600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 153285000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 720337800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 483699600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 133106515425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2969795195250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3440537926275 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811201 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4940433568236 # Time in different power states +system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27082630770 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32047173014 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86515320 # Number of BP lookups -system.cpu.branchPred.condPredicted 86515320 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 846562 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79887008 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77941063 # Number of BTB hits +system.cpu.branchPred.lookups 86512376 # Number of BP lookups +system.cpu.branchPred.condPredicted 86512376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844809 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79880541 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77944216 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.564128 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1538368 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179519 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.575974 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1537356 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 178131 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 448780162 # number of cpu cycles simulated +system.cpu.numCycles 465431904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27109366 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427484272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86515320 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79479431 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417767954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1778202 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 144572 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 59542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 198505 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8932158 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 424030 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4890 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446169387 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.890848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.050446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27316222 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427457339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86512376 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79481572 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433294653 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1774328 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 174290 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 61780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 197089 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 797 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8939505 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 424296 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5201 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 461932056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.826209 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.017418 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281281763 63.04% 63.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2130107 0.48% 63.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72126905 16.17% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1545484 0.35% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2095217 0.47% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2290541 0.51% 81.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1479828 0.33% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1850907 0.41% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81368635 18.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 297044979 64.30% 64.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2134462 0.46% 64.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72126640 15.61% 80.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1546779 0.33% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2100235 0.45% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2289900 0.50% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1474676 0.32% 81.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1857009 0.40% 82.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81357376 17.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446169387 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192779 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952547 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23013230 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 265986736 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 147854773 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8425547 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 889101 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 835878661 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 889101 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26336765 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 222825660 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12982234 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152266315 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 30869312 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 832551989 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 449261 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12787861 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 146326 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14734321 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 994655089 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1807638707 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1111268111 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963888503 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30766581 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460676 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463553 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43190500 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17070475 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10019861 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1311535 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1113253 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 827301854 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1181846 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 822527972 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 224018 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22481665 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33938360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 142118 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446169387 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843533 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.419200 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 461932056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185875 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.918410 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23107773 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 281695317 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 147794197 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8447605 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 887164 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 835787144 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 887164 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 26441875 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 229504552 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14337084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152214834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 38546547 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 832466923 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 458085 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12798467 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 221946 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22321415 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 994552862 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1807469855 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1111168371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 379 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963838514 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30714343 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 460142 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463176 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43334873 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17067493 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10022220 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1319734 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1116337 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827242342 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1181786 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 822485271 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 216558 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22465018 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33877646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 141871 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 461932056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.780533 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400914 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262457891 58.82% 58.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13818111 3.10% 61.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9771246 2.19% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7528828 1.69% 65.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 73243364 16.42% 82.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4832116 1.08% 83.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72756563 16.31% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1182673 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578595 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278202681 60.23% 60.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13844974 3.00% 63.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9781174 2.12% 65.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7532969 1.63% 66.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 73227075 15.85% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4827596 1.05% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72754467 15.75% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1183000 0.26% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 578120 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446169387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 461932056 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2475977 76.35% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 605774 18.68% 95.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161247 4.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2482095 76.42% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 605940 18.66% 95.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160087 4.93% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 283294 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 794512938 96.59% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150315 0.02% 96.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126079 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 284904 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 794458238 96.59% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149904 0.02% 96.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126188 0.02% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 113 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued @@ -476,98 +471,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18183253 2.21% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9272009 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18188915 2.21% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9277009 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 822527972 # Type of FU issued -system.cpu.iq.rate 1.832808 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3242998 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2094691886 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 850977244 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818130626 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 165 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825487451 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1857982 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 822485271 # Type of FU issued +system.cpu.iq.rate 1.767144 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3248122 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003949 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2110366769 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 850901074 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818087590 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 508 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 586 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 178 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825448239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1862376 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3083761 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14419 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13953 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1600409 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3081864 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14686 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14021 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1600056 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2207227 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 67958 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207186 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68323 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 889101 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 204671978 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10002497 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 828483700 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 158761 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17070475 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10019861 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 692471 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 393140 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8758574 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13953 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 479614 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 507057 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 986671 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821011839 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17813350 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1389357 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 887164 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205274699 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15795611 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 828424128 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 165882 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17067493 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10022220 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 692366 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 393655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14549719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14021 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 476392 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506422 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 982814 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 820971747 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17818623 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1389098 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26873346 # number of memory reference insts executed -system.cpu.iew.exec_branches 83150160 # Number of branches executed -system.cpu.iew.exec_stores 9059996 # Number of stores executed -system.cpu.iew.exec_rate 1.829430 # Inst execution rate -system.cpu.iew.wb_sent 820539763 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818130791 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639922411 # num instructions producing a value -system.cpu.iew.wb_consumers 1048802840 # num instructions consuming a value +system.cpu.iew.exec_refs 26886211 # number of memory reference insts executed +system.cpu.iew.exec_branches 83147027 # Number of branches executed +system.cpu.iew.exec_stores 9067588 # Number of stores executed +system.cpu.iew.exec_rate 1.763892 # Inst execution rate +system.cpu.iew.wb_sent 820497311 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818087768 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639862073 # num instructions producing a value +system.cpu.iew.wb_consumers 1048693225 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823010 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610146 # average fanout of values written-back +system.cpu.iew.wb_rate 1.757696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610152 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22357422 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1039727 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 857347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 442798070 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.820247 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.674846 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22343285 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1039914 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 855258 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 458562995 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.757576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.649246 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272013186 61.43% 61.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11121974 2.51% 63.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3639430 0.82% 64.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74586618 16.84% 81.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2447768 0.55% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1626880 0.37% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1002961 0.23% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70975924 16.03% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5383329 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 287777749 62.76% 62.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11132608 2.43% 65.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3641047 0.79% 65.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74579710 16.26% 82.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2448796 0.53% 82.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1627078 0.35% 83.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1001834 0.22% 83.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70969693 15.48% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5384480 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 442798070 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407767906 # Number of instructions committed -system.cpu.commit.committedOps 806002026 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 458562995 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407746267 # Number of instructions committed +system.cpu.commit.committedOps 805959101 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22406164 # Number of memory references committed -system.cpu.commit.loads 13986712 # Number of loads committed -system.cpu.commit.membars 468149 # Number of memory barriers committed -system.cpu.commit.branches 82157432 # Number of branches committed +system.cpu.commit.refs 22407791 # Number of memory references committed +system.cpu.commit.loads 13985627 # Number of loads committed +system.cpu.commit.membars 468163 # Number of memory barriers committed +system.cpu.commit.branches 82155343 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734850257 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155439 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171613 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783160302 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144896 0.02% 97.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121618 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734813827 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155420 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171757 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783115943 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144574 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -594,231 +589,230 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13984129 1.73% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8419452 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13983042 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8422164 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806002026 # Class of committed instruction -system.cpu.commit.bw_lim_events 5383329 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1265696040 # The number of ROB reads -system.cpu.rob.rob_writes 1660107630 # The number of ROB writes -system.cpu.timesIdled 283975 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2610775 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9803496536 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407767906 # Number of Instructions Simulated -system.cpu.committedOps 806002026 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.100577 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.100577 # CPI: Total CPI of All Threads -system.cpu.ipc 0.908614 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.908614 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1090426394 # number of integer regfile reads -system.cpu.int_regfile_writes 654841654 # number of integer regfile writes -system.cpu.fp_regfile_reads 165 # number of floating regfile reads -system.cpu.cc_regfile_reads 415713185 # number of cc regfile reads -system.cpu.cc_regfile_writes 321659378 # number of cc regfile writes -system.cpu.misc_regfile_reads 264880270 # number of misc regfile reads -system.cpu.misc_regfile_writes 399890 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1655948 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995019 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18959511 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656460 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.445801 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995019 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 805959101 # Class of committed instruction +system.cpu.commit.bw_lim_events 5384480 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1281402583 # The number of ROB reads +system.cpu.rob.rob_writes 1659991505 # The number of ROB writes +system.cpu.timesIdled 284256 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3499848 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9823097505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407746267 # Number of Instructions Simulated +system.cpu.committedOps 805959101 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.141474 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.141474 # CPI: Total CPI of All Threads +system.cpu.ipc 0.876060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.876060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1090398458 # number of integer regfile reads +system.cpu.int_regfile_writes 654801015 # number of integer regfile writes +system.cpu.fp_regfile_reads 178 # number of floating regfile reads +system.cpu.cc_regfile_reads 415698435 # number of cc regfile reads +system.cpu.cc_regfile_writes 321644299 # number of cc regfile writes +system.cpu.misc_regfile_reads 264872577 # number of misc regfile reads +system.cpu.misc_regfile_writes 400155 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1656886 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993571 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18963252 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657398 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.441580 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993571 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87653092 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87653092 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10818266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10818266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8075018 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8075018 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63136 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63136 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 18893284 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18893284 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18956420 # number of overall hits -system.cpu.dcache.overall_hits::total 18956420 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1801440 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1801440 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334795 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334795 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406500 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406500 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2136235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2136235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2542735 # number of overall misses -system.cpu.dcache.overall_misses::total 2542735 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26875877500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26875877500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13801276738 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13801276738 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40677154238 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40677154238 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40677154238 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40677154238 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12619706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12619706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8409813 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8409813 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 469636 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 469636 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21029519 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21029519 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21499155 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21499155 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142748 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.142748 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039810 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039810 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865564 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.865564 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101583 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101583 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118271 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118271 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14919.107769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14919.107769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.067065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.067065 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19041.516611 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19041.516611 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15997.402104 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15997.402104 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 467524 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 52009 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.989290 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 87668549 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87668549 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10819943 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10819943 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077328 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63083 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63083 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18897271 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18897271 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18960354 # number of overall hits +system.cpu.dcache.overall_hits::total 18960354 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1800618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1800618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 335187 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 335187 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406619 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406619 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2135805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2135805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2542424 # number of overall misses +system.cpu.dcache.overall_misses::total 2542424 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29915350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29915350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21131383234 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21131383234 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51046733734 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51046733734 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51046733734 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51046733734 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12620561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12620561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8412515 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412515 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 469702 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 469702 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21033076 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21033076 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21502778 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21502778 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142673 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142673 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039844 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865696 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.865696 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101545 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101545 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118237 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118237 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16613.935049 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16613.935049 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63043.564440 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63043.564440 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23900.465508 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23900.465508 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20077.978234 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20077.978234 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 549742 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52309 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.509511 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1557810 # number of writebacks -system.cpu.dcache.writebacks::total 1557810 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835579 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 835579 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44644 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44644 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 880223 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 880223 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 880223 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 880223 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 965861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290151 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290151 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403017 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 403017 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1256012 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1256012 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1659029 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1659029 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13873 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 13873 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616769 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 616769 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13275179500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13275179500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12396951239 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12396951239 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6045548500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6045548500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25672130739 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25672130739 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31717679239 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31717679239 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2614977500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2614977500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100408631000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 100408631000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076536 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076536 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034501 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034501 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858148 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858148 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077167 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077167 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.399556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.399556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42725.860807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42725.860807 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15000.728257 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15000.728257 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20439.399257 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20439.399257 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19118.218692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19118.218692 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.505766 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.505766 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188494.017156 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188494.017156 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.791394 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.791394 # average overall mshr uncacheable latency +system.cpu.dcache.writebacks::writebacks 1559463 # number of writebacks +system.cpu.dcache.writebacks::total 1559463 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834370 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 834370 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44863 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 879233 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 879233 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 879233 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 879233 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 966248 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 966248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290324 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290324 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403128 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403128 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1256572 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1256572 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1659700 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1659700 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602897 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 602897 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13882 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13882 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616779 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 616779 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14275238000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14275238000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19179377736 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19179377736 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6821935500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6821935500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33454615736 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33454615736 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40276551236 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40276551236 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793888500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793888500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2616393000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2616393000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100410281500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100410281500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076561 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076561 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034511 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034511 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858263 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858263 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059743 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059743 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077185 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 71018 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.855051 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 110090 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 71033 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.549843 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.855051 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.990941 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.990941 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 86946 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.839570 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92503 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 86961 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.063730 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.839570 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.989973 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.989973 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 436469 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 436469 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110104 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 110104 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110104 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 110104 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110104 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 110104 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 72087 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 72087 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 72087 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 72087 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 72087 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 72087 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 888705500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 888705500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 888705500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 888705500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 888705500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 888705500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182191 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 182191 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182191 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 182191 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182191 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 182191 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395667 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395667 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395667 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395667 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395667 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395667 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12328.235327 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12328.235327 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12328.235327 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12328.235327 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 449092 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 449092 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92507 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92507 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92507 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92507 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92507 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92507 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 88026 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 88026 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 88026 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 88026 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 88026 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 88026 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1095128000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1095128000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1095128000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1095128000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1095128000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1095128000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180533 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 180533 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180533 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 180533 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180533 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 180533 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.487590 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.487590 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.487590 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.487590 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.487590 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.487590 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -827,180 +821,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 17880 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 17880 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 72087 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 72087 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 72087 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 72087 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 72087 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 72087 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 816618500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 816618500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 816618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 816618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 816618500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 816618500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395667 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395667 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395667 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11328.235327 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 22750 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 22750 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 88026 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 88026 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 88026 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 88026 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 88026 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 88026 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1007102000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1007102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1007102000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.487590 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.487590 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.487590 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 972475 # number of replacements -system.cpu.icache.tags.tagsinuse 509.589862 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7892622 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 972987 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.111745 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147937650500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.589862 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995293 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995293 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 979952 # number of replacements +system.cpu.icache.tags.tagsinuse 509.399185 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7892668 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 980464 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.049931 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 150322947500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.399185 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994920 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994920 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9905522 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9905522 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7892622 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7892622 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7892622 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7892622 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7892622 # number of overall hits -system.cpu.icache.overall_hits::total 7892622 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1039533 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1039533 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1039533 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1039533 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1039533 # number of overall misses -system.cpu.icache.overall_misses::total 1039533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14506630997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14506630997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14506630997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14506630997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14506630997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14506630997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8932155 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8932155 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8932155 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8932155 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8932155 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8932155 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116381 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116381 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.116381 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.116381 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.116381 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.116381 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13954.949960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13954.949960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13954.949960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13954.949960 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6454 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.554140 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 9920034 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9920034 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7892668 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7892668 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7892668 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7892668 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7892668 # number of overall hits +system.cpu.icache.overall_hits::total 7892668 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1046827 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1046827 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1046827 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1046827 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1046827 # number of overall misses +system.cpu.icache.overall_misses::total 1046827 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15679887484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15679887484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15679887484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15679887484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15679887484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15679887484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8939495 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8939495 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8939495 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8939495 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8939495 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8939495 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117101 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.117101 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.117101 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.117101 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.117101 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.117101 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14978.489745 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14978.489745 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 13392 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 457 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.304158 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 973367 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12880264497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12880264497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12880264497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12880264497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12880264497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12880264497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108973 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108973 # 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Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13975 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.717710 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017494 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376093 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376093 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 92555 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 92555 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24014 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 24014 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 19284 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.025119 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 17613 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 19298 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 0.912685 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.025119 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376570 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376570 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 95741 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 95741 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 17618 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 17618 # 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number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 170100000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 170100000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 170100000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 170100000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 170100000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 170100000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38855 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38855 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 17620 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 17620 # 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average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 37787 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 37787 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.533730 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.533730 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.533702 # 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number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1009,183 +1003,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2319 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2319 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14841 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14841 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14841 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14841 # 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mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381959 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381939 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381939 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813 # 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number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 213017000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 213017000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 213017000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 213017000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 213017000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 213017000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.533730 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.533730 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.533702 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.533702 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50541.510277 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.632944 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.306836 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.688831 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771202 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.940071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3193.810391 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.770836 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000167 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047383 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63797 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 708 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3407 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5556 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54082 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.973465 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43431157 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43431157 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1578009 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1578009 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154224 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154224 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 956701 # 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number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16231 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169197 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185495 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16231 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169197 # number of overall misses -system.cpu.l2cache.overall_misses::total 185495 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23220500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 23220500 # 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number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2107 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287712 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287712 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 972932 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 972932 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 65614 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12097 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368134 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1445845 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 65614 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12097 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 972932 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1655846 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2706489 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 65614 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12097 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 972932 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1655846 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2706489 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.847651 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.847651 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 676 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3413 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5955 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54192 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980820 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43682151 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43682151 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1585410 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1585410 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 346 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 346 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 155314 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 155314 # 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mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.847651 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.847651 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463964 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463964 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026098 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024742 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068536 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068536 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75722.357587 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75739.090935 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808628 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808628 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016589 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024496 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067764 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067764 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125900 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3032324 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1727482 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1093519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 973367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1456602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1641 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5491514 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2726446 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 94920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1211 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1211 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 602897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3061240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1734407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1095490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2269 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2269 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 288196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 980539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1478351 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917513 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6205490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31703 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168231 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9322937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62267648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207474745 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 922624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5343616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 276008633 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 220316 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6258702 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.033424 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179742 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2939753 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6208049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 41124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 194511 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9383437 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207643157 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1196736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 6311744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 277897109 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 226924 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6316816 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.030269 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.203509 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6049509 96.66% 96.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 209193 3.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6163711 97.58% 97.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 115005 1.82% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 38100 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6258702 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4609709481 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6316816 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4646513967 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 659789 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1461362367 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1472350908 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3096027096 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3097364534 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22269484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 30265969 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 108175907 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 132091893 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 222102 # Transaction distribution -system.iobus.trans_dist::ReadResp 222102 # Transaction distribution -system.iobus.trans_dist::WriteReq 57708 # Transaction distribution -system.iobus.trans_dist::WriteResp 57708 # Transaction distribution -system.iobus.trans_dist::MessageReq 1641 # Transaction distribution -system.iobus.trans_dist::MessageResp 1641 # Transaction distribution +system.iobus.trans_dist::ReadReq 222097 # Transaction distribution +system.iobus.trans_dist::ReadResp 222097 # Transaction distribution +system.iobus.trans_dist::WriteReq 57711 # Transaction distribution +system.iobus.trans_dist::WriteResp 57711 # Transaction distribution +system.iobus.trans_dist::MessageReq 1645 # Transaction distribution +system.iobus.trans_dist::MessageResp 1645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) @@ -1384,18 +1384,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 562902 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 464358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 562906 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) @@ -1408,13 +1408,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3272880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 238456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3272852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3921096 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1426,7 +1426,7 @@ system.iobus.reqLayer4.occupancy 122000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1450,54 +1450,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242679087 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 241306768 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 453367000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50182000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47580 # number of replacements -system.iocache.tags.tagsinuse 0.091366 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.116041 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4993241946000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091366 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005710 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005710 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4999338704000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116041 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007253 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007253 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428715 # Number of tag accesses -system.iocache.tags.data_accesses 428715 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses -system.iocache.ReadReq_misses::total 915 # number of ReadReq misses +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 915 # number of demand (read+write) misses -system.iocache.demand_misses::total 915 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 915 # number of overall misses -system.iocache.overall_misses::total 915 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143595677 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143595677 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513463410 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5513463410 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 143595677 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 143595677 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 143595677 # number of overall miss cycles -system.iocache.overall_miss_latency::total 143595677 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses +system.iocache.demand_misses::total 909 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses +system.iocache.overall_misses::total 909 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144457672 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144457672 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6056832096 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6056832096 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144457672 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144457672 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144457672 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144457672 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 915 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 915 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 915 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 915 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1506,40 +1506,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 156935.166120 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 156935.166120 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 156935.166120 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158919.331133 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158919.331133 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158919.331133 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 52 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.615385 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 915 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97845677 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177463410 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3177463410 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97845677 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97845677 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 99007672 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3720832096 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3720832096 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 99007672 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 99007672 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1548,77 +1548,77 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 602896 # Transaction distribution -system.membus.trans_dist::ReadResp 655806 # Transaction distribution -system.membus.trans_dist::WriteReq 13873 # Transaction distribution -system.membus.trans_dist::WriteResp 13873 # Transaction distribution -system.membus.trans_dist::Writeback 149464 # Transaction distribution -system.membus.trans_dist::CleanEvict 9883 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2535 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2080 # Transaction distribution -system.membus.trans_dist::ReadExReq 133195 # Transaction distribution -system.membus.trans_dist::ReadExResp 133194 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52918 # Transaction distribution -system.membus.trans_dist::MessageReq 1641 # Transaction distribution -system.membus.trans_dist::MessageResp 1641 # Transaction distribution +system.membus.trans_dist::ReadReq 602897 # Transaction distribution +system.membus.trans_dist::ReadResp 655826 # Transaction distribution +system.membus.trans_dist::WriteReq 13882 # Transaction distribution +system.membus.trans_dist::WriteResp 13882 # Transaction distribution +system.membus.trans_dist::Writeback 148992 # Transaction distribution +system.membus.trans_dist::CleanEvict 9700 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2190 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1729 # Transaction distribution +system.membus.trans_dist::ReadExReq 132608 # Transaction distribution +system.membus.trans_dist::ReadExResp 132605 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52937 # Transaction distribution +system.membus.trans_dist::MessageReq 1645 # Transaction distribution +system.membus.trans_dist::MessageResp 1645 # Transaction distribution system.membus.trans_dist::BadAddressError 8 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 486631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769200 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484156 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720185 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1865287 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538373 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18388288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20165113 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1717730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1862834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538397 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20098965 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23186717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23120585 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 1616 # Total snoops (count) -system.membus.snoop_fanout::samples 1013692 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001619 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040202 # Request fanout histogram +system.membus.snoop_fanout::samples 1012128 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001625 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040282 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1012051 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1641 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1010483 99.84% 99.84% # Request fanout histogram +system.membus.snoop_fanout::2 1645 0.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1013692 # Request fanout histogram -system.membus.reqLayer0.occupancy 354973500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1012128 # Request fanout histogram +system.membus.reqLayer0.occupancy 355014500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388325000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388301500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1016908044 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1012808227 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2204699193 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2201176288 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 86072153 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 86060868 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 494bbffd2..4fb206696 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137726 # Number of seconds simulated -sim_ticks 5137726358500 # Number of ticks simulated -final_tick 5137726358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.141985 # Number of seconds simulated +sim_ticks 5141984685500 # Number of ticks simulated +final_tick 5141984685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193743 # Simulator instruction rate (inst/s) -host_op_rate 385165 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4079424438 # Simulator tick rate (ticks/s) -host_mem_usage 1056160 # Number of bytes of host memory used -host_seconds 1259.42 # Real time elapsed on the host -sim_insts 244004222 # Number of instructions simulated -sim_ops 485086710 # Number of ops (including micro ops) simulated +host_inst_rate 264541 # Simulator instruction rate (inst/s) +host_op_rate 525842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5597553756 # Simulator tick rate (ticks/s) +host_mem_usage 1010248 # Number of bytes of host memory used +host_seconds 918.61 # Real time elapsed on the host +sim_insts 243010444 # Number of instructions simulated +sim_ops 483045307 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 380096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4972288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 215232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2058496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 369024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3382272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 439936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4996672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 212288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2043456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 288960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3313664 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11408192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 380096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 215232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 369024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9193728 # Number of bytes written to this memory -system.physmem.bytes_written::total 9193728 # Number of bytes written to this memory +system.physmem.bytes_read::total 11325056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 439936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 212288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 288960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 941184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9131200 # Number of bytes written to this memory +system.physmem.bytes_written::total 9131200 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5939 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 77692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 32164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5766 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 52848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6874 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 31929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 51776 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178253 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143652 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143652 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176954 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142675 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142675 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 73981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 967799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 400663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 71826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 658321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2220475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 73981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 71826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1789455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1789455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1789455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 85558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 971740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 397406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 56196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 644433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2202468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 85558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 56196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 183039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1775812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1775812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1775812 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 73981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 967799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 400663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 71826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 658321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4009929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 94617 # Number of read requests accepted -system.physmem.writeReqs 88760 # Number of write requests accepted -system.physmem.readBursts 94617 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 88760 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6047936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 5680640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6055488 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5680640 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 85558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 971740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 397406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 56196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 644433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3978280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 91559 # Number of read requests accepted +system.physmem.writeReqs 81706 # Number of write requests accepted +system.physmem.readBursts 91559 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 81706 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5853184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 5229184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5859776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5229184 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 28899 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6147 # Per bank write bursts -system.physmem.perBankRdBursts::1 5269 # Per bank write bursts -system.physmem.perBankRdBursts::2 5685 # Per bank write bursts -system.physmem.perBankRdBursts::3 5978 # Per bank write bursts -system.physmem.perBankRdBursts::4 5788 # Per bank write bursts -system.physmem.perBankRdBursts::5 5231 # Per bank write bursts -system.physmem.perBankRdBursts::6 5218 # Per bank write bursts -system.physmem.perBankRdBursts::7 5097 # Per bank write bursts -system.physmem.perBankRdBursts::8 6282 # Per bank write bursts -system.physmem.perBankRdBursts::9 6366 # Per bank write bursts -system.physmem.perBankRdBursts::10 6408 # Per bank write bursts -system.physmem.perBankRdBursts::11 6175 # Per bank write bursts -system.physmem.perBankRdBursts::12 5716 # Per bank write bursts -system.physmem.perBankRdBursts::13 6642 # Per bank write bursts -system.physmem.perBankRdBursts::14 6153 # Per bank write bursts -system.physmem.perBankRdBursts::15 6344 # Per bank write bursts -system.physmem.perBankWrBursts::0 6191 # Per bank write bursts -system.physmem.perBankWrBursts::1 5213 # Per bank write bursts -system.physmem.perBankWrBursts::2 6082 # Per bank write bursts -system.physmem.perBankWrBursts::3 5966 # Per bank write bursts -system.physmem.perBankWrBursts::4 5232 # Per bank write bursts -system.physmem.perBankWrBursts::5 5147 # Per bank write bursts -system.physmem.perBankWrBursts::6 4857 # Per bank write bursts -system.physmem.perBankWrBursts::7 4466 # Per bank write bursts -system.physmem.perBankWrBursts::8 5491 # Per bank write bursts -system.physmem.perBankWrBursts::9 5559 # Per bank write bursts -system.physmem.perBankWrBursts::10 5838 # Per bank write bursts -system.physmem.perBankWrBursts::11 5586 # Per bank write bursts -system.physmem.perBankWrBursts::12 5717 # Per bank write bursts -system.physmem.perBankWrBursts::13 5929 # Per bank write bursts -system.physmem.perBankWrBursts::14 5787 # Per bank write bursts -system.physmem.perBankWrBursts::15 5699 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 24142 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5703 # Per bank write bursts +system.physmem.perBankRdBursts::1 4852 # Per bank write bursts +system.physmem.perBankRdBursts::2 5373 # Per bank write bursts +system.physmem.perBankRdBursts::3 5511 # Per bank write bursts +system.physmem.perBankRdBursts::4 5930 # Per bank write bursts +system.physmem.perBankRdBursts::5 4999 # Per bank write bursts +system.physmem.perBankRdBursts::6 5647 # Per bank write bursts +system.physmem.perBankRdBursts::7 5865 # Per bank write bursts +system.physmem.perBankRdBursts::8 5509 # Per bank write bursts +system.physmem.perBankRdBursts::9 5229 # Per bank write bursts +system.physmem.perBankRdBursts::10 5185 # Per bank write bursts +system.physmem.perBankRdBursts::11 5201 # Per bank write bursts +system.physmem.perBankRdBursts::12 6216 # Per bank write bursts +system.physmem.perBankRdBursts::13 6911 # Per bank write bursts +system.physmem.perBankRdBursts::14 6949 # Per bank write bursts +system.physmem.perBankRdBursts::15 6376 # Per bank write bursts +system.physmem.perBankWrBursts::0 5797 # Per bank write bursts +system.physmem.perBankWrBursts::1 4843 # Per bank write bursts +system.physmem.perBankWrBursts::2 5036 # Per bank write bursts +system.physmem.perBankWrBursts::3 5163 # Per bank write bursts +system.physmem.perBankWrBursts::4 5363 # Per bank write bursts +system.physmem.perBankWrBursts::5 4815 # Per bank write bursts +system.physmem.perBankWrBursts::6 4988 # Per bank write bursts +system.physmem.perBankWrBursts::7 5321 # Per bank write bursts +system.physmem.perBankWrBursts::8 4852 # Per bank write bursts +system.physmem.perBankWrBursts::9 4657 # Per bank write bursts +system.physmem.perBankWrBursts::10 4410 # Per bank write bursts +system.physmem.perBankWrBursts::11 4367 # Per bank write bursts +system.physmem.perBankWrBursts::12 5498 # Per bank write bursts +system.physmem.perBankWrBursts::13 5314 # Per bank write bursts +system.physmem.perBankWrBursts::14 5778 # Per bank write bursts +system.physmem.perBankWrBursts::15 5504 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 5136593386000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5140984417000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 94617 # Read request sizes (log2) +system.physmem.readPktSize::6 91559 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 88760 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 81706 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 86389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -161,1117 +161,1114 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4579 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.270307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.374177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.197981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16587 39.78% 39.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10275 24.64% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4266 10.23% 74.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2445 5.86% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1622 3.89% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1132 2.71% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 786 1.89% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 680 1.63% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3904 9.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41697 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4370 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.624485 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 178.940609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4367 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4370 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4370 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.311213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.106663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.785732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 51 1.17% 1.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 5 0.11% 1.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 8 0.18% 1.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3654 83.62% 85.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 60 1.37% 86.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 119 2.72% 89.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 59 1.35% 90.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 85 1.95% 92.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 116 2.65% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.30% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.11% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.21% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.07% 95.84% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 276.476998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.125046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 300.303961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15966 39.83% 39.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9813 24.48% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4306 10.74% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2350 5.86% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1723 4.30% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1131 2.82% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 740 1.85% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 595 1.48% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3460 8.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40084 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.316984 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.117398 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4096 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4098 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.938019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.673577 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.950142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 4 0.10% 1.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.07% 1.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.10% 1.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3475 84.80% 86.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 74 1.81% 88.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.68% 89.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 103 2.51% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 14 0.34% 92.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 88 2.15% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 45 1.10% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.12% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.20% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.20% 95.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 2 0.05% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.09% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 133 3.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.09% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.14% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.07% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.23% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4370 # Writes before turning the bus around for reads -system.physmem.totQLat 1101479246 # Total ticks spent queuing -system.physmem.totMemAccLat 2873335496 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 472495000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11655.99 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::60-63 4 0.10% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 126 3.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 13 0.32% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.05% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.37% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4098 # Writes before turning the bus around for reads +system.physmem.totQLat 1118460500 # Total ticks spent queuing +system.physmem.totMemAccLat 2833260500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 457280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12229.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30405.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30979.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.15 # Average write queue length when enqueuing -system.physmem.readRowHits 75876 # Number of row buffer hits during reads -system.physmem.writeRowHits 65681 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 28011110.37 # Average gap between requests -system.physmem.pageHitRate 77.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153536040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83535375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 346421400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279618480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94990329855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2239672524000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2585764947390 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.869445 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3685813216724 # Time in different power states -system.physmem_0.memoryStateTime::REF 127934040000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.88 # Average write queue length when enqueuing +system.physmem.readRowHits 73104 # Number of row buffer hits during reads +system.physmem.writeRowHits 59973 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.40 # Row buffer hit rate for writes +system.physmem.avgGap 29671222.79 # Average gap between requests +system.physmem.pageHitRate 76.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 146323800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79666125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 342256200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 267792480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96409908585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2240143266750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2587784324100 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.897651 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3686083069500 # Time in different power states +system.physmem_0.memoryStateTime::REF 128013860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17956780776 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19995411750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 161655480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 87978000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 390663000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 295410240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95244065640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2234394426750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580813181350 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.044329 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3685435461238 # Time in different power states -system.physmem_1.memoryStateTime::REF 127934040000 # Time in different power states +system.physmem_1.actEnergy 156711240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 371092800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 261662400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96741256995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2232099467250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2580110601720 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.145421 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685614437250 # Time in different power states +system.physmem_1.memoryStateTime::REF 128013860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18309070012 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20427995000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 810473886 # number of cpu cycles simulated +system.cpu0.numCycles 1069587616 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70312072 # Number of instructions committed -system.cpu0.committedOps 143658243 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 131612768 # Number of integer alu accesses +system.cpu0.committedInsts 72296493 # Number of instructions committed +system.cpu0.committedOps 147472982 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 135372886 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 897074 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13988759 # number of instructions that are conditional controls -system.cpu0.num_int_insts 131612768 # number of integer instructions +system.cpu0.num_func_calls 990052 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14329607 # number of instructions that are conditional controls +system.cpu0.num_int_insts 135372886 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 240911367 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113282572 # number of times the integer registers were written +system.cpu0.num_int_register_reads 248231827 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116398223 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82064957 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 54880945 # number of times the CC registers were written -system.cpu0.num_mem_refs 13139441 # number of memory refs -system.cpu0.num_load_insts 9809284 # Number of load instructions -system.cpu0.num_store_insts 3330157 # Number of store instructions -system.cpu0.num_idle_cycles 769348747.137634 # Number of idle cycles -system.cpu0.num_busy_cycles 41125138.862366 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050742 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949258 # Percentage of idle cycles -system.cpu0.Branches 15218344 # Number of branches fetched -system.cpu0.op_class::No_OpClass 83498 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 130336285 90.73% 90.78% # Class of executed instruction -system.cpu0.op_class::IntMult 55624 0.04% 90.82% # Class of executed instruction -system.cpu0.op_class::IntDiv 45353 0.03% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.85% # Class of executed instruction -system.cpu0.op_class::MemRead 9807642 6.83% 97.68% # Class of executed instruction -system.cpu0.op_class::MemWrite 3330157 2.32% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 84256506 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56232303 # number of times the CC registers were written +system.cpu0.num_mem_refs 13832544 # number of memory refs +system.cpu0.num_load_insts 10299641 # Number of load instructions +system.cpu0.num_store_insts 3532903 # Number of store instructions +system.cpu0.num_idle_cycles 1014098909.517961 # Number of idle cycles +system.cpu0.num_busy_cycles 55488706.482039 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051879 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948121 # Percentage of idle cycles +system.cpu0.Branches 15685270 # Number of branches fetched +system.cpu0.op_class::No_OpClass 94460 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 133436032 90.48% 90.55% # Class of executed instruction +system.cpu0.op_class::IntMult 61341 0.04% 90.59% # Class of executed instruction +system.cpu0.op_class::IntDiv 50787 0.03% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::MemRead 10297804 6.98% 97.60% # Class of executed instruction +system.cpu0.op_class::MemWrite 3532903 2.40% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143658559 # Class of executed instruction +system.cpu0.op_class::total 147473327 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1637472 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999430 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19610556 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1637984 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.972373 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1636478 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19597198 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1636990 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.971483 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 233.382237 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 253.425972 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 25.191221 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.455825 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.494973 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.049202 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.606115 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 212.665668 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 114.727666 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360559 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.415363 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.224077 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # 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number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171580 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 65147 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 193119 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 258266 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 230855 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 542805 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 773660 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 296002 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 735924 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1031926 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 186313 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5694639490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12720746872 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 18415386362 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30666876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33145024000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63811900000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 650679500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 751025500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1401705000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31317555500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33896049500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65213605000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060310 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085775 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.047056 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036227 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032336 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020407 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.868291 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.849390 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.553932 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065167 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.036489 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063668 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086004 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.047622 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12866.345889 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13535.559935 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13354.223691 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38777.876089 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38258.052104 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38463.188379 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14888.014797 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14528.099255 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14618.887116 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20466.223344 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18266.402984 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18922.814753 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19238.516936 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17285.408374 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17845.646260 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164598.691449 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161957.977445 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163216.400445 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178709.008514 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 203474.803576 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 191176.350245 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164869.155164 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162693.488622 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163731.097648 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1547054 # number of writebacks +system.cpu0.dcache.writebacks::total 1547054 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 65 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 367229 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 367294 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1711 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33525 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 35236 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1776 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 400754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 402530 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1776 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 400754 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 402530 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 158637 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 415762 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 574399 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60622 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 105442 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 166064 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 61803 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 187828 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 249631 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 219259 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 521204 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 740463 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 281062 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 709032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 990094 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 185046 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 202918 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 387964 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3480 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2043 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 5523 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 188526 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 204961 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 393487 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2187272000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5900092500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8087364500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3897729991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 6072748397 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9970478388 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1081694500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2966872000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 4048566500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6085001991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11972840897 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18057842888 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7166696491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14939712897 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 22106409388 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30549904500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32777781000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63327685500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 637496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 432772500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1070269000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31187401000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33210553500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64397954500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.089416 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045021 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033523 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.034243 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019733 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.860275 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.857294 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.535678 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048909 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067435 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034971 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061706 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.089208 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045753 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13787.905722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14191.033572 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14079.698084 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64295.635099 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57593.258825 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 60039.974877 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17502.297623 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15795.685414 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16218.204069 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27752.575680 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22971.506161 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24387.231891 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25498.631942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21070.576359 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22327.586459 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165093.568626 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161532.150918 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163230.829407 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183188.649425 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211831.864905 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 193783.994206 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165427.585585 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162033.525890 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163659.674907 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 865313 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.808042 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 127930489 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 865825 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 147.755596 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149027837500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 256.241174 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 140.482462 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 114.084406 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.500471 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.274380 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.222821 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997672 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 856629 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.743625 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 130224655 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 857141 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 151.929093 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149031497500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 143.311880 # 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number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22174 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22174 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22174 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22174 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 176943 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 349338 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 526281 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 176943 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 349338 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 526281 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 176943 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 349338 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 526281 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2525467000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4769426473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7294893473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2525467000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4769426473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7294893473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2525467000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4769426473 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7294893473 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004014 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004014 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004014 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13861.213825 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606018119 # number of cpu cycles simulated +system.cpu1.numCycles 2608369012 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35722790 # Number of instructions committed -system.cpu1.committedOps 69377917 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64437935 # Number of integer alu accesses +system.cpu1.committedInsts 35935781 # Number of instructions committed +system.cpu1.committedOps 69853480 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64823976 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 498036 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6548156 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64437935 # number of integer instructions +system.cpu1.num_func_calls 488968 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6599189 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64823976 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119381439 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55453390 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120030856 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55861909 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36402445 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27104510 # number of times the CC registers were written -system.cpu1.num_mem_refs 4834095 # number of memory refs -system.cpu1.num_load_insts 2964009 # Number of load instructions -system.cpu1.num_store_insts 1870086 # Number of store instructions -system.cpu1.num_idle_cycles 2478102522.985643 # Number of idle cycles -system.cpu1.num_busy_cycles 127915596.014357 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049085 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950915 # Percentage of idle cycles -system.cpu1.Branches 7225753 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35671 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64456455 92.91% 92.96% # Class of executed instruction -system.cpu1.op_class::IntMult 31131 0.04% 93.00% # Class of executed instruction -system.cpu1.op_class::IntDiv 22623 0.03% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.03% # Class of executed instruction -system.cpu1.op_class::MemRead 2962280 4.27% 97.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 1870086 2.70% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36569866 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27235503 # number of times the CC registers were written +system.cpu1.num_mem_refs 4739526 # number of memory refs +system.cpu1.num_load_insts 2929606 # Number of load instructions +system.cpu1.num_store_insts 1809920 # Number of store instructions +system.cpu1.num_idle_cycles 2476291441.144386 # Number of idle cycles +system.cpu1.num_busy_cycles 132077570.855614 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050636 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949364 # Percentage of idle cycles +system.cpu1.Branches 7267259 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35769 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 65023245 93.08% 93.14% # Class of executed instruction +system.cpu1.op_class::IntMult 31643 0.05% 93.18% # Class of executed instruction +system.cpu1.op_class::IntDiv 24977 0.04% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::MemRead 2928241 4.19% 97.41% # Class of executed instruction +system.cpu1.op_class::MemWrite 1809920 2.59% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69378246 # Class of executed instruction +system.cpu1.op_class::total 69853795 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29560975 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29560975 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 321330 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26625449 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26036610 # Number of BTB hits +system.cpu2.branchPred.lookups 28595724 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28595724 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 274281 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 25954960 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25419524 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.788435 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 603794 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 66654 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155113045 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.937057 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 541766 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 58217 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155590039 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 11047280 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145686023 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29560975 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26640404 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 142542790 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 677515 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 104928 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8867 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 68985 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3604542 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 166149 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3283 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154116964 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.860489 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.036370 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9827756 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141445049 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28595724 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 25961290 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 144324316 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 577708 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 89529 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 4628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 9926 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 52140 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 25 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1381 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3207378 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 141789 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2491 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154597903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.800587 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.004500 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98277439 63.77% 63.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 921613 0.60% 64.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23771065 15.42% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 603849 0.39% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 843324 0.55% 80.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 864608 0.56% 81.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 573617 0.37% 81.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 772001 0.50% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27489448 17.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 100285595 64.87% 64.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 850088 0.55% 65.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23359910 15.11% 80.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 558025 0.36% 80.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 768716 0.50% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 809103 0.52% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 512827 0.33% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 703407 0.45% 82.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 26750232 17.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154116964 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.190577 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.939225 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10113688 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93745988 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23732554 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5061206 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 339409 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283817902 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 339409 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12262766 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76655623 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4610961 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26368994 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12755160 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282570010 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 203292 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5910187 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 59652 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4622392 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337562699 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 617313701 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 378956511 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 176 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325317107 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12245592 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 169706 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 171154 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24674635 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6903065 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3842483 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 404867 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 342392 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280633357 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 431682 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278499537 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 103065 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 9014489 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13791367 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 66778 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154116964 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.807066 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.400549 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154597903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.183789 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.909088 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8590820 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95748375 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 20322096 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4023271 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 289506 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 275783905 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 289506 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10203934 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77122652 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4692669 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 22463307 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14202064 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 274713209 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 193941 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5398657 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 70031 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 7189088 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 328421156 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 598952608 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 367856783 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 202 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 317944423 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10476733 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 154897 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 156262 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19984245 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6287198 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3639298 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 400920 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 367403 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 273029174 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 403661 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 271361789 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 92310 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7713990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11716947 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 58327 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154597903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.755275 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.385225 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90926640 59.00% 59.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5330208 3.46% 62.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3853102 2.50% 64.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3864237 2.51% 67.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22585971 14.66% 82.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2780196 1.80% 83.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24046184 15.60% 99.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 494962 0.32% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 235464 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 93164208 60.26% 60.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5135729 3.32% 63.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3649233 2.36% 65.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3187928 2.06% 68.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23055647 14.91% 82.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2154571 1.39% 84.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23598215 15.26% 99.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 439899 0.28% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 212473 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154116964 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154597903 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1774419 86.10% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 221659 10.76% 96.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 64684 3.14% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1212353 81.77% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 211907 14.29% 96.06% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 58391 3.94% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 87958 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 267524922 96.06% 96.09% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 58980 0.02% 96.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 56493 0.02% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 63 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 7208859 2.59% 98.72% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3562262 1.28% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 71762 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 261142020 96.23% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 52428 0.02% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48121 0.02% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 75 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6661415 2.45% 98.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3385968 1.25% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278499537 # Type of FU issued -system.cpu2.iq.rate 1.795462 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2060762 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007400 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713279610 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 290083917 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276907807 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 101 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280472218 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 745560 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 271361789 # Type of FU issued +system.cpu2.iq.rate 1.744082 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1482651 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005464 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 698896144 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 281150786 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 269884047 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 272772537 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 141 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 697485 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1225052 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5875 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5188 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 625672 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1044107 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5365 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4726 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 557112 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 750058 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 26954 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 749552 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 25864 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 339409 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70544458 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 3078967 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281065039 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 38553 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6903084 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3842483 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 256263 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 170697 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2578390 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5188 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 180466 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 193564 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374030 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 277914745 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 7063605 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 530025 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 289506 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69224885 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4893125 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 273432835 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 29776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6287198 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3639298 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 235948 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 164149 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4411192 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4726 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 153905 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164065 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 317970 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 270855594 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6536848 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 455372 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10537501 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28240197 # Number of branches executed -system.cpu2.iew.exec_stores 3473896 # Number of stores executed -system.cpu2.iew.exec_rate 1.791692 # Inst execution rate -system.cpu2.iew.wb_sent 277728046 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276907908 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215869899 # num instructions producing a value -system.cpu2.iew.wb_consumers 354183211 # num instructions consuming a value +system.cpu2.iew.exec_refs 9843230 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27477788 # Number of branches executed +system.cpu2.iew.exec_stores 3306382 # Number of stores executed +system.cpu2.iew.exec_rate 1.740829 # Inst execution rate +system.cpu2.iew.wb_sent 270693369 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 269884157 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 210625616 # num instructions producing a value +system.cpu2.iew.wb_consumers 345602988 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.785201 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609487 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.734585 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609444 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9010167 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 364904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325088 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152771285 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.780770 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.657176 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7711989 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 345334 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 277097 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153447715 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.731657 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.637088 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94646882 61.95% 61.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4418156 2.89% 64.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1318603 0.86% 65.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24750822 16.20% 81.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 992364 0.65% 82.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 731797 0.48% 83.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 443039 0.29% 83.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23300929 15.25% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2168693 1.42% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 96780970 63.07% 63.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4222028 2.75% 65.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1231000 0.80% 66.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24221852 15.79% 82.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 924771 0.60% 83.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 693299 0.45% 83.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 425605 0.28% 83.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 22935468 14.95% 98.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2012722 1.31% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152771285 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137969360 # Number of instructions committed -system.cpu2.commit.committedOps 272050550 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153447715 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 134778170 # Number of instructions committed +system.cpu2.commit.committedOps 265718845 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8894843 # Number of memory references committed -system.cpu2.commit.loads 5678032 # Number of loads committed -system.cpu2.commit.membars 160530 # Number of memory barriers committed -system.cpu2.commit.branches 27847068 # Number of branches committed +system.cpu2.commit.refs 8325277 # Number of memory references committed +system.cpu2.commit.loads 5243091 # Number of loads committed +system.cpu2.commit.membars 153740 # Number of memory barriers committed +system.cpu2.commit.branches 27132938 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248702825 # Number of committed integer instructions. -system.cpu2.commit.function_calls 458806 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 52824 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 262991815 96.67% 96.69% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 56918 0.02% 96.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 54179 0.02% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5677987 2.09% 98.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3216811 1.18% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 242753564 # Number of committed integer instructions. +system.cpu2.commit.function_calls 416792 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 41984 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 257254606 96.81% 96.83% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 50787 0.02% 96.85% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 46205 0.02% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5243061 1.97% 98.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3082186 1.16% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 272050550 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2168693 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 431630642 # The number of ROB reads -system.cpu2.rob.rob_writes 563473683 # The number of ROB writes -system.cpu2.timesIdled 116646 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 996081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4908046353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137969360 # Number of Instructions Simulated -system.cpu2.committedOps 272050550 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.124257 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.124257 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.889476 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.889476 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370420908 # number of integer regfile reads -system.cpu2.int_regfile_writes 221942656 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73069 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 141352578 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108476747 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90603281 # number of misc regfile reads -system.cpu2.misc_regfile_writes 149391 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3552124 # Transaction distribution -system.iobus.trans_dist::ReadResp 3552124 # Transaction distribution -system.iobus.trans_dist::WriteReq 57703 # Transaction distribution -system.iobus.trans_dist::WriteResp 57703 # Transaction distribution -system.iobus.trans_dist::MessageReq 1656 # Transaction distribution -system.iobus.trans_dist::MessageResp 1656 # Transaction distribution +system.cpu2.commit.op_class_0::total 265718845 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2012722 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 424836983 # The number of ROB reads +system.cpu2.rob.rob_writes 548017282 # The number of ROB writes +system.cpu2.timesIdled 100227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 992136 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4909996040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 134778170 # Number of Instructions Simulated +system.cpu2.committedOps 265718845 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.154416 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.154416 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.866239 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.866239 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 360832495 # number of integer regfile reads +system.cpu2.int_regfile_writes 216221900 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73134 # number of floating regfile reads +system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes +system.cpu2.cc_regfile_reads 137826475 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106107258 # number of cc regfile writes +system.cpu2.misc_regfile_reads 87959882 # number of misc regfile reads +system.cpu2.misc_regfile_writes 137617 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3552161 # Transaction distribution +system.iobus.trans_dist::ReadResp 3552161 # Transaction distribution +system.iobus.trans_dist::WriteReq 57740 # Transaction distribution +system.iobus.trans_dist::WriteResp 57740 # Transaction distribution +system.iobus.trans_dist::MessageReq 1667 # Transaction distribution +system.iobus.trans_dist::MessageResp 1667 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080216 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27854 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27868 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95250 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95250 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7222966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7124546 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7223136 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540108 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540117 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13927 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13934 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6602845 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2765072 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3568475 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6602951 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2194728 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5295000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3095000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 748000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 140109000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 140118000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 421000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 340000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11369000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8907000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 144756051 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 119418499 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 299839000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 295238000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30990000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 23500000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1161000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 920000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47570 # number of replacements -system.iocache.tags.tagsinuse 0.092294 # Cycle average of tags in use +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.105025 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000591335509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092294 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005768 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005768 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000694858009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.105025 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006564 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006564 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428625 # Number of tag accesses -system.iocache.tags.data_accesses 428625 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 905 # number of demand (read+write) misses -system.iocache.demand_misses::total 905 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 905 # number of overall misses -system.iocache.overall_misses::total 905 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128938756 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128938756 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3283387295 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3283387295 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 128938756 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 128938756 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 128938756 # number of overall miss cycles -system.iocache.overall_miss_latency::total 128938756 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses +system.iocache.demand_misses::total 908 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses +system.iocache.overall_misses::total 908 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 17834920 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 17834920 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3008484579 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3008484579 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 17834920 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 17834920 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 17834920 # number of overall miss cycles +system.iocache.overall_miss_latency::total 17834920 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 905 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 905 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 905 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 905 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1280,323 +1277,323 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142473.763536 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70277.981485 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 70277.981485 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 142473.763536 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 142473.763536 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 19641.982379 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 64393.933626 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 64393.933626 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 19641.982379 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 19641.982379 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 771 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27816 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 27816 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 771 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 771 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 771 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 771 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90388756 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1892587295 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1892587295 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 90388756 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 90388756 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.851934 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.595377 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.595377 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.851934 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.851934 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117235.740597 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68039.520240 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.520240 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 150 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 23200 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 23200 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 150 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 150 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 150 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 150 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10334920 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1848484579 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1848484579 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10334920 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10334920 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.165198 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.496575 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.496575 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.165198 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.165198 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68899.466667 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79676.059440 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79676.059440 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 105297 # number of replacements -system.l2c.tags.tagsinuse 64829.932138 # Cycle average of tags in use -system.l2c.tags.total_refs 4653506 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169379 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.473925 # Average number of references to valid blocks. +system.l2c.tags.replacements 104099 # number of replacements +system.l2c.tags.tagsinuse 64798.751400 # Cycle average of tags in use +system.l2c.tags.total_refs 4622477 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168145 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.491017 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51173.407982 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134359 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1534.003878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4961.516829 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 244.491161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1538.007484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.330522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1242.728330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4127.311591 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.780844 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50975.916354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1575.171206 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4997.364493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 516.989893 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1851.248692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 5.076348 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 959.125226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3917.724589 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.777831 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.023407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000127 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.018963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.062978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989226 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64082 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3909 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52613 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977814 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41530530 # Number of tag accesses -system.l2c.tags.data_accesses 41530530 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 18603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10268 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 13451 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7422 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 62068 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13128 # number of ReadReq hits -system.l2c.ReadReq_hits::total 124940 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.024035 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076254 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007889 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000077 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.014635 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.059780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988750 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64046 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3569 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7409 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52933 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977264 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41263442 # Number of tag accesses +system.l2c.tags.data_accesses 41263442 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10440 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 11603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6238 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 52514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits +system.l2c.ReadReq_hits::total 110945 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1547245 # number of Writeback hits -system.l2c.Writeback_hits::total 1547245 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 73 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 62 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 120 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56139 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 39496 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 63875 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 159510 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 289595 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 170749 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 390398 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 850742 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 472949 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 223727 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 618198 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 1314874 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 18603 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10270 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 289595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 529088 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 13451 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7422 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 170749 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 263223 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 62068 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13128 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 390398 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 682073 # number of demand (read+write) hits -system.l2c.demand_hits::total 2450068 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 18603 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10270 # number of overall hits -system.l2c.overall_hits::cpu0.inst 289595 # number of overall hits -system.l2c.overall_hits::cpu0.data 529088 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 13451 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7422 # number of overall hits -system.l2c.overall_hits::cpu1.inst 170749 # number of overall hits -system.l2c.overall_hits::cpu1.data 263223 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 62068 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13128 # number of overall hits -system.l2c.overall_hits::cpu2.inst 390398 # number of overall hits -system.l2c.overall_hits::cpu2.data 682073 # number of overall hits -system.l2c.overall_hits::total 2450068 # number of overall hits +system.l2c.Writeback_hits::writebacks 1547054 # number of Writeback hits +system.l2c.Writeback_hits::total 1547054 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 89 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 110 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 271 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 61093 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 64950 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159276 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 323982 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 173626 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 344819 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 842427 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 508184 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 215306 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 591519 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 1315009 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 19237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10442 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 323982 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 569277 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6238 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 173626 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 248539 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 52514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 344819 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 656469 # number of demand (read+write) hits +system.l2c.demand_hits::total 2427659 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 19237 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10442 # number of overall hits +system.l2c.overall_hits::cpu0.inst 323982 # number of overall hits +system.l2c.overall_hits::cpu0.data 569277 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 11603 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6238 # number of overall hits +system.l2c.overall_hits::cpu1.inst 173626 # number of overall hits +system.l2c.overall_hits::cpu1.data 248539 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 52514 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits +system.l2c.overall_hits::cpu2.inst 344819 # number of overall hits +system.l2c.overall_hits::cpu2.data 656469 # number of overall hits +system.l2c.overall_hits::total 2427659 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 33 # number of ReadReq misses -system.l2c.ReadReq_misses::total 38 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 455 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 314 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 620 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1389 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63544 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 27850 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 39321 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130715 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 5939 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 3363 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 5766 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15068 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 14540 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 4565 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 13791 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 32896 # number of ReadSharedReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 22 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.231445 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010544 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019996 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.021822 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.013620 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.109644 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000531 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.072243 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.036020 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.109644 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000531 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.072243 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036020 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 82787.878788 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22609.872611 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20978.225806 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21526.766595 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65325.332136 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69441.634241 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67734.960027 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73498.192573 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72655.969332 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77973.823508 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76651.312922 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66357.704766 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71657.092559 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 70024.327007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66357.704766 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71657.092559 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 70024.327007 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152098.675347 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149457.967672 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150716.387656 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167209.008514 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191973.178001 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 179675.531915 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152388.307169 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150211.166202 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 151249.478404 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790087 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.842857 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.523404 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.448699 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.380207 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.231292 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018746 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012925 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.009137 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.023290 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019917 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012728 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018746 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.114641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.073220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035277 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018746 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.114641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.073220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035277 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 142977.272727 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70583.025830 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70739.830508 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70690.476190 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117000.591541 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 120028.135432 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118803.919810 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121557.883630 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124134.448417 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121974.191663 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 128086.764828 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126257.446809 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121557.883630 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117794.030825 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121895.958661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120655.342764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121557.883630 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117794.030825 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121895.958661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120655.342764 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152593.568626 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149032.145990 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150730.826829 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171688.649425 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200329.907000 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 182283.269962 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152946.044577 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 149543.469245 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 151173.698242 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5066901 # Transaction distribution -system.membus.trans_dist::ReadResp 5115808 # Transaction distribution -system.membus.trans_dist::WriteReq 13888 # Transaction distribution -system.membus.trans_dist::WriteResp 13888 # Transaction distribution -system.membus.trans_dist::Writeback 143652 # Transaction distribution -system.membus.trans_dist::CleanEvict 8856 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1645 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1645 # Transaction distribution -system.membus.trans_dist::ReadExReq 130459 # Transaction distribution -system.membus.trans_dist::ReadExResp 130459 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48907 # Transaction distribution -system.membus.trans_dist::MessageReq 1656 # Transaction distribution -system.membus.trans_dist::MessageResp 1656 # Transaction distribution +system.membus.trans_dist::ReadReq 5081876 # Transaction distribution +system.membus.trans_dist::ReadResp 5130307 # Transaction distribution +system.membus.trans_dist::WriteReq 13937 # Transaction distribution +system.membus.trans_dist::WriteResp 13937 # Transaction distribution +system.membus.trans_dist::Writeback 142675 # Transaction distribution +system.membus.trans_dist::CleanEvict 8457 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1667 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1667 # Transaction distribution +system.membus.trans_dist::ReadExReq 129637 # Transaction distribution +system.membus.trans_dist::ReadExResp 129637 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48432 # Transaction distribution +system.membus.trans_dist::MessageReq 1667 # Transaction distribution +system.membus.trans_dist::MessageResp 1667 # Transaction distribution +system.membus.trans_dist::BadAddressError 1 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10626768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10772166 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074345 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17606208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27248990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3023616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3023616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30279230 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 694 # Total snoops (count) -system.membus.snoop_fanout::samples 5463095 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017408 # Request fanout histogram +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3067080 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461494 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10653122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142139 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142139 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10798595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568475 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6134157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17466624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27169256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3035200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3035200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30211124 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 409 # Total snoops (count) +system.membus.snoop_fanout::samples 5475610 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017446 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5461439 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1656 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5473943 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5463095 # Request fanout histogram -system.membus.reqLayer0.occupancy 232635000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5475610 # Request fanout histogram +system.membus.reqLayer0.occupancy 227177500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 304127000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 301308000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2322000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1840000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 583726731 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 538434425 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1161000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 920000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1349926167 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1326481306 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 52433855 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 41176558 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1814,53 +1815,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 5228525 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7442369 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1636010 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 961008 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1644 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1644 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 290225 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 290225 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 865835 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1348541 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 1161 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 27816 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2596558 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15078411 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72306 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 219403 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17966678 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55412672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213513438 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 261576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 779088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 269966774 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176011 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10394757 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.029410 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.168953 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 5040257 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2546109 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 319 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1148 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1148 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 5235870 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7440960 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13939 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13939 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1628762 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 950991 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1645 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1645 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289206 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289206 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 857150 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1347950 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 920 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 23200 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2570707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15105454 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 66396 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204903 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17947460 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54857344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213491432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 241048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 697376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 269287200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 238040 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10439686 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.005090 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.071166 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10089048 97.06% 97.06% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 305709 2.94% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 10386543 99.49% 99.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 53143 0.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10394757 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2840392499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 10439686 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2709674498 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 358500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 251420 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 856033294 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 789952436 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1941516813 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1874874404 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 27469982 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23291487 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100352159 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 94859175 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |