diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
3 files changed, 3570 insertions, 3561 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index bca94218b..442dd3c07 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.129874 # Number of seconds simulated -sim_ticks 5129873616500 # Number of ticks simulated -final_tick 5129873616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.129877 # Number of seconds simulated +sim_ticks 5129876981500 # Number of ticks simulated +final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122712 # Simulator instruction rate (inst/s) -host_op_rate 242564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1543734215 # Simulator tick rate (ticks/s) -host_mem_usage 750608 # Number of bytes of host memory used -host_seconds 3323.03 # Real time elapsed on the host -sim_insts 407773893 # Number of instructions simulated -sim_ops 806048632 # Number of ops (including micro ops) simulated +host_inst_rate 179907 # Simulator instruction rate (inst/s) +host_op_rate 355619 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2263051238 # Simulator tick rate (ticks/s) +host_mem_usage 804092 # Number of bytes of host memory used +host_seconds 2266.80 # Real time elapsed on the host +sim_insts 407812863 # Number of instructions simulated +sim_ops 806114915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1049344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10817792 # Number of bytes read from this memory -system.physmem.bytes_read::total 11900032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1049344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1049344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6600896 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory +system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1048192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6597248 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9590976 # Number of bytes written to this memory +system.physmem.bytes_written::total 9587328 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169028 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185938 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 103139 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 186153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 103082 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149859 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2108783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2319751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204556 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204556 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1286756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2322432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1286044 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1869632 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1286756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 588403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2108783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4189384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185938 # Number of read requests accepted -system.physmem.writeReqs 149859 # Number of write requests accepted -system.physmem.readBursts 185938 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149859 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11881152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue -system.physmem.bytesWritten 9589248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11900032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9590976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1868920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1286044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 588402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 204331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2111701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4191352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 186153 # Number of read requests accepted +system.physmem.writeReqs 149802 # Number of write requests accepted +system.physmem.readBursts 186153 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149802 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11895360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18432 # Total number of bytes read from write queue +system.physmem.bytesWritten 9586112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11913792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9587328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1710 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11383 # Per bank write bursts -system.physmem.perBankRdBursts::1 10659 # Per bank write bursts -system.physmem.perBankRdBursts::2 11850 # Per bank write bursts -system.physmem.perBankRdBursts::3 11657 # Per bank write bursts -system.physmem.perBankRdBursts::4 11883 # Per bank write bursts -system.physmem.perBankRdBursts::5 11508 # Per bank write bursts -system.physmem.perBankRdBursts::6 11028 # Per bank write bursts -system.physmem.perBankRdBursts::7 11462 # Per bank write bursts -system.physmem.perBankRdBursts::8 11217 # Per bank write bursts -system.physmem.perBankRdBursts::9 11477 # Per bank write bursts -system.physmem.perBankRdBursts::10 11649 # Per bank write bursts -system.physmem.perBankRdBursts::11 12129 # Per bank write bursts -system.physmem.perBankRdBursts::12 11737 # Per bank write bursts -system.physmem.perBankRdBursts::13 12518 # Per bank write bursts -system.physmem.perBankRdBursts::14 12268 # Per bank write bursts -system.physmem.perBankRdBursts::15 11218 # Per bank write bursts -system.physmem.perBankWrBursts::0 10090 # Per bank write bursts -system.physmem.perBankWrBursts::1 9375 # Per bank write bursts -system.physmem.perBankWrBursts::2 9103 # Per bank write bursts -system.physmem.perBankWrBursts::3 8918 # Per bank write bursts -system.physmem.perBankWrBursts::4 9314 # Per bank write bursts -system.physmem.perBankWrBursts::5 9243 # Per bank write bursts -system.physmem.perBankWrBursts::6 8603 # Per bank write bursts -system.physmem.perBankWrBursts::7 8925 # Per bank write bursts -system.physmem.perBankWrBursts::8 9240 # Per bank write bursts -system.physmem.perBankWrBursts::9 9268 # Per bank write bursts -system.physmem.perBankWrBursts::10 9747 # Per bank write bursts -system.physmem.perBankWrBursts::11 9397 # Per bank write bursts -system.physmem.perBankWrBursts::12 9475 # Per bank write bursts -system.physmem.perBankWrBursts::13 9702 # Per bank write bursts -system.physmem.perBankWrBursts::14 10013 # Per bank write bursts -system.physmem.perBankWrBursts::15 9419 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1739 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11465 # Per bank write bursts +system.physmem.perBankRdBursts::1 11004 # Per bank write bursts +system.physmem.perBankRdBursts::2 11873 # Per bank write bursts +system.physmem.perBankRdBursts::3 11540 # Per bank write bursts +system.physmem.perBankRdBursts::4 11961 # Per bank write bursts +system.physmem.perBankRdBursts::5 11322 # Per bank write bursts +system.physmem.perBankRdBursts::6 11640 # Per bank write bursts +system.physmem.perBankRdBursts::7 11420 # Per bank write bursts +system.physmem.perBankRdBursts::8 11351 # Per bank write bursts +system.physmem.perBankRdBursts::9 11861 # Per bank write bursts +system.physmem.perBankRdBursts::10 11826 # Per bank write bursts +system.physmem.perBankRdBursts::11 12031 # Per bank write bursts +system.physmem.perBankRdBursts::12 11538 # Per bank write bursts +system.physmem.perBankRdBursts::13 12375 # Per bank write bursts +system.physmem.perBankRdBursts::14 11569 # Per bank write bursts +system.physmem.perBankRdBursts::15 11089 # Per bank write bursts +system.physmem.perBankWrBursts::0 10234 # Per bank write bursts +system.physmem.perBankWrBursts::1 9627 # Per bank write bursts +system.physmem.perBankWrBursts::2 9640 # Per bank write bursts +system.physmem.perBankWrBursts::3 9149 # Per bank write bursts +system.physmem.perBankWrBursts::4 9237 # Per bank write bursts +system.physmem.perBankWrBursts::5 9047 # Per bank write bursts +system.physmem.perBankWrBursts::6 8744 # Per bank write bursts +system.physmem.perBankWrBursts::7 8727 # Per bank write bursts +system.physmem.perBankWrBursts::8 9070 # Per bank write bursts +system.physmem.perBankWrBursts::9 9221 # Per bank write bursts +system.physmem.perBankWrBursts::10 9815 # Per bank write bursts +system.physmem.perBankWrBursts::11 9405 # Per bank write bursts +system.physmem.perBankWrBursts::12 9499 # Per bank write bursts +system.physmem.perBankWrBursts::13 9604 # Per bank write bursts +system.physmem.perBankWrBursts::14 9640 # Per bank write bursts +system.physmem.perBankWrBursts::15 9124 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 5129873502000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5129876930000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185938 # Read request sizes (log2) +system.physmem.readPktSize::6 186153 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149859 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149802 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 171145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see @@ -159,112 +159,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.717718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.081512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 320.465816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27438 38.17% 38.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17395 24.20% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7359 10.24% 72.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4225 5.88% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2947 4.10% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2054 2.86% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1404 1.95% 87.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1166 1.62% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7887 10.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71875 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7354 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.241501 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 560.072825 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7353 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 72700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.480165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.038242 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7354 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7354 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.374218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.656947 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.477131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6319 85.93% 85.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51 0.69% 86.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.45% 87.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 263 3.58% 90.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 273 3.71% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 24 0.33% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 24 0.33% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.20% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 39 0.53% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.08% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 229 3.11% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 25 0.34% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 13 0.18% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.14% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7354 # Writes before turning the bus around for reads -system.physmem.totQLat 1988147750 # Total ticks spent queuing -system.physmem.totMemAccLat 5468954000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 928215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10709.52 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads +system.physmem.totQLat 2030519500 # Total ticks spent queuing +system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29459.52 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s @@ -273,119 +276,128 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.59 # Average write queue length when enqueuing -system.physmem.readRowHits 152685 # Number of row buffer hits during reads -system.physmem.writeRowHits 110914 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes -system.physmem.avgGap 15276710.34 # Average gap between requests -system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4923726743250 # Time in different power states +system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing +system.physmem.readRowHits 152396 # Number of row buffer hits during reads +system.physmem.writeRowHits 110551 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes +system.physmem.avgGap 15269535.89 # Average gap between requests +system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states system.physmem.memoryStateTime::REF 171297620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 34849149750 # Time in different power states +system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 4545861 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662568 # Transaction distribution -system.membus.trans_dist::ReadResp 662557 # Transaction distribution +system.membus.trans_dist::ReadReq 662528 # Transaction distribution +system.membus.trans_dist::ReadResp 662520 # Transaction distribution system.membus.trans_dist::WriteReq 13776 # Transaction distribution system.membus.trans_dist::WriteResp 13776 # Transaction distribution -system.membus.trans_dist::Writeback 103139 # Transaction distribution +system.membus.trans_dist::Writeback 103082 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1710 # Transaction distribution -system.membus.trans_dist::ReadExReq 133156 # Transaction distribution -system.membus.trans_dist::ReadExResp 133153 # Transaction distribution -system.membus.trans_dist::MessageReq 1644 # Transaction distribution -system.membus.trans_dist::MessageResp 1644 # Transaction distribution -system.membus.trans_dist::BadAddressError 11 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution +system.membus.trans_dist::ReadExReq 133413 # Transaction distribution +system.membus.trans_dist::ReadExResp 133410 # Transaction distribution +system.membus.trans_dist::MessageReq 1645 # Transaction distribution +system.membus.trans_dist::MessageResp 1645 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478059 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724235 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94797 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94797 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1822320 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18472576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20264541 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 23289549 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 23289549 # Total data (bytes) -system.membus.snoop_data_through_bus 30144 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 251288000 # Layer occupancy (ticks) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 943 # Total snoops (count) +system.membus.snoop_fanout::samples 338647 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 338647 # Request fanout histogram +system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583699000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1574361000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3158618040 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54966743 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47579 # number of replacements -system.iocache.tags.tagsinuse 0.103859 # Cycle average of tags in use +system.iocache.tags.replacements 47584 # number of replacements +system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992945696000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103859 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006491 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006491 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428706 # Number of tag accesses -system.iocache.tags.data_accesses 428706 # Number of data accesses +system.iocache.tags.tag_accesses 428751 # Number of tag accesses +system.iocache.tags.data_accesses 428751 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses -system.iocache.ReadReq_misses::total 914 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses -system.iocache.demand_misses::total 914 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses -system.iocache.overall_misses::total 914 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152667446 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152667446 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 152667446 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 152667446 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 152667446 # number of overall miss cycles -system.iocache.overall_miss_latency::total 152667446 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses +system.iocache.ReadReq_misses::total 919 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses +system.iocache.demand_misses::total 919 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses +system.iocache.overall_misses::total 919 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles +system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167032.216630 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167032.216630 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167032.216630 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked @@ -394,22 +406,22 @@ system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 914 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 914 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 914 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 914 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 105114946 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2850047667 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2850047667 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 105114946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 105114946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -418,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -439,13 +451,12 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638663 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225570 # Transaction distribution -system.iobus.trans_dist::ReadResp 225570 # Transaction distribution +system.iobus.trans_dist::ReadReq 225575 # Transaction distribution +system.iobus.trans_dist::ReadResp 225575 # Transaction distribution system.iobus.trans_dist::WriteReq 57606 # Transaction distribution system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1644 # Transaction distribution -system.iobus.trans_dist::MessageResp 1644 # Transaction distribution +system.iobus.trans_dist::MessageReq 1645 # Transaction distribution +system.iobus.trans_dist::MessageResp 1645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) @@ -465,37 +476,36 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276260 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276260 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3918185 # Layer occupancy (ticks) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -531,155 +541,155 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 422017356 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52370257 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 86877356 # Number of BP lookups -system.cpu.branchPred.condPredicted 86877356 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 902542 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80133511 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78163225 # Number of BTB hits +system.cpu.branchPred.lookups 86898883 # Number of BP lookups +system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.541246 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1555611 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178528 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449309558 # number of cpu cycles simulated +system.cpu.numCycles 449490093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27651859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428959611 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86877356 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79718836 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417653044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1892712 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 141479 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 49827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 205407 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 127451 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9182196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 444767 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5009 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446775840 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894723 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281257253 62.95% 62.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2318085 0.52% 63.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72134929 16.15% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1613434 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2149929 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2328393 0.52% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1530698 0.34% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1882713 0.42% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81560406 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446775840 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193357 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954708 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23023114 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264661195 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150717323 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7427852 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 946356 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838299668 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 946356 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25879231 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223164657 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13208529 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154609969 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 28967098 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834812666 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 479412 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12346095 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 191662 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13684658 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997151203 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1813191058 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114665342 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 185 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963963482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33187719 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468373 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 472487 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39006494 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336272 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10188880 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1345741 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1123547 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829275749 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1209290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824021244 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 242579 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23492118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36175819 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154222 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446775840 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.844373 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418251 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262561849 58.77% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13882888 3.11% 61.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10086827 2.26% 64.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6921999 1.55% 65.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74315249 16.63% 82.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4452451 1.00% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72780033 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1201096 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 573448 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446775840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1974933 71.79% 71.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 151 0.01% 71.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 606 0.02% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 614459 22.33% 94.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161026 5.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 292875 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795624977 96.55% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125321 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued @@ -706,98 +716,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18429310 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9398312 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824021244 # Type of FU issued -system.cpu.iq.rate 1.833972 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2751175 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003339 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2097811864 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 853989635 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819447653 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 217 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826479445 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1882501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued +system.cpu.iq.rate 1.833363 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3343168 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14800 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14469 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1764190 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224524 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72794 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 946356 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205489198 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9385897 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830485039 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 188872 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336272 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10188880 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 713065 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 415930 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8070911 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14469 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 518528 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 536731 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1055259 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822394413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18030482 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1492613 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27200783 # number of memory reference insts executed -system.cpu.iew.exec_branches 83281301 # Number of branches executed -system.cpu.iew.exec_stores 9170301 # Number of stores executed -system.cpu.iew.exec_rate 1.830351 # Inst execution rate -system.cpu.iew.wb_sent 821885746 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819447713 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640810294 # num instructions producing a value -system.cpu.iew.wb_consumers 1050192124 # num instructions consuming a value +system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed +system.cpu.iew.exec_branches 83289157 # Number of branches executed +system.cpu.iew.exec_stores 9174614 # Number of stores executed +system.cpu.iew.exec_rate 1.829760 # Inst execution rate +system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640910074 # num instructions producing a value +system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823793 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610184 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24342460 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1055068 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914367 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443118746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819035 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675250 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272366005 61.47% 61.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11194221 2.53% 63.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3590232 0.81% 64.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74521712 16.82% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2434404 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1603700 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 952599 0.21% 82.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71009883 16.03% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5445990 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443118746 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407773893 # Number of instructions committed -system.cpu.commit.committedOps 806048632 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407812863 # Number of instructions committed +system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22417793 # Number of memory references committed -system.cpu.commit.loads 13993103 # Number of loads committed -system.cpu.commit.membars 474875 # Number of memory barriers committed -system.cpu.commit.branches 82158924 # Number of branches committed +system.cpu.commit.refs 22429266 # Number of memory references committed +system.cpu.commit.loads 14000019 # Number of loads committed +system.cpu.commit.membars 474889 # Number of memory barriers committed +system.cpu.commit.branches 82168190 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734892496 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155452 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174150 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783190673 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144749 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121267 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734958550 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155635 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -824,214 +834,225 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13993103 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8424690 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806048632 # Class of committed instruction -system.cpu.commit.bw_lim_events 5445990 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction +system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1267985613 # The number of ROB reads -system.cpu.rob.rob_writes 1664458820 # The number of ROB writes -system.cpu.timesIdled 297027 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2533718 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9810435335 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407773893 # Number of Instructions Simulated -system.cpu.committedOps 806048632 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.101860 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.101860 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907557 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907557 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092201088 # number of integer regfile reads -system.cpu.int_regfile_writes 655889202 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.cc_regfile_reads 416095530 # number of cc regfile reads -system.cpu.cc_regfile_writes 321948927 # number of cc regfile writes -system.cpu.misc_regfile_reads 265553416 # number of misc regfile reads -system.cpu.misc_regfile_writes 402606 # number of misc regfile writes -system.cpu.toL2Bus.throughput 55008962 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3071462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3070914 # Transaction distribution +system.cpu.rob.rob_reads 1268217156 # The number of ROB reads +system.cpu.rob.rob_writes 1664635865 # The number of ROB writes +system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407812863 # Number of Instructions Simulated +system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads +system.cpu.int_regfile_writes 655932610 # number of integer regfile writes +system.cpu.fp_regfile_reads 56 # number of floating regfile reads +system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads +system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes +system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads +system.cpu.misc_regfile_writes 402863 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2242 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2242 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 11 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1996026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130754 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30653 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 164256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8321689 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63869504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207903453 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 978368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5729920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 278481245 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 278457117 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3731904 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4072507880 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61506 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1501244795 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3142652109 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 23061226 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 112150627 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 997506 # number of replacements -system.cpu.icache.tags.tagsinuse 509.982226 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8120756 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 998018 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.136883 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147598371250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.982226 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996059 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996059 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1003070 # number of replacements +system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10180257 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10180257 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8120756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8120756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8120756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8120756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8120756 # number of overall hits -system.cpu.icache.overall_hits::total 8120756 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061436 # number of overall misses -system.cpu.icache.overall_misses::total 1061436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14736249127 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14736249127 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14736249127 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14736249127 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14736249127 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14736249127 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9182192 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9182192 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9182192 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9182192 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9182192 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9182192 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115597 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115597 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115597 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115597 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115597 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115597 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13883.313857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13883.313857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13883.313857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13883.313857 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6673 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10188308 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10188308 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8117984 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8117984 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8117984 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8117984 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8117984 # number of overall hits +system.cpu.icache.overall_hits::total 8117984 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066696 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066696 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066696 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066696 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066696 # number of overall misses +system.cpu.icache.overall_misses::total 1066696 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14789893561 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14789893561 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14789893561 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14789893561 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14789893561 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14789893561 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9184680 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9184680 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9184680 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9184680 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9184680 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9184680 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116139 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116139 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116139 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116139 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116139 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116139 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.143922 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13865.143922 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13865.143922 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.143922 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13865.143922 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 266 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.852740 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.943609 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63371 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63371 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63371 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63371 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63371 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63371 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998065 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 998065 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 998065 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 998065 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 998065 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 998065 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095503951 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12095503951 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095503951 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12095503951 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095503951 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12095503951 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108696 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108696 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12118.954127 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12118.954127 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63068 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63068 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63068 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63068 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63068 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63068 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1003628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1003628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1003628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1003628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1003628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1003628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12143729999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12143729999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12143729999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12143729999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143729999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12143729999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109272 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109272 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109272 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 14491 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.005977 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26506 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 14506 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.827244 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104029760000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.005977 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375374 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.375374 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 99110 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 99110 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26504 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26504 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 16690 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.006176 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 23588 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 16704 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.412117 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5099387464000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006176 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375386 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375386 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 99931 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 99931 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 23592 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 23592 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26506 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26506 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26506 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26506 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15366 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 15366 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15366 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15366 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15366 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15366 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 173869741 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 173869741 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 173869741 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 173869741 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 173869741 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 173869741 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41870 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41870 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 23594 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 23594 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 23594 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 23594 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 17581 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 17581 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 17581 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 17581 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 17581 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 17581 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 194939990 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 194939990 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 194939990 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 194939990 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 194939990 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 194939990 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41173 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41173 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41872 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41872 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41872 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41872 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.366993 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.366993 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.366976 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.366976 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.366976 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.366976 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11315.224587 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11315.224587 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11315.224587 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11315.224587 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41175 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41175 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41175 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41175 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.427003 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.427003 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.426982 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.426982 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.426982 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.426982 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11088.105910 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11088.105910 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11088.105910 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11088.105910 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1040,85 +1061,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2963 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2963 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15366 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15366 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15366 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 15366 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15366 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 15366 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143113289 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143113289 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143113289 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143113289 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143113289 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143113289 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.366993 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.366993 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.366976 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.366976 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9313.633281 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3261 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3261 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 17581 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 17581 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 17581 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 17581 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 17581 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 17581 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159752038 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159752038 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159752038 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159752038 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159752038 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159752038 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.427003 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.427003 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.426982 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.426982 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9086.629771 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73624 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.198399 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 115934 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73640 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.574335 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 3233327929250 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.198399 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.949900 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.949900 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 76771 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.789364 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 114792 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 76787 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.494941 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 197445175000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.789364 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986835 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986835 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 456046 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 456046 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 115934 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 115934 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 115934 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 115934 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 115934 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 115934 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74726 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74726 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74726 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74726 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74726 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74726 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 911611211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 911611211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 911611211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 911611211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 911611211 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 911611211 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190660 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 190660 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190660 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 190660 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190660 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 190660 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391933 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391933 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391933 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391933 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391933 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391933 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12199.384565 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12199.384565 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12199.384565 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12199.384565 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 463158 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 463158 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114792 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 114792 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114792 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 114792 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114792 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 114792 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77858 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 77858 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 77858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77858 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 77858 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 943768714 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 943768714 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 943768714 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 943768714 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 943768714 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 943768714 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192650 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 192650 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192650 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 192650 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192650 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 192650 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404142 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404142 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404142 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404142 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404142 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404142 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12121.666547 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12121.666547 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12121.666547 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12121.666547 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1127,169 +1148,169 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22207 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22207 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74726 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74726 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74726 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 74726 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74726 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 74726 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762035957 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762035957 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762035957 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762035957 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762035957 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762035957 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391933 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391933 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391933 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10197.735152 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21599 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21599 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 77858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 77858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 787936434 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 787936434 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 787936434 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 787936434 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 787936434 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 787936434 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404142 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404142 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404142 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10120.173059 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1659582 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996805 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19130892 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1660094 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.523981 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1661725 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996415 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19139703 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1662237 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.514425 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996805 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996415 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88336593 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88336593 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10981431 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10981431 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8081664 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8081664 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 65027 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 65027 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19063095 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19063095 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19128122 # number of overall hits -system.cpu.dcache.overall_hits::total 19128122 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1801191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1801191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 333463 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 333463 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406345 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406345 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2134654 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2134654 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2540999 # number of overall misses -system.cpu.dcache.overall_misses::total 2540999 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26558757753 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26558757753 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12819840878 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12819840878 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39378598631 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39378598631 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39378598631 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39378598631 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12782622 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12782622 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8415127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8415127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 471372 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 471372 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21197749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21197749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21669121 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21669121 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140909 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140909 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039627 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862047 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.862047 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100702 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100702 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117264 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117264 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.109071 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.109071 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38444.567697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38444.567697 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18447.298078 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18447.298078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15497.290094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15497.290094 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 378253 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88377305 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88377305 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10986051 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10986051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8085611 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8085611 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 65242 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 65242 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19071662 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19071662 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19136904 # number of overall hits +system.cpu.dcache.overall_hits::total 19136904 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801162 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801162 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334073 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406623 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406623 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2135235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2135235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2541858 # number of overall misses +system.cpu.dcache.overall_misses::total 2541858 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26563616547 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26563616547 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12873735113 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12873735113 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39437351660 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39437351660 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39437351660 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39437351660 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12787213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12787213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8419684 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8419684 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 471865 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 471865 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21206897 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21206897 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21678762 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21678762 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140856 # miss rate for ReadReq accesses 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-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.422170 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353791 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks -system.cpu.dcache.writebacks::total 1560667 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 830878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 830878 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 875195 # number of demand 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0.075909 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075909 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854718 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854718 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059415 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059415 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076715 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076715 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 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mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13899.277966 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13899.277966 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18615.200728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18615.200728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.929954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.929954 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ 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percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50353.205869 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.791697 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3275.059967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11170.356359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000241 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170044 # Average 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for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency 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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 591176ec8..9d272e2fa 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.304497 # Number of seconds simulated -sim_ticks 5304496799500 # Number of ticks simulated -final_tick 5304496799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.300439 # Number of seconds simulated +sim_ticks 5300438650000 # Number of ticks simulated +final_tick 5300438650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120327 # Simulator instruction rate (inst/s) -host_op_rate 230715 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5973118168 # Simulator tick rate (ticks/s) -host_mem_usage 829584 # Number of bytes of host memory used -host_seconds 888.06 # Real time elapsed on the host -sim_insts 106858198 # Number of instructions simulated -sim_ops 204889266 # Number of ops (including micro ops) simulated +host_inst_rate 184616 # Simulator instruction rate (inst/s) +host_op_rate 353991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9163289290 # Simulator tick rate (ticks/s) +host_mem_usage 842832 # Number of bytes of host memory used +host_seconds 578.44 # Real time elapsed on the host +sim_insts 106789618 # Number of instructions simulated +sim_ops 204763566 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 168624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 87432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 563238768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 42054251 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 54624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 20152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 449830560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 51714243 # Number of bytes read from this memory -system.physmem.bytes_read::total 1107203814 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 563238768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 449830560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1013069328 # Number of instructions bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 541981136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38703389 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 101016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 45856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470377672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 54942760 # Number of bytes read from this memory +system.physmem.bytes_read::total 1106370453 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 541981136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470377672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1012358808 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 34106065 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 33949188 # Number of bytes written to this memory -system.physmem.bytes_written::total 71046373 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 21078 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 10929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 70404846 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 7007948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6828 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56228820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8722584 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142406363 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 31533942 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 36447976 # Number of bytes written to this memory +system.physmem.bytes_written::total 70973038 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15245 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 7685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 67747642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6493671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5732 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58797209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9219399 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142300024 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 5095102 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4745797 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9887637 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 31789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 16483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 106181376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7928038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 10298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 84801740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 9749133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 208729283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 106181376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 84801740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190983116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563881 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 4739534 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 5091384 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9877656 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 23009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 11599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 102252129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7301922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 19058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88743159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10365701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 208731867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 102252129 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88743159 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 190995288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 564313 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6429651 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6400077 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13393612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 31789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 16486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 106181376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 14357689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 10298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 84801740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16149210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 222122895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 5949308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6876407 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13390031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 23009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 11602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 102252129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13251230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 19058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88743159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 17242108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 222121898 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue @@ -253,56 +253,56 @@ system.physmem.readRowHitRate nan # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 5127363440000 # Time in different power states -system.physmem.memoryStateTime::REF 177128640000 # Time in different power states +system.physmem.memoryStateTime::IDLE 5123442263750 # Time in different power states +system.physmem.memoryStateTime::REF 176993180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 0 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10864368 # delay histogram for all message -system.ruby.delayHist::mean 0.442902 # delay histogram for all message -system.ruby.delayHist::stdev 1.830573 # delay histogram for all message -system.ruby.delayHist | 10263231 94.47% 94.47% | 1369 0.01% 94.48% | 599393 5.52% 100.00% | 125 0.00% 100.00% | 205 0.00% 100.00% | 8 0.00% 100.00% | 37 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10864368 # delay histogram for all message +system.ruby.delayHist::samples 10855969 # delay histogram for all message +system.ruby.delayHist::mean 0.443071 # delay histogram for all message +system.ruby.delayHist::stdev 1.830936 # delay histogram for all message +system.ruby.delayHist | 10255101 94.47% 94.47% | 1445 0.01% 94.48% | 599037 5.52% 100.00% | 126 0.00% 100.00% | 212 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10855969 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152246454 +system.ruby.outstanding_req_hist::samples 152130131 system.ruby.outstanding_req_hist::mean 1.000112 system.ruby.outstanding_req_hist::gmean 1.000078 -system.ruby.outstanding_req_hist::stdev 0.010602 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152229339 99.99% 99.99% | 17115 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152246454 +system.ruby.outstanding_req_hist::stdev 0.010599 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152113038 99.99% 99.99% | 17093 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152130131 system.ruby.latency_hist::bucket_size 32 system.ruby.latency_hist::max_bucket 319 -system.ruby.latency_hist::samples 152246453 -system.ruby.latency_hist::mean 3.380088 -system.ruby.latency_hist::gmean 3.106160 -system.ruby.latency_hist::stdev 3.773917 -system.ruby.latency_hist | 152072522 99.89% 99.89% | 120 0.00% 99.89% | 79139 0.05% 99.94% | 93729 0.06% 100.00% | 941 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152246453 +system.ruby.latency_hist::samples 152130130 +system.ruby.latency_hist::mean 3.380455 +system.ruby.latency_hist::gmean 3.106132 +system.ruby.latency_hist::stdev 3.781513 +system.ruby.latency_hist | 151955103 99.88% 99.88% | 126 0.00% 99.89% | 79786 0.05% 99.94% | 94134 0.06% 100.00% | 979 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 152130130 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 149587693 +system.ruby.hit_latency_hist::samples 149475024 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149587693 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 149587693 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149475024 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 149475024 system.ruby.miss_latency_hist::bucket_size 32 system.ruby.miss_latency_hist::max_bucket 319 -system.ruby.miss_latency_hist::samples 2658760 -system.ruby.miss_latency_hist::mean 24.764674 -system.ruby.miss_latency_hist::gmean 21.974787 -system.ruby.miss_latency_hist::stdev 18.711640 -system.ruby.miss_latency_hist | 2484829 93.46% 93.46% | 120 0.00% 93.46% | 79139 2.98% 96.44% | 93729 3.53% 99.96% | 941 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2658760 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11563536 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 571523 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12135059 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 70045998 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 358848 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 70404846 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2655106 +system.ruby.miss_latency_hist::mean 24.799008 +system.ruby.miss_latency_hist::gmean 21.990340 +system.ruby.miss_latency_hist::stdev 18.773320 +system.ruby.miss_latency_hist | 2480079 93.41% 93.41% | 126 0.00% 93.41% | 79786 3.01% 96.42% | 94134 3.55% 99.96% | 979 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 2655106 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 10730190 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 525947 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11256137 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 67423344 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 324298 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 67747642 # Number of cache demand accesses system.cpu_clk_domain.clock 500 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching @@ -313,30 +313,30 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 13 # cycles for which number of transistions == max transitions -system.ruby.network.routers0.percent_links_utilized 0.032337 -system.ruby.network.routers0.msg_count.Control::0 930371 -system.ruby.network.routers0.msg_count.Request_Control::2 42522 -system.ruby.network.routers0.msg_count.Response_Data::1 958517 -system.ruby.network.routers0.msg_count.Response_Control::1 545617 -system.ruby.network.routers0.msg_count.Response_Control::2 541977 -system.ruby.network.routers0.msg_count.Writeback_Data::0 316333 -system.ruby.network.routers0.msg_count.Writeback_Data::1 73 -system.ruby.network.routers0.msg_count.Writeback_Control::0 187850 -system.ruby.network.routers0.msg_bytes.Control::0 7442968 -system.ruby.network.routers0.msg_bytes.Request_Control::2 340176 -system.ruby.network.routers0.msg_bytes.Response_Data::1 69013224 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4364936 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4335816 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 22775976 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5256 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1502800 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12207979 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1269749 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13477728 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 55770180 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 458640 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 56228820 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions +system.ruby.network.routers0.percent_links_utilized 0.029767 +system.ruby.network.routers0.msg_count.Control::0 850245 +system.ruby.network.routers0.msg_count.Request_Control::2 42194 +system.ruby.network.routers0.msg_count.Response_Data::1 878350 +system.ruby.network.routers0.msg_count.Response_Control::1 503571 +system.ruby.network.routers0.msg_count.Response_Control::2 500402 +system.ruby.network.routers0.msg_count.Writeback_Data::0 294663 +system.ruby.network.routers0.msg_count.Writeback_Data::1 77 +system.ruby.network.routers0.msg_count.Writeback_Control::0 168221 +system.ruby.network.routers0.msg_bytes.Control::0 6801960 +system.ruby.network.routers0.msg_bytes.Request_Control::2 337552 +system.ruby.network.routers0.msg_bytes.Response_Data::1 63241200 +system.ruby.network.routers0.msg_bytes.Response_Control::1 4028568 +system.ruby.network.routers0.msg_bytes.Response_Control::2 4003216 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21215736 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5544 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1345768 +system.ruby.l1_cntrl1.L1Dcache.demand_hits 13015788 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313354 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14329142 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 58305702 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 491507 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58797209 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -346,111 +346,111 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.network.routers1.percent_links_utilized 0.054687 -system.ruby.network.routers1.msg_count.Control::0 1728389 -system.ruby.network.routers1.msg_count.Request_Control::2 38822 -system.ruby.network.routers1.msg_count.Response_Data::1 1752004 -system.ruby.network.routers1.msg_count.Response_Control::1 1215403 -system.ruby.network.routers1.msg_count.Response_Control::2 1215696 -system.ruby.network.routers1.msg_count.Writeback_Data::0 257519 -system.ruby.network.routers1.msg_count.Writeback_Data::1 203 -system.ruby.network.routers1.msg_count.Writeback_Control::0 921082 -system.ruby.network.routers1.msg_bytes.Control::0 13827112 -system.ruby.network.routers1.msg_bytes.Request_Control::2 310576 -system.ruby.network.routers1.msg_bytes.Response_Data::1 126144288 -system.ruby.network.routers1.msg_bytes.Response_Control::1 9723224 -system.ruby.network.routers1.msg_bytes.Response_Control::2 9725568 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 18541368 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 14616 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7368656 -system.ruby.l2_cntrl0.L2cache.demand_hits 2436175 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 222585 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2658760 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 13 # cycles for which number of transistions == max transitions +system.ruby.network.routers1.percent_links_utilized 0.057220 +system.ruby.network.routers1.msg_count.Control::0 1804861 +system.ruby.network.routers1.msg_count.Request_Control::2 38457 +system.ruby.network.routers1.msg_count.Response_Data::1 1828237 +system.ruby.network.routers1.msg_count.Response_Control::1 1255902 +system.ruby.network.routers1.msg_count.Response_Control::2 1256112 +system.ruby.network.routers1.msg_count.Writeback_Data::0 279082 +system.ruby.network.routers1.msg_count.Writeback_Data::1 227 +system.ruby.network.routers1.msg_count.Writeback_Control::0 940216 +system.ruby.network.routers1.msg_bytes.Control::0 14438888 +system.ruby.network.routers1.msg_bytes.Request_Control::2 307656 +system.ruby.network.routers1.msg_bytes.Response_Data::1 131633064 +system.ruby.network.routers1.msg_bytes.Response_Control::1 10047216 +system.ruby.network.routers1.msg_bytes.Response_Control::2 10048896 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20093904 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 16344 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7521728 +system.ruby.l2_cntrl0.L2cache.demand_hits 2431773 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 223333 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2655106 # Number of cache demand accesses system.ruby.l2_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions -system.ruby.network.routers2.percent_links_utilized 0.091278 -system.ruby.network.routers2.msg_count.Control::0 2832571 -system.ruby.network.routers2.msg_count.Request_Control::2 79701 -system.ruby.network.routers2.msg_count.Response_Data::1 2883607 -system.ruby.network.routers2.msg_count.Response_Control::1 1836255 -system.ruby.network.routers2.msg_count.Response_Control::2 1757673 -system.ruby.network.routers2.msg_count.Writeback_Data::0 573852 -system.ruby.network.routers2.msg_count.Writeback_Data::1 276 -system.ruby.network.routers2.msg_count.Writeback_Control::0 1108932 -system.ruby.network.routers2.msg_bytes.Control::0 22660568 -system.ruby.network.routers2.msg_bytes.Request_Control::2 637608 -system.ruby.network.routers2.msg_bytes.Response_Data::1 207619704 -system.ruby.network.routers2.msg_bytes.Response_Control::1 14690040 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14061384 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41317344 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 19872 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8871456 +system.ruby.network.routers2.percent_links_utilized 0.091305 +system.ruby.network.routers2.msg_count.Control::0 2830007 +system.ruby.network.routers2.msg_count.Request_Control::2 78985 +system.ruby.network.routers2.msg_count.Response_Data::1 2882064 +system.ruby.network.routers2.msg_count.Response_Control::1 1837383 +system.ruby.network.routers2.msg_count.Response_Control::2 1756514 +system.ruby.network.routers2.msg_count.Writeback_Data::0 573745 +system.ruby.network.routers2.msg_count.Writeback_Data::1 304 +system.ruby.network.routers2.msg_count.Writeback_Control::0 1108437 +system.ruby.network.routers2.msg_bytes.Control::0 22640056 +system.ruby.network.routers2.msg_bytes.Request_Control::2 631880 +system.ruby.network.routers2.msg_bytes.Response_Data::1 207508608 +system.ruby.network.routers2.msg_bytes.Response_Control::1 14699064 +system.ruby.network.routers2.msg_bytes.Response_Control::2 14052112 +system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41309640 +system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888 +system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867496 system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 316333 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 174271 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 142062 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 709010 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 938353 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 49 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 6542 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 944944 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.987181 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 926785 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 8256 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 98 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 9 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 3205 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.25% 3.25% | 9688 3.06% 6.31% | 9618 3.04% 9.35% | 9663 3.05% 12.41% | 10044 3.18% 15.58% | 9949 3.15% 18.73% | 9819 3.10% 21.83% | 9702 3.07% 24.90% | 9851 3.11% 28.01% | 9707 3.07% 31.08% | 9714 3.07% 34.15% | 9748 3.08% 37.23% | 9782 3.09% 40.33% | 9588 3.03% 43.36% | 9583 3.03% 46.39% | 8652 2.74% 49.12% | 10210 3.23% 52.35% | 9818 3.10% 55.45% | 9760 3.09% 58.54% | 9707 3.07% 61.61% | 10012 3.17% 64.77% | 9864 3.12% 67.89% | 9722 3.07% 70.96% | 9786 3.09% 74.06% | 10077 3.19% 77.24% | 9920 3.14% 80.38% | 10090 3.19% 83.57% | 10790 3.41% 86.98% | 10587 3.35% 90.33% | 10505 3.32% 93.65% | 10419 3.29% 96.94% | 9676 3.06% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 316333 # Number of accesses per bank -system.ruby.network.routers3.percent_links_utilized 0.006678 -system.ruby.network.routers3.msg_count.Control::0 173811 -system.ruby.network.routers3.msg_count.Response_Data::1 271445 -system.ruby.network.routers3.msg_count.Response_Control::1 122871 -system.ruby.network.routers3.msg_count.Writeback_Control::0 47547 +system.ruby.dir_cntrl0.memBuffer.memReq 317875 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 175364 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 142511 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 714751 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 942834 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 6611 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 949491 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.986995 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 931351 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 8237 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 87 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 3151 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.23% 3.23% | 9701 3.05% 6.29% | 9679 3.04% 9.33% | 9712 3.06% 12.39% | 10010 3.15% 15.54% | 9927 3.12% 18.66% | 9854 3.10% 21.76% | 9702 3.05% 24.81% | 9904 3.12% 27.93% | 9752 3.07% 30.99% | 9805 3.08% 34.08% | 9914 3.12% 37.20% | 9948 3.13% 40.33% | 9724 3.06% 43.39% | 9647 3.03% 46.42% | 8750 2.75% 49.17% | 10266 3.23% 52.40% | 9887 3.11% 55.51% | 9844 3.10% 58.61% | 9758 3.07% 61.68% | 10022 3.15% 64.83% | 9879 3.11% 67.94% | 9766 3.07% 71.01% | 9852 3.10% 74.11% | 10073 3.17% 77.28% | 9931 3.12% 80.41% | 10175 3.20% 83.61% | 10769 3.39% 86.99% | 10605 3.34% 90.33% | 10522 3.31% 93.64% | 10506 3.31% 96.95% | 9709 3.05% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 317875 # Number of accesses per bank +system.ruby.network.routers3.percent_links_utilized 0.006727 +system.ruby.network.routers3.msg_count.Control::0 174901 +system.ruby.network.routers3.msg_count.Response_Data::1 273155 +system.ruby.network.routers3.msg_count.Response_Control::1 125034 +system.ruby.network.routers3.msg_count.Writeback_Control::0 47550 system.ruby.network.routers3.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.msg_bytes.Control::0 1390488 -system.ruby.network.routers3.msg_bytes.Response_Data::1 19544040 -system.ruby.network.routers3.msg_bytes.Response_Control::1 982968 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380376 +system.ruby.network.routers3.msg_bytes.Control::0 1399208 +system.ruby.network.routers3.msg_bytes.Response_Data::1 19667160 +system.ruby.network.routers3.msg_bytes.Response_Control::1 1000272 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380400 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.routers4.percent_links_utilized 0.000239 -system.ruby.network.routers4.msg_count.Response_Data::1 811 -system.ruby.network.routers4.msg_count.Writeback_Control::0 47547 +system.ruby.network.routers4.percent_links_utilized 0.000240 +system.ruby.network.routers4.msg_count.Response_Data::1 814 +system.ruby.network.routers4.msg_count.Writeback_Control::0 47550 system.ruby.network.routers4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.msg_bytes.Response_Data::1 58392 -system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380376 +system.ruby.network.routers4.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380400 system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.routers5.percent_links_utilized 0.037045 -system.ruby.network.routers5.msg_count.Control::0 2832571 -system.ruby.network.routers5.msg_count.Request_Control::2 81344 -system.ruby.network.routers5.msg_count.Response_Data::1 2933192 -system.ruby.network.routers5.msg_count.Response_Control::1 1860073 -system.ruby.network.routers5.msg_count.Response_Control::2 1757673 -system.ruby.network.routers5.msg_count.Writeback_Data::0 573852 -system.ruby.network.routers5.msg_count.Writeback_Data::1 276 -system.ruby.network.routers5.msg_count.Writeback_Control::0 1156479 +system.ruby.network.routers5.percent_links_utilized 0.037053 +system.ruby.network.routers5.msg_count.Control::0 2830007 +system.ruby.network.routers5.msg_count.Request_Control::2 80651 +system.ruby.network.routers5.msg_count.Response_Data::1 2931310 +system.ruby.network.routers5.msg_count.Response_Control::1 1860945 +system.ruby.network.routers5.msg_count.Response_Control::2 1756514 +system.ruby.network.routers5.msg_count.Writeback_Data::0 573745 +system.ruby.network.routers5.msg_count.Writeback_Data::1 304 +system.ruby.network.routers5.msg_count.Writeback_Control::0 1155987 system.ruby.network.routers5.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers5.msg_bytes.Control::0 22660568 -system.ruby.network.routers5.msg_bytes.Request_Control::2 650752 -system.ruby.network.routers5.msg_bytes.Response_Data::1 211189824 -system.ruby.network.routers5.msg_bytes.Response_Control::1 14880584 -system.ruby.network.routers5.msg_bytes.Response_Control::2 14061384 -system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41317344 -system.ruby.network.routers5.msg_bytes.Writeback_Data::1 19872 -system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9251832 +system.ruby.network.routers5.msg_bytes.Control::0 22640056 +system.ruby.network.routers5.msg_bytes.Request_Control::2 645208 +system.ruby.network.routers5.msg_bytes.Response_Data::1 211054320 +system.ruby.network.routers5.msg_bytes.Response_Control::1 14887560 +system.ruby.network.routers5.msg_bytes.Response_Control::2 14052112 +system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41309640 +system.ruby.network.routers5.msg_bytes.Writeback_Data::1 21888 +system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9247896 system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.msg_count.Control 8497713 -system.ruby.network.msg_count.Request_Control 242389 -system.ruby.network.msg_count.Response_Data 8799576 -system.ruby.network.msg_count.Response_Control 10853238 -system.ruby.network.msg_count.Writeback_Data 1722384 -system.ruby.network.msg_count.Writeback_Control 3609645 -system.ruby.network.msg_byte.Control 67981704 -system.ruby.network.msg_byte.Request_Control 1939112 -system.ruby.network.msg_byte.Response_Data 633569472 -system.ruby.network.msg_byte.Response_Control 86825904 -system.ruby.network.msg_byte.Writeback_Data 124011648 -system.ruby.network.msg_byte.Writeback_Control 28877160 +system.ruby.network.msg_count.Control 8490021 +system.ruby.network.msg_count.Request_Control 240287 +system.ruby.network.msg_count.Response_Data 8793930 +system.ruby.network.msg_count.Response_Control 10852377 +system.ruby.network.msg_count.Writeback_Data 1722147 +system.ruby.network.msg_count.Writeback_Control 3608169 +system.ruby.network.msg_byte.Control 67920168 +system.ruby.network.msg_byte.Request_Control 1922296 +system.ruby.network.msg_byte.Response_Data 633162960 +system.ruby.network.msg_byte.Response_Control 86819016 +system.ruby.network.msg_byte.Writeback_Data 123994584 +system.ruby.network.msg_byte.Writeback_Control 28865352 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -463,737 +463,738 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 383266 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 858445 # Transaction distribution -system.iobus.trans_dist::ReadResp 858445 # Transaction distribution -system.iobus.trans_dist::WriteReq 37732 # Transaction distribution -system.iobus.trans_dist::WriteResp 37732 # Transaction distribution -system.iobus.trans_dist::MessageReq 1926 # Transaction distribution -system.iobus.trans_dist::MessageResp 1926 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 858433 # Transaction distribution +system.iobus.trans_dist::ReadResp 858433 # Transaction distribution +system.iobus.trans_dist::WriteReq 37701 # Transaction distribution +system.iobus.trans_dist::WriteResp 37701 # Transaction distribution +system.iobus.trans_dist::MessageReq 1920 # Transaction distribution +system.iobus.trans_dist::MessageResp 1920 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5246 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 984 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14276 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 246 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1701984 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5796 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 350 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12392 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1796206 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486422 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 488 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972089 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 520 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10501 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54249 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2033034 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2033034 # Total data (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 250 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5220 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 90780 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1796108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7138 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 492 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971279 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3692 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 700 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10437 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54937 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2032904 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 44000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10235000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10297000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1064500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1047500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 56500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1237000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1246000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 41501500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 41493500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 23566000 # Layer occupancy (ticks) +system.iobus.reqLayer12.occupancy 23740500 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 469636032 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 469005748 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 7824868 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8238216 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2417900 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2422964 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1790325500 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1790015500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 80269500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 80920500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10608993599 # number of cpu cycles simulated +system.cpu0.numCycles 10600877300 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 60256011 # Number of instructions committed -system.cpu0.committedOps 115558641 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108487069 # Number of integer alu accesses +system.cpu0.committedInsts 58227397 # Number of instructions committed +system.cpu0.committedOps 111982705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 104955708 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1055482 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10261722 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108487069 # number of integer instructions +system.cpu0.num_func_calls 986034 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9961508 # number of instructions that are conditional controls +system.cpu0.num_int_insts 104955708 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 204952011 # number of times the integer registers were read -system.cpu0.num_int_register_writes 91998767 # number of times the integer registers were written +system.cpu0.num_int_register_reads 197725542 # number of times the integer registers were read +system.cpu0.num_int_register_writes 89196196 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 62453256 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44908337 # number of times the CC registers were written -system.cpu0.num_mem_refs 12953157 # number of memory refs -system.cpu0.num_load_insts 7847096 # Number of load instructions -system.cpu0.num_store_insts 5106061 # Number of store instructions -system.cpu0.num_idle_cycles 10082177996.950100 # Number of idle cycles -system.cpu0.num_busy_cycles 526815602.049901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049657 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950343 # Percentage of idle cycles -system.cpu0.Branches 11678089 # Number of branches fetched -system.cpu0.op_class::No_OpClass 146086 0.13% 0.13% # Class of executed instruction -system.cpu0.op_class::IntAlu 102311234 88.54% 88.66% # Class of executed instruction -system.cpu0.op_class::IntMult 88422 0.08% 88.74% # Class of executed instruction -system.cpu0.op_class::IntDiv 60826 0.05% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::MemRead 7847096 6.79% 95.58% # Class of executed instruction -system.cpu0.op_class::MemWrite 5106061 4.42% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 60309477 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43597657 # number of times the CC registers were written +system.cpu0.num_mem_refs 12082037 # number of memory refs +system.cpu0.num_load_insts 7332388 # Number of load instructions +system.cpu0.num_store_insts 4749649 # Number of store instructions +system.cpu0.num_idle_cycles 10090456434.750097 # Number of idle cycles +system.cpu0.num_busy_cycles 510420865.249904 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048149 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951851 # Percentage of idle cycles +system.cpu0.Branches 11280989 # Number of branches fetched +system.cpu0.op_class::No_OpClass 134403 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 99628506 88.97% 89.09% # Class of executed instruction +system.cpu0.op_class::IntMult 83751 0.07% 89.16% # Class of executed instruction +system.cpu0.op_class::IntDiv 54749 0.05% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::MemRead 7332388 6.55% 95.76% # Class of executed instruction +system.cpu0.op_class::MemWrite 4749649 4.24% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 115559725 # Class of executed instruction +system.cpu0.op_class::total 111983446 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10606073781 # number of cpu cycles simulated +system.cpu1.numCycles 10598045368 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 46602187 # Number of instructions committed -system.cpu1.committedOps 89330625 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 85693039 # Number of integer alu accesses +system.cpu1.committedInsts 48562221 # Number of instructions committed +system.cpu1.committedOps 92780861 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 89101588 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1689151 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7994407 # number of instructions that are conditional controls -system.cpu1.num_int_insts 85693039 # number of integer instructions +system.cpu1.num_func_calls 1756989 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8282079 # number of instructions that are conditional controls +system.cpu1.num_int_insts 89101588 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 165895875 # number of times the integer registers were read -system.cpu1.num_int_register_writes 70974584 # number of times the integer registers were written +system.cpu1.num_int_register_reads 172887570 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73678147 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 49186847 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 31804657 # number of times the CC registers were written -system.cpu1.num_mem_refs 13506592 # number of memory refs -system.cpu1.num_load_insts 8734544 # Number of load instructions -system.cpu1.num_store_insts 4772048 # Number of store instructions -system.cpu1.num_idle_cycles 10285708583.748486 # Number of idle cycles -system.cpu1.num_busy_cycles 320365197.251515 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030206 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969794 # Percentage of idle cycles -system.cpu1.Branches 10261414 # Number of branches fetched -system.cpu1.op_class::No_OpClass 160911 0.18% 0.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 75499496 84.52% 84.70% # Class of executed instruction -system.cpu1.op_class::IntMult 96292 0.11% 84.80% # Class of executed instruction -system.cpu1.op_class::IntDiv 67765 0.08% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::MemRead 8734544 9.78% 94.66% # Class of executed instruction -system.cpu1.op_class::MemWrite 4772048 5.34% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 51235949 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 33065863 # number of times the CC registers were written +system.cpu1.num_mem_refs 14350246 # number of memory refs +system.cpu1.num_load_insts 9231791 # Number of load instructions +system.cpu1.num_store_insts 5118455 # Number of store instructions +system.cpu1.num_idle_cycles 10261750383.824707 # Number of idle cycles +system.cpu1.num_busy_cycles 336294984.175294 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031732 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968268 # Percentage of idle cycles +system.cpu1.Branches 10643732 # Number of branches fetched +system.cpu1.op_class::No_OpClass 171960 0.19% 0.19% # Class of executed instruction +system.cpu1.op_class::IntAlu 78085090 84.16% 84.35% # Class of executed instruction +system.cpu1.op_class::IntMult 100662 0.11% 84.45% # Class of executed instruction +system.cpu1.op_class::IntDiv 73682 0.08% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::MemRead 9231791 9.95% 94.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 5118455 5.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 89331056 # Class of executed instruction +system.cpu1.op_class::total 92781640 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.ruby.network.routers0.throttle0.link_utilization 0.041641 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42522 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 918158 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 529385 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 340176 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 66107376 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 4235080 -system.ruby.network.routers0.throttle1.link_utilization 0.023034 -system.ruby.network.routers0.throttle1.msg_count.Control::0 930371 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40359 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 16232 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 541977 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 316333 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 73 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 187850 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7442968 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2905848 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 129856 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4335816 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 22775976 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 5256 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1502800 -system.ruby.network.routers1.throttle0.link_utilization 0.078728 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 38822 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1718478 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 1199341 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 310576 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 123730416 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 9594728 -system.ruby.network.routers1.throttle1.link_utilization 0.030646 -system.ruby.network.routers1.throttle1.msg_count.Control::0 1728389 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 33526 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 16062 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1215696 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 257519 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 203 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 921082 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 13827112 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 2413872 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 128496 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 9725568 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 18541368 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 14616 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7368656 -system.ruby.network.routers2.throttle0.link_utilization 0.059393 -system.ruby.network.routers2.throttle0.msg_count.Control::0 2658760 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 198922 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 119247 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1757673 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 573852 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 276 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 1108932 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21270080 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 14322384 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 953976 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14061384 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 41317344 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 19872 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8871456 -system.ruby.network.routers2.throttle1.link_utilization 0.123163 -system.ruby.network.routers2.throttle1.msg_count.Control::0 173811 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 79701 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2684685 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1717008 -system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1390488 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 637608 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 193297320 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13736064 -system.ruby.network.routers3.throttle0.link_utilization 0.005207 -system.ruby.network.routers3.throttle0.msg_count.Control::0 173811 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 96823 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 12100 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47547 -system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1390488 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 6971256 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 96800 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380376 -system.ruby.network.routers3.throttle1.link_utilization 0.008149 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 174622 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 110771 +system.ruby.network.routers0.throttle0.link_utilization 0.038084 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42194 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+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 20093904 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 16344 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7521728 +system.ruby.network.routers2.throttle0.link_utilization 0.059452 +system.ruby.network.routers2.throttle0.msg_count.Control::0 2655106 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 199764 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 120598 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1756514 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 573745 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 304 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 1108437 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21240848 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 14383008 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 964784 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14052112 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 41309640 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 21888 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8867496 +system.ruby.network.routers2.throttle1.link_utilization 0.123157 +system.ruby.network.routers2.throttle1.msg_count.Control::0 174901 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 78985 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2682300 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1716785 +system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1399208 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 631880 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 193125600 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13734280 +system.ruby.network.routers3.throttle0.link_utilization 0.005246 +system.ruby.network.routers3.throttle0.msg_count.Control::0 174901 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 97440 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 12789 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47550 +system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1399208 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 7015680 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 102312 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers3.throttle1.link_utilization 0.008209 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 175715 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 112245 system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12572784 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 886168 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12651480 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 897960 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle0.link_utilization 0.000255 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 811 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 814 system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58392 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58608 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle1.link_utilization 0.000224 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47547 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380376 -system.ruby.network.routers5.throttle0.link_utilization 0.041641 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::2 42522 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 918158 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 529385 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::2 340176 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 66107376 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 4235080 -system.ruby.network.routers5.throttle1.link_utilization 0.078728 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 38822 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 1718478 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 1199341 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 310576 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 123730416 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 9594728 -system.ruby.network.routers5.throttle2.link_utilization 0.059393 -system.ruby.network.routers5.throttle2.msg_count.Control::0 2658760 -system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 198922 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 119247 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1757673 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 573852 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 276 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 1108932 -system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21270080 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 14322384 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 953976 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14061384 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 41317344 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 19872 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 8871456 -system.ruby.network.routers5.throttle3.link_utilization 0.005207 -system.ruby.network.routers5.throttle3.msg_count.Control::0 173811 -system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 96823 -system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12100 -system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0 47547 -system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1390488 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 6971256 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 96800 -system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380376 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47550 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers5.throttle0.link_utilization 0.038084 +system.ruby.network.routers5.throttle0.msg_count.Request_Control::2 42194 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 838308 +system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 487492 +system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::2 337552 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 60358176 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 3899936 +system.ruby.network.routers5.throttle1.link_utilization 0.082226 +system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 38457 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 1794984 +system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 1240066 +system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 307656 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 129238848 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 9920528 +system.ruby.network.routers5.throttle2.link_utilization 0.059452 +system.ruby.network.routers5.throttle2.msg_count.Control::0 2655106 +system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 199764 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 120598 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1756514 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 573745 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 304 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 1108437 +system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21240848 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 14383008 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 964784 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14052112 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 41309640 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 21888 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 8867496 +system.ruby.network.routers5.throttle3.link_utilization 0.005246 +system.ruby.network.routers5.throttle3.msg_count.Control::0 174901 +system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 97440 +system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12789 +system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0 47550 +system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1399208 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 7015680 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 102312 +system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380400 system.ruby.network.routers5.throttle4.link_utilization 0.000255 -system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 811 +system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 814 system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58392 +system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58608 system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6099217 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754439 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.340051 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5524579 90.58% 90.58% | 410 0.01% 90.59% | 573855 9.41% 99.99% | 123 0.00% 100.00% | 205 0.00% 100.00% | 8 0.00% 100.00% | 37 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6099217 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6093802 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.755007 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.340941 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5519285 90.57% 90.57% | 399 0.01% 90.58% | 573737 9.42% 99.99% | 123 0.00% 100.00% | 210 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6093802 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4683807 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.044910 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.595023 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4656927 99.43% 99.43% | 381 0.01% 99.43% | 370 0.01% 99.44% | 589 0.01% 99.45% | 25416 0.54% 100.00% | 122 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4683807 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4681516 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.044663 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.593096 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4654718 99.43% 99.43% | 447 0.01% 99.44% | 398 0.01% 99.45% | 648 0.01% 99.46% | 25177 0.54% 100.00% | 123 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4681516 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 81344 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000123 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.015680 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 81339 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 81344 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 80651 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000124 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.015747 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 80646 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 80651 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 16 system.ruby.LD.latency_hist::max_bucket 159 -system.ruby.LD.latency_hist::samples 14937313 -system.ruby.LD.latency_hist::mean 4.746801 -system.ruby.LD.latency_hist::gmean 3.589441 -system.ruby.LD.latency_hist::stdev 6.550511 -system.ruby.LD.latency_hist | 13550250 90.71% 90.71% | 1355967 9.08% 99.79% | 85 0.00% 99.79% | 0 0.00% 99.79% | 9654 0.06% 99.86% | 173 0.00% 99.86% | 20215 0.14% 99.99% | 758 0.01% 100.00% | 186 0.00% 100.00% | 25 0.00% 100.00% -system.ruby.LD.latency_hist::total 14937313 +system.ruby.LD.latency_hist::samples 14920569 +system.ruby.LD.latency_hist::mean 4.752955 +system.ruby.LD.latency_hist::gmean 3.589881 +system.ruby.LD.latency_hist::stdev 6.604009 +system.ruby.LD.latency_hist | 13535034 90.71% 90.71% | 1353292 9.07% 99.78% | 96 0.00% 99.78% | 0 0.00% 99.78% | 9982 0.07% 99.85% | 163 0.00% 99.85% | 20984 0.14% 99.99% | 796 0.01% 100.00% | 200 0.00% 100.00% | 22 0.00% 100.00% +system.ruby.LD.latency_hist::total 14920569 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13550250 +system.ruby.LD.hit_latency_hist::samples 13535034 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13550250 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13550250 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535034 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13535034 system.ruby.LD.miss_latency_hist::bucket_size 16 system.ruby.LD.miss_latency_hist::max_bucket 159 -system.ruby.LD.miss_latency_hist::samples 1387063 -system.ruby.LD.miss_latency_hist::mean 21.811342 -system.ruby.LD.miss_latency_hist::gmean 20.705599 -system.ruby.LD.miss_latency_hist::stdev 11.877845 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1355967 97.76% 97.76% | 85 0.01% 97.76% | 0 0.00% 97.76% | 9654 0.70% 98.46% | 173 0.01% 98.47% | 20215 1.46% 99.93% | 758 0.05% 99.98% | 186 0.01% 100.00% | 25 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1387063 +system.ruby.LD.miss_latency_hist::samples 1385535 +system.ruby.LD.miss_latency_hist::mean 21.877250 +system.ruby.LD.miss_latency_hist::gmean 20.732182 +system.ruby.LD.miss_latency_hist::stdev 12.099590 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1353292 97.67% 97.67% | 96 0.01% 97.68% | 0 0.00% 97.68% | 9982 0.72% 98.40% | 163 0.01% 98.41% | 20984 1.51% 99.93% | 796 0.06% 99.98% | 200 0.01% 100.00% | 22 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1385535 system.ruby.ST.latency_hist::bucket_size 32 system.ruby.ST.latency_hist::max_bucket 319 -system.ruby.ST.latency_hist::samples 9501279 -system.ruby.ST.latency_hist::mean 4.608129 -system.ruby.ST.latency_hist::gmean 3.286792 -system.ruby.ST.latency_hist::stdev 10.643686 -system.ruby.ST.latency_hist | 9375615 98.68% 98.68% | 20 0.00% 98.68% | 64184 0.68% 99.35% | 60844 0.64% 99.99% | 614 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9501279 +system.ruby.ST.latency_hist::samples 9491428 +system.ruby.ST.latency_hist::mean 4.608485 +system.ruby.ST.latency_hist::gmean 3.286938 +system.ruby.ST.latency_hist::stdev 10.640707 +system.ruby.ST.latency_hist | 9365714 98.68% 98.68% | 17 0.00% 98.68% | 64552 0.68% 99.36% | 60510 0.64% 99.99% | 633 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 9491428 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9151065 +system.ruby.ST.hit_latency_hist::samples 9141411 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9151065 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9151065 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9141411 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9141411 system.ruby.ST.miss_latency_hist::bucket_size 32 system.ruby.ST.miss_latency_hist::max_bucket 319 -system.ruby.ST.miss_latency_hist::samples 350214 -system.ruby.ST.miss_latency_hist::mean 46.628404 -system.ruby.ST.miss_latency_hist::gmean 35.714857 -system.ruby.ST.miss_latency_hist::stdev 35.216783 -system.ruby.ST.miss_latency_hist | 224550 64.12% 64.12% | 20 0.01% 64.12% | 64184 18.33% 82.45% | 60844 17.37% 99.82% | 614 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 350214 +system.ruby.ST.miss_latency_hist::samples 350017 +system.ruby.ST.miss_latency_hist::mean 46.617353 +system.ruby.ST.miss_latency_hist::gmean 35.715902 +system.ruby.ST.miss_latency_hist::stdev 35.185303 +system.ruby.ST.miss_latency_hist | 224303 64.08% 64.08% | 17 0.00% 64.09% | 64552 18.44% 82.53% | 60510 17.29% 99.82% | 633 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 350017 system.ruby.IFETCH.latency_hist::bucket_size 16 system.ruby.IFETCH.latency_hist::max_bucket 159 -system.ruby.IFETCH.latency_hist::samples 126633666 -system.ruby.IFETCH.latency_hist::mean 3.112947 -system.ruby.IFETCH.latency_hist::gmean 3.036567 -system.ruby.IFETCH.latency_hist::stdev 1.654702 -system.ruby.IFETCH.latency_hist | 125816178 99.35% 99.35% | 802052 0.63% 99.99% | 5 0.00% 99.99% | 0 0.00% 99.99% | 3918 0.00% 99.99% | 22 0.00% 99.99% | 11172 0.01% 100.00% | 208 0.00% 100.00% | 111 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126633666 +system.ruby.IFETCH.latency_hist::samples 126544851 +system.ruby.IFETCH.latency_hist::mean 3.112747 +system.ruby.IFETCH.latency_hist::gmean 3.036514 +system.ruby.IFETCH.latency_hist::stdev 1.652226 +system.ruby.IFETCH.latency_hist | 125729046 99.36% 99.36% | 800495 0.63% 99.99% | 4 0.00% 99.99% | 0 0.00% 99.99% | 3856 0.00% 99.99% | 28 0.00% 99.99% | 11079 0.01% 100.00% | 224 0.00% 100.00% | 119 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126544851 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 125816178 +system.ruby.IFETCH.hit_latency_hist::samples 125729046 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125816178 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 125816178 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125729046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 125729046 system.ruby.IFETCH.miss_latency_hist::bucket_size 16 system.ruby.IFETCH.miss_latency_hist::max_bucket 159 -system.ruby.IFETCH.miss_latency_hist::samples 817488 -system.ruby.IFETCH.miss_latency_hist::mean 20.496144 -system.ruby.IFETCH.miss_latency_hist::gmean 19.596306 -system.ruby.IFETCH.miss_latency_hist::stdev 10.954425 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 802052 98.11% 98.11% | 5 0.00% 98.11% | 0 0.00% 98.11% | 3918 0.48% 98.59% | 22 0.00% 98.59% | 11172 1.37% 99.96% | 208 0.03% 99.99% | 111 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 817488 +system.ruby.IFETCH.miss_latency_hist::samples 815805 +system.ruby.IFETCH.miss_latency_hist::mean 20.488864 +system.ruby.IFETCH.miss_latency_hist::gmean 19.593048 +system.ruby.IFETCH.miss_latency_hist::stdev 10.934190 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 800495 98.12% 98.12% | 4 0.00% 98.12% | 0 0.00% 98.12% | 3856 0.47% 98.60% | 28 0.00% 98.60% | 11079 1.36% 99.96% | 224 0.03% 99.99% | 119 0.01% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 815805 system.ruby.RMW_Read.latency_hist::bucket_size 16 system.ruby.RMW_Read.latency_hist::max_bucket 159 -system.ruby.RMW_Read.latency_hist::samples 494951 -system.ruby.RMW_Read.latency_hist::mean 5.895220 -system.ruby.RMW_Read.latency_hist::gmean 3.951159 -system.ruby.RMW_Read.latency_hist::stdev 8.211294 -system.ruby.RMW_Read.latency_hist | 429288 86.73% 86.73% | 64260 12.98% 99.72% | 3 0.00% 99.72% | 0 0.00% 99.72% | 989 0.20% 99.92% | 21 0.00% 99.92% | 364 0.07% 99.99% | 22 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 494951 +system.ruby.RMW_Read.latency_hist::samples 494298 +system.ruby.RMW_Read.latency_hist::mean 5.892257 +system.ruby.RMW_Read.latency_hist::gmean 3.949809 +system.ruby.RMW_Read.latency_hist::stdev 8.207792 +system.ruby.RMW_Read.latency_hist | 428816 86.75% 86.75% | 64079 12.96% 99.72% | 2 0.00% 99.72% | 0 0.00% 99.72% | 994 0.20% 99.92% | 20 0.00% 99.92% | 365 0.07% 100.00% | 18 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494298 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 429288 +system.ruby.RMW_Read.hit_latency_hist::samples 428816 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 429288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 429288 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428816 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428816 system.ruby.RMW_Read.miss_latency_hist::bucket_size 16 system.ruby.RMW_Read.miss_latency_hist::max_bucket 159 -system.ruby.RMW_Read.miss_latency_hist::samples 65663 -system.ruby.RMW_Read.miss_latency_hist::mean 24.823432 -system.ruby.RMW_Read.miss_latency_hist::gmean 23.914448 -system.ruby.RMW_Read.miss_latency_hist::stdev 9.754848 -system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64260 97.86% 97.86% | 3 0.00% 97.87% | 0 0.00% 97.87% | 989 1.51% 99.37% | 21 0.03% 99.41% | 364 0.55% 99.96% | 22 0.03% 99.99% | 3 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65663 +system.ruby.RMW_Read.miss_latency_hist::samples 65482 +system.ruby.RMW_Read.miss_latency_hist::mean 24.832519 +system.ruby.RMW_Read.miss_latency_hist::gmean 23.924296 +system.ruby.RMW_Read.miss_latency_hist::stdev 9.747837 +system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64079 97.86% 97.86% | 2 0.00% 97.86% | 0 0.00% 97.86% | 994 1.52% 99.38% | 20 0.03% 99.41% | 365 0.56% 99.97% | 18 0.03% 99.99% | 3 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65482 system.ruby.Locked_RMW_Read.latency_hist::bucket_size 16 system.ruby.Locked_RMW_Read.latency_hist::max_bucket 159 -system.ruby.Locked_RMW_Read.latency_hist::samples 339622 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.235927 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.761812 -system.ruby.Locked_RMW_Read.latency_hist::stdev 6.715360 -system.ruby.Locked_RMW_Read.latency_hist | 301290 88.71% 88.71% | 38000 11.19% 99.90% | 7 0.00% 99.90% | 0 0.00% 99.90% | 176 0.05% 99.96% | 2 0.00% 99.96% | 134 0.04% 100.00% | 12 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339622 +system.ruby.Locked_RMW_Read.latency_hist::samples 339492 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.237555 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.760998 +system.ruby.Locked_RMW_Read.latency_hist::stdev 6.749704 +system.ruby.Locked_RMW_Read.latency_hist | 301225 88.73% 88.73% | 37910 11.17% 99.89% | 7 0.00% 99.90% | 0 0.00% 99.90% | 190 0.06% 99.95% | 1 0.00% 99.95% | 148 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339492 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301290 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301225 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301290 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 301290 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301225 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 301225 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 16 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 159 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38332 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.810341 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.276488 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 7.169146 -system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 38000 99.13% 99.13% | 7 0.02% 99.15% | 0 0.00% 99.15% | 176 0.46% 99.61% | 2 0.01% 99.62% | 134 0.35% 99.97% | 12 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 38332 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38267 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.850838 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.292446 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 7.385228 +system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 37910 99.07% 99.07% | 7 0.02% 99.09% | 0 0.00% 99.09% | 190 0.50% 99.58% | 1 0.00% 99.58% | 148 0.39% 99.97% | 10 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 38267 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339622 +system.ruby.Locked_RMW_Write.latency_hist::samples 339492 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339622 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339492 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339492 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339622 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339492 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339622 -system.ruby.L1Cache_Controller.Load | 6583252 44.07% 44.07% | 8354061 55.93% 100.00% -system.ruby.L1Cache_Controller.Load::total 14937313 -system.ruby.L1Cache_Controller.Ifetch | 70404850 55.60% 55.60% | 56228821 44.40% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126633671 -system.ruby.L1Cache_Controller.Store | 5551807 52.01% 52.01% | 5123667 47.99% 100.00% -system.ruby.L1Cache_Controller.Store::total 10675474 -system.ruby.L1Cache_Controller.Inv | 16305 50.06% 50.06% | 16265 49.94% 100.00% -system.ruby.L1Cache_Controller.Inv::total 32570 -system.ruby.L1Cache_Controller.L1_Replacement | 902922 34.67% 34.67% | 1701187 65.33% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2604109 -system.ruby.L1Cache_Controller.Fwd_GETX | 12075 51.03% 51.03% | 11588 48.97% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 23663 -system.ruby.L1Cache_Controller.Fwd_GETS | 14138 56.31% 56.31% | 10969 43.69% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25107 +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339492 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339492 +system.ruby.L1Cache_Controller.Load | 6084011 40.78% 40.78% | 8836558 59.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 14920569 +system.ruby.L1Cache_Controller.Ifetch | 67747645 53.54% 53.54% | 58797210 46.46% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126544855 +system.ruby.L1Cache_Controller.Store | 5172126 48.50% 48.50% | 5492584 51.50% 100.00% +system.ruby.L1Cache_Controller.Store::total 10664710 +system.ruby.L1Cache_Controller.Inv | 16156 50.14% 50.14% | 16063 49.86% 100.00% +system.ruby.L1Cache_Controller.Inv::total 32219 +system.ruby.L1Cache_Controller.L1_Replacement | 823129 31.64% 31.64% | 1778072 68.36% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2601201 +system.ruby.L1Cache_Controller.Fwd_GETX | 12034 51.06% 51.06% | 11535 48.94% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23569 +system.ruby.L1Cache_Controller.Fwd_GETS | 14000 56.32% 56.32% | 10859 43.68% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 24859 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 776 45.81% 45.81% | 918 54.19% 100.00% -system.ruby.L1Cache_Controller.Data::total 1694 -system.ruby.L1Cache_Controller.Data_Exclusive | 274584 21.48% 21.48% | 1003769 78.52% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1278353 -system.ruby.L1Cache_Controller.DataS_fromL1 | 10969 43.68% 43.68% | 14142 56.32% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25111 -system.ruby.L1Cache_Controller.Data_all_Acks | 631829 47.45% 47.45% | 699649 52.55% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1331478 -system.ruby.L1Cache_Controller.Ack | 12213 55.20% 55.20% | 9911 44.80% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22124 -system.ruby.L1Cache_Controller.Ack_all | 12989 54.53% 54.53% | 10829 45.47% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 23818 -system.ruby.L1Cache_Controller.WB_Ack | 504183 29.96% 29.96% | 1178601 70.04% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1682784 -system.ruby.L1Cache_Controller.NP.Load | 306639 22.41% 22.41% | 1061542 77.59% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1368181 -system.ruby.L1Cache_Controller.NP.Ifetch | 358742 43.90% 43.90% | 458479 56.10% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 817221 -system.ruby.L1Cache_Controller.NP.Store | 238565 56.70% 56.70% | 182190 43.30% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 420755 -system.ruby.L1Cache_Controller.NP.Inv | 5465 60.99% 60.99% | 3496 39.01% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 8961 -system.ruby.L1Cache_Controller.I.Load | 8460 44.80% 44.80% | 10422 55.20% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18882 -system.ruby.L1Cache_Controller.I.Ifetch | 106 39.70% 39.70% | 161 60.30% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 267 -system.ruby.L1Cache_Controller.I.Store | 5646 49.83% 49.83% | 5684 50.17% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11330 -system.ruby.L1Cache_Controller.I.L1_Replacement | 8703 52.15% 52.15% | 7984 47.85% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 16687 -system.ruby.L1Cache_Controller.S.Load | 576531 53.67% 53.67% | 497753 46.33% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1074284 -system.ruby.L1Cache_Controller.S.Ifetch | 70045998 55.67% 55.67% | 55770180 44.33% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 125816178 -system.ruby.L1Cache_Controller.S.Store | 12213 55.20% 55.20% | 9911 44.80% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22124 -system.ruby.L1Cache_Controller.S.Inv | 10713 46.06% 46.06% | 12547 53.94% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23260 -system.ruby.L1Cache_Controller.S.L1_Replacement | 390036 43.12% 43.12% | 514602 56.88% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 904638 -system.ruby.L1Cache_Controller.E.Load | 1291134 33.50% 33.50% | 2563123 66.50% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3854257 -system.ruby.L1Cache_Controller.E.Store | 85252 51.14% 51.14% | 81438 48.86% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166690 -system.ruby.L1Cache_Controller.E.Inv | 54 73.97% 73.97% | 19 26.03% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 73 -system.ruby.L1Cache_Controller.E.L1_Replacement | 187850 16.94% 16.94% | 921082 83.06% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1108932 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 211 75.09% 75.09% | 70 24.91% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 281 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 1011 47.55% 47.55% | 1115 52.45% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2126 -system.ruby.L1Cache_Controller.M.Load | 4400488 51.04% 51.04% | 4221221 48.96% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8621709 -system.ruby.L1Cache_Controller.M.Store | 5210131 51.82% 51.82% | 4844444 48.18% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10054575 -system.ruby.L1Cache_Controller.M.Inv | 73 26.45% 26.45% | 203 73.55% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 276 -system.ruby.L1Cache_Controller.M.L1_Replacement | 316333 55.12% 55.12% | 257519 44.88% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 573852 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11864 50.74% 50.74% | 11518 49.26% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23382 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13127 57.12% 57.12% | 9854 42.88% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 22981 +system.ruby.L1Cache_Controller.Data | 734 41.99% 41.99% | 1014 58.01% 100.00% +system.ruby.L1Cache_Controller.Data::total 1748 +system.ruby.L1Cache_Controller.Data_Exclusive | 250298 19.59% 19.59% | 1027587 80.41% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1277885 +system.ruby.L1Cache_Controller.DataS_fromL1 | 10859 43.68% 43.68% | 14004 56.32% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 24863 +system.ruby.L1Cache_Controller.Data_all_Acks | 576417 43.38% 43.38% | 752379 56.62% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1328796 +system.ruby.L1Cache_Controller.Ack | 11937 54.72% 54.72% | 9877 45.28% 100.00% +system.ruby.L1Cache_Controller.Ack::total 21814 +system.ruby.L1Cache_Controller.Ack_all | 12671 53.78% 53.78% | 10891 46.22% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 23562 +system.ruby.L1Cache_Controller.WB_Ack | 462884 27.52% 27.52% | 1219298 72.48% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1682182 +system.ruby.L1Cache_Controller.NP.Load | 278313 20.36% 20.36% | 1088632 79.64% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1366945 +system.ruby.L1Cache_Controller.NP.Ifetch | 324200 39.75% 39.75% | 491378 60.25% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815578 +system.ruby.L1Cache_Controller.NP.Store | 221640 52.68% 52.68% | 199086 47.32% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 420726 +system.ruby.L1Cache_Controller.NP.Inv | 5298 59.26% 59.26% | 3642 40.74% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8940 +system.ruby.L1Cache_Controller.I.Load | 8389 45.13% 45.13% | 10201 54.87% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 18590 +system.ruby.L1Cache_Controller.I.Ifetch | 98 43.17% 43.17% | 129 56.83% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 227 +system.ruby.L1Cache_Controller.I.Store | 5668 50.49% 50.49% | 5558 49.51% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11226 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8737 52.26% 52.26% | 7980 47.74% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 16717 +system.ruby.L1Cache_Controller.S.Load | 550351 51.54% 51.54% | 517372 48.46% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1067723 +system.ruby.L1Cache_Controller.S.Ifetch | 67423344 53.63% 53.63% | 58305702 46.37% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 125729046 +system.ruby.L1Cache_Controller.S.Store | 11937 54.72% 54.72% | 9877 45.28% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 21814 +system.ruby.L1Cache_Controller.S.Inv | 10724 46.84% 46.84% | 12170 53.16% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 22894 +system.ruby.L1Cache_Controller.S.L1_Replacement | 351508 38.96% 38.96% | 550794 61.04% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 902302 +system.ruby.L1Cache_Controller.E.Load | 1120765 29.13% 29.13% | 2726807 70.87% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3847572 +system.ruby.L1Cache_Controller.E.Store | 80620 48.39% 48.39% | 85993 51.61% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166613 +system.ruby.L1Cache_Controller.E.Inv | 57 70.37% 70.37% | 24 29.63% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 81 +system.ruby.L1Cache_Controller.E.L1_Replacement | 168221 15.18% 15.18% | 940216 84.82% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1108437 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 207 58.81% 58.81% | 145 41.19% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 352 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 1001 46.45% 46.45% | 1154 53.55% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2155 +system.ruby.L1Cache_Controller.M.Load | 4126193 47.87% 47.87% | 4493546 52.13% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8619739 +system.ruby.L1Cache_Controller.M.Store | 4852261 48.31% 48.31% | 5192070 51.69% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10044331 +system.ruby.L1Cache_Controller.M.Inv | 77 25.33% 25.33% | 227 74.67% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 304 +system.ruby.L1Cache_Controller.M.L1_Replacement | 294663 51.36% 51.36% | 279082 48.64% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 573745 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11827 50.94% 50.94% | 11390 49.06% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23217 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 12999 57.25% 57.25% | 9705 42.75% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 22704 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 274584 21.48% 21.48% | 1003769 78.52% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1278353 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10969 43.68% 43.68% | 14142 56.32% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25111 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 388394 43.10% 43.10% | 512693 56.90% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 901087 -system.ruby.L1Cache_Controller.IM.Data | 776 45.81% 45.81% | 918 54.19% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1694 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 243435 56.56% 56.56% | 186956 43.44% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 430391 -system.ruby.L1Cache_Controller.SM.Ack | 12213 55.20% 55.20% | 9911 44.80% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22124 -system.ruby.L1Cache_Controller.SM.Ack_all | 12989 54.53% 54.53% | 10829 45.47% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 23818 -system.ruby.L1Cache_Controller.M_I.Ifetch | 4 80.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Ifetch::total 5 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 504183 29.96% 29.96% | 1178601 70.04% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1682784 -system.ruby.L2Cache_Controller.L1_GET_INSTR 817488 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1387273 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 432085 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22124 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1682784 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 94886 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 12189 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 173811 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 108923 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23261 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2126 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1643 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 6833 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25111 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1732562 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 3696 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15431 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 31011 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127369 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 802025 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 83603 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1729 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22124 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 253 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6503 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 4 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 250298 19.59% 19.59% | 1027587 80.41% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1277885 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10859 43.68% 43.68% | 14004 56.32% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 24863 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 349843 38.93% 38.93% | 548749 61.07% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898592 +system.ruby.L1Cache_Controller.IM.Data | 734 41.99% 41.99% | 1014 58.01% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1748 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 226574 52.67% 52.67% | 203630 47.33% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 430204 +system.ruby.L1Cache_Controller.SM.Ack | 11937 54.72% 54.72% | 9877 45.28% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 21814 +system.ruby.L1Cache_Controller.SM.Ack_all | 12671 53.78% 53.78% | 10891 46.22% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 23562 +system.ruby.L1Cache_Controller.M_I.Ifetch | 3 75.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Ifetch::total 4 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 462884 27.52% 27.52% | 1219298 72.48% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1682182 +system.ruby.L2Cache_Controller.L1_GET_INSTR 815805 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1385683 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 431953 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 21814 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1682182 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95349 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 12864 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 174901 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 110229 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23012 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2155 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1666 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 6687 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 24863 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1731651 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 4032 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15306 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 32147 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 127448 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 800467 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 82791 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1783 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 21814 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 268 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6335 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 28 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1247342 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 279324 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 94480 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 5571 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1763 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1245738 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 279152 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 94920 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6421 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1897 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25107 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 23663 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1682784 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 153 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 115 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 81 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 108923 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1763 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 187 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 47 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 81 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 89 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 26 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1386 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 6503 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 257 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 257 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 31011 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 15431 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127369 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 164 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23853 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 46 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708709 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22985 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2126 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25111 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest 811 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 24859 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23569 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1682182 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 161 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 108 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 116 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 110229 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1897 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 229 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 48 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 116 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 75 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 33 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1395 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 6335 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 271 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 271 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 32147 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 15306 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 127448 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 111 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23597 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 37 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708054 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22706 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2155 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 24861 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest 814 0.00% 0.00% system.ruby.DMA_Controller.WriteRequest 46736 0.00% 0.00% -system.ruby.DMA_Controller.Data 811 0.00% 0.00% +system.ruby.DMA_Controller.Data 814 0.00% 0.00% system.ruby.DMA_Controller.Ack 46736 0.00% 0.00% -system.ruby.DMA_Controller.READY.ReadRequest 811 0.00% 0.00% +system.ruby.DMA_Controller.READY.ReadRequest 814 0.00% 0.00% system.ruby.DMA_Controller.READY.WriteRequest 46736 0.00% 0.00% -system.ruby.DMA_Controller.BUSY_RD.Data 811 0.00% 0.00% +system.ruby.DMA_Controller.BUSY_RD.Data 814 0.00% 0.00% system.ruby.DMA_Controller.BUSY_WR.Ack 46736 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 173811 0.00% 0.00% -system.ruby.Directory_Controller.Data 96823 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 174271 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 142062 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 811 0.00% 0.00% +system.ruby.Directory_Controller.Fetch 174901 0.00% 0.00% +system.ruby.Directory_Controller.Data 97440 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 175364 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142511 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 12100 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 173811 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 460 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45239 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 460 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45239 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 94975 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 12789 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 174901 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 463 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45071 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 463 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45071 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95424 0.00% 0.00% system.ruby.Directory_Controller.M.DMA_READ 351 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1497 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 12100 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 173811 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 94975 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1665 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 12789 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 174901 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95424 0.00% 0.00% system.ruby.Directory_Controller.M_DRD.Data 351 0.00% 0.00% system.ruby.Directory_Controller.M_DRDI.Memory_Ack 351 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1497 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1497 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1665 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1665 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index f26bf1c54..cf390c4d1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137881 # Number of seconds simulated -sim_ticks 5137881357500 # Number of ticks simulated -final_tick 5137881357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133872 # Number of seconds simulated +sim_ticks 5133872107500 # Number of ticks simulated +final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 401147 # Simulator instruction rate (inst/s) -host_op_rate 797370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8430324111 # Simulator tick rate (ticks/s) -host_mem_usage 944704 # Number of bytes of host memory used -host_seconds 609.45 # Real time elapsed on the host -sim_insts 244480058 # Number of instructions simulated -sim_ops 485958826 # Number of ops (including micro ops) simulated +host_inst_rate 287663 # Simulator instruction rate (inst/s) +host_op_rate 571806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6046720341 # Simulator tick rate (ticks/s) +host_mem_usage 1024224 # Number of bytes of host memory used +host_seconds 849.03 # Real time elapsed on the host +sim_insts 244235751 # Number of instructions simulated +sim_ops 485482573 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5697984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1826880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 430976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2905472 # Number of bytes read from this memory -system.physmem.bytes_read::total 11438656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 430976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6187584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5572928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 164928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1639680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 412864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3220800 # Number of bytes read from this memory +system.physmem.bytes_read::total 11438848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 164928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 412864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 974528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6205312 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9177664 # Number of bytes written to this memory +system.physmem.bytes_written::total 9195392 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 89031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28545 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 45398 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96681 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 87077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 25620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 50325 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178732 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96958 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143401 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 77230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1109014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 355571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 83882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 565500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2226337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 77230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29173 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 83882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1204307 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 581968 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1786274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1204307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 587486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 77230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1109014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 355571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 83882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 565500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4012611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 83494 # Number of read requests accepted -system.physmem.writeReqs 76163 # Number of write requests accepted -system.physmem.readBursts 83494 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 76163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5331584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 4872768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5343616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4874432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 143678 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 77278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1085521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 319385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 80420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 627363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2228113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 77278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 80420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 189823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1208700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 582422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1791122 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1208700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 77278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1085521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 319385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 80420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 627363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4019235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 85451 # Number of read requests accepted +system.physmem.writeReqs 85019 # Number of write requests accepted +system.physmem.readBursts 85451 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 85019 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5457024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11840 # Total number of bytes read from write queue +system.physmem.bytesWritten 5440128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5468864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5441216 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 873 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4736 # Per bank write bursts -system.physmem.perBankRdBursts::1 4757 # Per bank write bursts -system.physmem.perBankRdBursts::2 5051 # Per bank write bursts -system.physmem.perBankRdBursts::3 5281 # Per bank write bursts -system.physmem.perBankRdBursts::4 5400 # Per bank write bursts -system.physmem.perBankRdBursts::5 4765 # Per bank write bursts -system.physmem.perBankRdBursts::6 4961 # Per bank write bursts -system.physmem.perBankRdBursts::7 5223 # Per bank write bursts -system.physmem.perBankRdBursts::8 5069 # Per bank write bursts -system.physmem.perBankRdBursts::9 5177 # Per bank write bursts -system.physmem.perBankRdBursts::10 4953 # Per bank write bursts -system.physmem.perBankRdBursts::11 4660 # Per bank write bursts -system.physmem.perBankRdBursts::12 5195 # Per bank write bursts -system.physmem.perBankRdBursts::13 6216 # Per bank write bursts -system.physmem.perBankRdBursts::14 6082 # Per bank write bursts -system.physmem.perBankRdBursts::15 5780 # Per bank write bursts -system.physmem.perBankWrBursts::0 4915 # Per bank write bursts -system.physmem.perBankWrBursts::1 4846 # Per bank write bursts -system.physmem.perBankWrBursts::2 4413 # Per bank write bursts -system.physmem.perBankWrBursts::3 4685 # Per bank write bursts -system.physmem.perBankWrBursts::4 5227 # Per bank write bursts -system.physmem.perBankWrBursts::5 4409 # Per bank write bursts -system.physmem.perBankWrBursts::6 4642 # Per bank write bursts -system.physmem.perBankWrBursts::7 4533 # Per bank write bursts -system.physmem.perBankWrBursts::8 4328 # Per bank write bursts -system.physmem.perBankWrBursts::9 4737 # Per bank write bursts -system.physmem.perBankWrBursts::10 4592 # Per bank write bursts -system.physmem.perBankWrBursts::11 4470 # Per bank write bursts -system.physmem.perBankWrBursts::12 4760 # Per bank write bursts -system.physmem.perBankWrBursts::13 5234 # Per bank write bursts -system.physmem.perBankWrBursts::14 5550 # Per bank write bursts -system.physmem.perBankWrBursts::15 4796 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 868 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5096 # Per bank write bursts +system.physmem.perBankRdBursts::1 5035 # Per bank write bursts +system.physmem.perBankRdBursts::2 5503 # Per bank write bursts +system.physmem.perBankRdBursts::3 5713 # Per bank write bursts +system.physmem.perBankRdBursts::4 5011 # Per bank write bursts +system.physmem.perBankRdBursts::5 4756 # Per bank write bursts +system.physmem.perBankRdBursts::6 4921 # Per bank write bursts +system.physmem.perBankRdBursts::7 5413 # Per bank write bursts +system.physmem.perBankRdBursts::8 5128 # Per bank write bursts +system.physmem.perBankRdBursts::9 4999 # Per bank write bursts +system.physmem.perBankRdBursts::10 4701 # Per bank write bursts +system.physmem.perBankRdBursts::11 5348 # Per bank write bursts +system.physmem.perBankRdBursts::12 5396 # Per bank write bursts +system.physmem.perBankRdBursts::13 6167 # Per bank write bursts +system.physmem.perBankRdBursts::14 6376 # Per bank write bursts +system.physmem.perBankRdBursts::15 5703 # Per bank write bursts +system.physmem.perBankWrBursts::0 5743 # Per bank write bursts +system.physmem.perBankWrBursts::1 5870 # Per bank write bursts +system.physmem.perBankWrBursts::2 5006 # Per bank write bursts +system.physmem.perBankWrBursts::3 5323 # Per bank write bursts +system.physmem.perBankWrBursts::4 4689 # Per bank write bursts +system.physmem.perBankWrBursts::5 4481 # Per bank write bursts +system.physmem.perBankWrBursts::6 5327 # Per bank write bursts +system.physmem.perBankWrBursts::7 5300 # Per bank write bursts +system.physmem.perBankWrBursts::8 5281 # Per bank write bursts +system.physmem.perBankWrBursts::9 5131 # Per bank write bursts +system.physmem.perBankWrBursts::10 5421 # Per bank write bursts +system.physmem.perBankWrBursts::11 5658 # Per bank write bursts +system.physmem.perBankWrBursts::12 5171 # Per bank write bursts +system.physmem.perBankWrBursts::13 5597 # Per bank write bursts +system.physmem.perBankWrBursts::14 5966 # Per bank write bursts +system.physmem.perBankWrBursts::15 5038 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5136881165000 # Total gap between requests +system.physmem.totGap 5132871981000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 83494 # Read request sizes (log2) +system.physmem.readPktSize::6 85451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 76163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 78715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.writePktSize::6 85019 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 78990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 26 # What read queue length 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incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -168,475 +164,469 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 60 # What write queue length does an incoming req see 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incoming req see -system.physmem.wrQLenPdf::18 3942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 65 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5996 # 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incoming req see +system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38507 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 264.993274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 160.426697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 294.053955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15907 41.31% 41.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9655 25.07% 66.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3981 10.34% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2127 5.52% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1469 3.81% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1046 2.72% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 664 1.72% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 555 1.44% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3103 8.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38507 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.615365 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121.265146 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 3842 99.71% 99.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 8 0.21% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3853 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3853 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.760446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.599143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.462049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 66 1.71% 1.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.21% 1.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 10 0.26% 2.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3269 84.84% 87.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 44 1.14% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.67% 88.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 135 3.50% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 114 2.96% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.08% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.36% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.21% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.34% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.05% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.03% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 96 2.49% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.03% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.13% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.34% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.13% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 39962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.686252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.690614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.316153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16345 40.90% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9834 24.61% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4112 10.29% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2230 5.58% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1552 3.88% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1069 2.68% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 711 1.78% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 597 1.49% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3512 8.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4105 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.770767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 117.592245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 4095 99.76% 99.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.17% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4105 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.706943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.214534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.616872 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 63 1.53% 1.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.17% 1.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.10% 1.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3359 81.83% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 49 1.19% 84.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.63% 85.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 173 4.21% 89.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 182 4.43% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.17% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.29% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.19% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.24% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 3.82% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.24% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.17% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.05% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.12% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.19% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3853 # Writes before turning the bus around for reads -system.physmem.totQLat 942120750 # Total ticks spent queuing -system.physmem.totMemAccLat 2504108250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 416530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11309.16 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 4105 # Writes before turning the bus around for reads +system.physmem.totQLat 1041221500 # Total ticks spent queuing +system.physmem.totMemAccLat 2639959000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 426330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12211.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30059.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30961.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.45 # Average write queue length when enqueuing -system.physmem.readRowHits 65566 # Number of row buffer hits during reads -system.physmem.writeRowHits 55368 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.70 # Row buffer hit rate for writes -system.physmem.avgGap 32174481.33 # Average gap between requests -system.physmem.pageHitRate 75.84 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4942580735250 # Time in different power states -system.physmem.memoryStateTime::REF 171564900000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 6.94 # Average write queue length when enqueuing +system.physmem.readRowHits 67077 # Number of row buffer hits during reads +system.physmem.writeRowHits 63228 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes +system.physmem.avgGap 30110118.97 # Average gap between requests +system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4938526642750 # Time in different power states +system.physmem.memoryStateTime::REF 171431260000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23734191750 # Time in different power states +system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 5877722 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 425622 # Transaction distribution -system.membus.trans_dist::ReadResp 425619 # Transaction distribution -system.membus.trans_dist::WriteReq 7303 # Transaction distribution -system.membus.trans_dist::WriteResp 7303 # Transaction distribution -system.membus.trans_dist::Writeback 54691 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 21472 # Transaction distribution -system.membus.trans_dist::UpgradeReq 873 # Transaction distribution -system.membus.trans_dist::UpgradeResp 873 # Transaction distribution -system.membus.trans_dist::ReadExReq 56661 # Transaction distribution -system.membus.trans_dist::ReadExResp 56661 # Transaction distribution -system.membus.trans_dist::MessageReq 1005 # Transaction distribution -system.membus.trans_dist::MessageResp 1005 # Transaction distribution -system.membus.trans_dist::BadAddressError 3 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 2010 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 2010 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 313168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 222539 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1034159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 44112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 44112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1080281 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 4020 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 4020 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160913 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996889 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8815488 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9973290 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1402560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 1402560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 11379870 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30180989 # Total data (bytes) -system.membus.snoop_data_through_bus 18048 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 165986000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 5056260 # Transaction distribution +system.membus.trans_dist::ReadResp 5056258 # Transaction distribution +system.membus.trans_dist::WriteReq 13754 # Transaction distribution +system.membus.trans_dist::WriteResp 13754 # Transaction distribution +system.membus.trans_dist::Writeback 96958 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1654 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1654 # Transaction distribution +system.membus.trans_dist::ReadExReq 129924 # Transaction distribution +system.membus.trans_dist::ReadExResp 129924 # Transaction distribution +system.membus.trans_dist::MessageReq 1664 # Transaction distribution +system.membus.trans_dist::MessageResp 1664 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7028524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3012958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456844 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10498330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10596613 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3520458 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6025913 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17615808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27162179 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3029056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30197891 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 297 # Total snoops (count) +system.membus.snoop_fanout::samples 324529 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 324529 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 324529 # Request fanout histogram +system.membus.reqLayer0.occupancy 165183000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315728000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315920500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2010000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1960000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 815495498 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 897247500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1005000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 980000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1662343876 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1679098885 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 28017243 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 35042997 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 105452 # number of replacements -system.l2c.tags.tagsinuse 64826.295665 # Cycle average of tags in use -system.l2c.tags.total_refs 3690842 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169644 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.756396 # Average number of references to valid blocks. +system.l2c.tags.replacements 105529 # number of replacements +system.l2c.tags.tagsinuse 64826.632454 # Cycle average of tags in use +system.l2c.tags.total_refs 3692969 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169653 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.767779 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50973.887089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1039.864675 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3857.355286 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 297.125354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1525.078899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.736641 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003210 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1792.530465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5328.582890 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777800 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50921.041202 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1022.158767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3887.538850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 285.540185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1563.161522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 13.370475 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1774.545144 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5359.142034 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.776993 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.015867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058859 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004534 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023271 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.027352 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.081308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64192 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 605 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7395 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52837 # Occupied blocks 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61919.579534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60870.660914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60432.285603 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57647.550784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65657.766238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61919.579534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60870.660914 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -783,98 +758,98 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47572 # number of replacements -system.iocache.tags.tagsinuse 0.093953 # Cycle average of tags in use +system.iocache.tags.replacements 47571 # number of replacements +system.iocache.tags.tagsinuse 0.081570 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000192642009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.093953 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005872 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005872 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000192639009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081570 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005098 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005098 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428643 # Number of tag accesses -system.iocache.tags.data_accesses 428643 # Number of data accesses +system.iocache.tags.tag_accesses 428634 # Number of tag accesses +system.iocache.tags.data_accesses 428634 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses -system.iocache.demand_misses::total 907 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses -system.iocache.overall_misses::total 907 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132008537 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132008537 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132008537 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132008537 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132008537 # number of overall miss cycles -system.iocache.overall_miss_latency::total 132008537 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses +system.iocache.ReadReq_misses::total 906 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 906 # number of demand (read+write) misses +system.iocache.demand_misses::total 906 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 906 # number of overall misses +system.iocache.overall_misses::total 906 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132202779 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 132202779 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 132202779 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 132202779 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 132202779 # number of overall miss cycles +system.iocache.overall_miss_latency::total 132202779 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 906 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 906 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 906 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 906 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145544.142227 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145544.142227 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145544.142227 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145919.182119 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145919.182119 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145919.182119 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 725 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 725 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21472 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 21472 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94282037 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1310743323 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1310743323 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94282037 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94282037 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.799338 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.459589 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.459589 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.799338 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.799338 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130044.188966 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61044.305281 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61044.305281 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 740 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 740 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28368 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 28368 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 740 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 740 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 740 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 740 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93698779 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1718205368 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1718205368 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 93698779 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 93698779 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.816777 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.607192 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.607192 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.816777 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.816777 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -884,109 +859,121 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 53202678 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1873297 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1872762 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 7303 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 7303 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 935388 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 816 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 816 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 157258 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 157258 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1081926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3727147 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 42874 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 142768 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4994715 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34620672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124341034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 151600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 524032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 159637338 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 270199237 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 3149808 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5231949371 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 7367165 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7366643 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13756 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13756 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1548978 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 28368 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1663 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1663 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296632 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296632 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740682 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14873990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 198555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16884529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55700736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213654403 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 264160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 728920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270348219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69633 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4254339 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011195 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105211 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4206713 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47626 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4254339 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5229007845 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 868500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 990000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2437443949 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2442789502 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4869271823 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4872933864 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23963155 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24776404 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 77561882 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 82986153 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1275815 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 151004 # Transaction distribution -system.iobus.trans_dist::ReadResp 151004 # Transaction distribution -system.iobus.trans_dist::WriteReq 27777 # Transaction distribution -system.iobus.trans_dist::WriteResp 27777 # Transaction distribution -system.iobus.trans_dist::MessageReq 1005 # Transaction distribution -system.iobus.trans_dist::MessageResp 1005 # Transaction distribution +system.iobus.trans_dist::ReadReq 3504325 # Transaction distribution +system.iobus.trans_dist::ReadResp 3504325 # Transaction distribution +system.iobus.trans_dist::WriteReq 57563 # Transaction distribution +system.iobus.trans_dist::WriteResp 39211 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 18352 # Transaction distribution +system.iobus.trans_dist::MessageReq 1664 # Transaction distribution +system.iobus.trans_dist::MessageResp 1664 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5602 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 594 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 142 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 16180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 6984892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27280 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 313168 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 44394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 44394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 2010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 2010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 359572 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143631 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1188 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 71 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 8090 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 160913 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1410472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1410472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 4020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 4020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1575405 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6554984 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2375600 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7028524 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7127104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3492446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 3520458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6554906 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2324808 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4638000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4502000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -994,11 +981,11 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 469000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 361000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12075000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11636000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -1008,431 +995,431 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 194319603 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 256433144 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306863000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306163000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 26743757 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33668003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1005000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 980000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1069887436 # number of cpu cycles simulated +system.cpu0.numCycles 1069607129 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70857782 # Number of instructions committed -system.cpu0.committedOps 144307609 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 132405898 # Number of integer alu accesses +system.cpu0.committedInsts 70538619 # Number of instructions committed +system.cpu0.committedOps 143755687 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 131850662 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 941314 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14024705 # number of instructions that are conditional controls -system.cpu0.num_int_insts 132405898 # number of integer instructions +system.cpu0.num_func_calls 928819 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13976393 # number of instructions that are conditional controls +system.cpu0.num_int_insts 131850662 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 243097330 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113712565 # number of times the integer registers were written +system.cpu0.num_int_register_reads 241989475 # number of times the integer registers were read +system.cpu0.num_int_register_writes 113259644 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82467233 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55021807 # number of times the CC registers were written -system.cpu0.num_mem_refs 13631596 # number of memory refs -system.cpu0.num_load_insts 10001277 # Number of load instructions -system.cpu0.num_store_insts 3630319 # Number of store instructions -system.cpu0.num_idle_cycles 1016044794.752217 # Number of idle cycles -system.cpu0.num_busy_cycles 53842641.247783 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050326 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949674 # Percentage of idle cycles -system.cpu0.Branches 15304700 # Number of branches fetched -system.cpu0.op_class::No_OpClass 96295 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 130472194 90.41% 90.48% # Class of executed instruction -system.cpu0.op_class::IntMult 58212 0.04% 90.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 49897 0.03% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::MemRead 10001277 6.93% 97.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 3630319 2.52% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82136389 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 54810829 # number of times the CC registers were written +system.cpu0.num_mem_refs 13501731 # number of memory refs +system.cpu0.num_load_insts 9912408 # Number of load instructions +system.cpu0.num_store_insts 3589323 # Number of store instructions +system.cpu0.num_idle_cycles 1016224343.330366 # Number of idle cycles +system.cpu0.num_busy_cycles 53382785.669634 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049909 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950091 # Percentage of idle cycles +system.cpu0.Branches 15238819 # Number of branches fetched +system.cpu0.op_class::No_OpClass 94852 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 130054750 90.47% 90.53% # Class of executed instruction +system.cpu0.op_class::IntMult 56051 0.04% 90.57% # Class of executed instruction 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Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::MemRead 9912408 6.90% 97.50% # Class of executed instruction +system.cpu0.op_class::MemWrite 3589323 2.50% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 144308194 # Class of executed instruction +system.cpu0.op_class::total 143756229 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 870298 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.224543 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 128999874 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 870810 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 148.137796 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147420132000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.471919 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.049993 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.702632 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.245062 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267676 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.483794 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996532 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 869835 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.810026 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128546541 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 870347 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 147.695736 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147420125000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.953257 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.567270 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.289498 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.246002 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.268686 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.482987 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997676 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 130765185 # Number of tag accesses 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accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004064 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117261 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006886 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004151 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115315 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006907 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003811 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004064 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117261 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006886 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13953.064780 # average ReadReq miss latency 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ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15926.913883 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11160.492946 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36804.709998 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31623.977265 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19019.649216 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20044.440194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18120.028891 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12755.083151 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 15171.663710 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15005.967453 # average overall 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average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34813.912363 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32561.311943 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18841.990618 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19327.209704 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 19249.105917 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13313.284047 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 14602.266020 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15987.586490 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10656.437768 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 138914 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 26365 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 26241 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.887085 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5.293777 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1547750 # number of writebacks -system.cpu0.dcache.writebacks::total 1547750 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 72 # 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+system.cpu0.dcache.WriteReq_mshr_misses::total 156500 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 75065 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 179480 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 254545 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 230324 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 505999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 736323 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 305389 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 685479 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 990868 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2019901500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5830950588 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7850852088 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1912820354 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3255992760 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5168813114 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 995266500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770573261 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3765839761 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3932721854 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9086943348 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13019665202 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4927988354 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11857516609 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16785504963 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30674705000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246369000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63921074000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534053500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 811227000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345280500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31208758500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34057596000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65266354500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061209 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084010 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045295 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033572 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031937 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018640 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.862400 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.842514 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.545962 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050505 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.063972 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034738 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065711 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084391 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045740 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1443,376 +1430,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606024060 # number of cpu cycles simulated +system.cpu1.numCycles 2604021576 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35944624 # Number of instructions committed -system.cpu1.committedOps 69816061 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64937038 # Number of integer alu accesses +system.cpu1.committedInsts 35901808 # Number of instructions committed +system.cpu1.committedOps 69778761 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64893692 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 484528 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6597164 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64937038 # number of integer instructions +system.cpu1.num_func_calls 487874 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6598396 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64893692 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120144832 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55989327 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119938204 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55974127 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36928761 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27400948 # number of times the CC registers were written -system.cpu1.num_mem_refs 4904439 # number of memory refs -system.cpu1.num_load_insts 3100845 # Number of load instructions -system.cpu1.num_store_insts 1803594 # Number of store instructions -system.cpu1.num_idle_cycles 2475176569.081452 # Number of idle cycles -system.cpu1.num_busy_cycles 130847490.918548 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050210 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949790 # Percentage of idle cycles -system.cpu1.Branches 7263647 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35052 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64819822 92.84% 92.89% # Class of executed instruction -system.cpu1.op_class::IntMult 29822 0.04% 92.94% # Class of executed instruction -system.cpu1.op_class::IntDiv 27277 0.04% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::MemRead 3100845 4.44% 97.42% # Class of executed instruction -system.cpu1.op_class::MemWrite 1803594 2.58% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36929560 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27415142 # number of times the CC registers were written +system.cpu1.num_mem_refs 4838216 # number of memory refs +system.cpu1.num_load_insts 3070311 # Number of load instructions +system.cpu1.num_store_insts 1767905 # Number of store instructions +system.cpu1.num_idle_cycles 2474835372.874957 # Number of idle cycles +system.cpu1.num_busy_cycles 129186203.125043 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049610 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950390 # Percentage of idle cycles +system.cpu1.Branches 7267731 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34873 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64849393 92.94% 92.99% # Class of executed instruction +system.cpu1.op_class::IntMult 30804 0.04% 93.03% # Class of executed instruction +system.cpu1.op_class::IntDiv 25762 0.04% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::MemRead 3070311 4.40% 97.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 1767905 2.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69816412 # Class of executed instruction +system.cpu1.op_class::total 69779048 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29512659 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29512659 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 322904 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26886254 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26249300 # Number of BTB hits +system.cpu2.branchPred.lookups 29537500 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29537500 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 323734 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26929505 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26224950 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.630931 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 591365 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 64668 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155365551 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.383706 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 595117 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63666 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155672620 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10587640 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145508462 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29512659 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26840665 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 143230873 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 673912 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 95091 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 7931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8903 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 52631 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 2801 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3432374 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 167414 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3341 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154322486 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.857387 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.033367 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10607285 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145694636 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29537500 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26820067 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143529975 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 676631 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 97153 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 5039 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8049 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 56841 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 4424 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3472431 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 167012 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3661 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154646852 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.855079 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.032629 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98410042 63.77% 63.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 833989 0.54% 64.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 24035117 15.57% 79.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 597750 0.39% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 798628 0.52% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 859445 0.56% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 568143 0.37% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 716402 0.46% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27502970 17.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98720699 63.84% 63.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 840447 0.54% 64.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23990695 15.51% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 599923 0.39% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 812589 0.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 861055 0.56% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 574182 0.37% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 718315 0.46% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27528947 17.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154322486 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189956 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.936556 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10280285 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95091051 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 22517334 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5911995 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 337607 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283677190 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 337607 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12887048 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76613528 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4915145 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 25582017 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13802994 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282449598 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 208301 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 6363616 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 49211 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4861555 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337331977 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 615247721 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 378014471 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325050122 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12281853 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 158846 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160455 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 28628976 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6469632 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3638513 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 420201 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 343826 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280493266 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 428842 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278404006 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 102314 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8748691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13528194 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64074 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154322486 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.804040 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.401684 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154646852 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189741 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.935904 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10277789 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95381782 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22559618 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5904125 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 338966 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283871353 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 338966 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12885148 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76664692 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4829048 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25619792 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14124701 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 282624473 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 211024 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 6375709 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 73879 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 5159969 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 337473501 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 616062521 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 378507156 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325128635 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12344864 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 162095 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 163797 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 28599466 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6606628 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3716011 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 425441 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 346966 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 280674873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 430305 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278581977 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 102725 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8814114 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13599788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 65362 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154646852 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.801407 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400759 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 91177599 59.08% 59.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5361636 3.47% 62.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3887403 2.52% 65.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4108764 2.66% 67.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 21799190 14.13% 81.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 3056480 1.98% 83.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24267786 15.73% 99.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 453628 0.29% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 210000 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91425932 59.12% 59.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5392264 3.49% 62.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3912324 2.53% 65.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4126244 2.67% 67.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 21795400 14.09% 81.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 3071037 1.99% 83.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24235245 15.67% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 469170 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 219236 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154322486 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154646852 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2321368 89.34% 89.34% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 246 0.01% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 217075 8.35% 97.70% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 59662 2.30% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2310389 89.01% 89.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 246 0.01% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 223101 8.59% 97.61% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 62004 2.39% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 72561 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 268083598 96.29% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 57882 0.02% 96.34% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 47134 0.02% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6794594 2.44% 98.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3348237 1.20% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 76436 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 268041478 96.22% 96.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 58746 0.02% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49744 0.02% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6933130 2.49% 98.77% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3422443 1.23% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278404006 # Type of FU issued -system.cpu2.iq.rate 1.791929 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2598351 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.009333 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713831099 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 289675272 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276815941 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 63 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 278581977 # Type of FU issued +system.cpu2.iq.rate 1.789537 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2595740 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.009318 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 714509188 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289923619 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 276984093 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 82 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280929766 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 30 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 708692 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 281101244 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 37 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 733638 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1202973 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6613 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5162 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 660777 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1227908 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6601 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5025 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 667461 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 754641 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21520 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 754863 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 24022 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 337607 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 71713264 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1590839 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 280922108 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 41019 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6469632 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3638513 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 247100 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 199459 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1088059 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5162 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 186556 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 187873 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374429 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 277824668 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6659327 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 530499 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 338966 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71689555 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1628683 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 281105178 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 39439 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6606628 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3716011 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 250069 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 194031 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1131651 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5025 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 186633 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 188127 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374760 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 278001109 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6795315 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 530943 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9922055 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28210243 # Number of branches executed -system.cpu2.iew.exec_stores 3262728 # Number of stores executed -system.cpu2.iew.exec_rate 1.788200 # Inst execution rate -system.cpu2.iew.wb_sent 277637651 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276815959 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215923076 # num instructions producing a value -system.cpu2.iew.wb_consumers 354065892 # num instructions consuming a value +system.cpu2.iew.exec_refs 10133053 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28226522 # Number of branches executed +system.cpu2.iew.exec_stores 3337738 # Number of stores executed +system.cpu2.iew.exec_rate 1.785806 # Inst execution rate +system.cpu2.iew.wb_sent 277806882 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 276984111 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215977189 # num instructions producing a value +system.cpu2.iew.wb_consumers 354208085 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.781707 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609839 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.779273 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609747 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9085200 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 364768 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325355 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152966387 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.777091 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.654040 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9156375 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364943 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 326343 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153280377 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.774187 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.653000 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 95002675 62.11% 62.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4175839 2.73% 64.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1266091 0.83% 65.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24954040 16.31% 81.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 981729 0.64% 82.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 650164 0.43% 83.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 435006 0.28% 83.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23529501 15.38% 98.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1971342 1.29% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95267512 62.15% 62.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4211429 2.75% 64.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1288351 0.84% 65.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24928908 16.26% 82.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 992667 0.65% 82.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 656859 0.43% 83.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 436979 0.29% 83.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23484943 15.32% 98.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2012729 1.31% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152966387 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137677652 # Number of instructions committed -system.cpu2.commit.committedOps 271835156 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153280377 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137795324 # Number of instructions committed +system.cpu2.commit.committedOps 271948125 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8244394 # Number of memory references committed -system.cpu2.commit.loads 5266658 # Number of loads committed -system.cpu2.commit.membars 166791 # Number of memory barriers committed -system.cpu2.commit.branches 27802655 # Number of branches committed +system.cpu2.commit.refs 8427269 # Number of memory references committed +system.cpu2.commit.loads 5378719 # Number of loads committed +system.cpu2.commit.membars 165391 # Number of memory barriers committed +system.cpu2.commit.branches 27813078 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248203210 # Number of committed integer instructions. -system.cpu2.commit.function_calls 440588 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 43200 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 263446464 96.91% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 55564 0.02% 96.95% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 45534 0.02% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5266658 1.94% 98.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2977736 1.10% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 248363308 # Number of committed integer instructions. +system.cpu2.commit.function_calls 444774 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44974 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 263371453 96.85% 96.86% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56553 0.02% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 47876 0.02% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5378719 1.98% 98.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3048550 1.12% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 271835156 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1971342 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 271948125 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2012729 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 431889681 # The number of ROB reads -system.cpu2.rob.rob_writes 563202973 # The number of ROB writes -system.cpu2.timesIdled 114782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1043065 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4908353341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137677652 # Number of Instructions Simulated -system.cpu2.committedOps 271835156 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.128473 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.128473 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.886153 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.886153 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 369541594 # number of integer regfile reads -system.cpu2.int_regfile_writes 221773447 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72930 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 140769340 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108468562 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90221682 # number of misc regfile reads -system.cpu2.misc_regfile_writes 135530 # number of misc regfile writes +system.cpu2.rob.rob_reads 432344700 # The number of ROB reads +system.cpu2.rob.rob_writes 563581737 # The number of ROB writes +system.cpu2.timesIdled 114304 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1025768 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4904031691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137795324 # Number of Instructions Simulated +system.cpu2.committedOps 271948125 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.129738 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.129738 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.885161 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.885161 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370036745 # number of integer regfile reads +system.cpu2.int_regfile_writes 221903617 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72874 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140867740 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108480868 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90412070 # number of misc regfile reads +system.cpu2.misc_regfile_writes 138782 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |