diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1770 |
1 files changed, 885 insertions, 885 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f421b5375..978d3ed52 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,327 +1,84 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.163939 # Number of seconds simulated -sim_ticks 5163939423500 # Number of ticks simulated -final_tick 5163939423500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125295 # Number of seconds simulated +sim_ticks 5125295451000 # Number of ticks simulated +final_tick 5125295451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202828 # Simulator instruction rate (inst/s) -host_op_rate 400952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2568035232 # Simulator tick rate (ticks/s) -host_mem_usage 368532 # Number of bytes of host memory used -host_seconds 2010.85 # Real time elapsed on the host -sim_insts 407858031 # Number of instructions simulated -sim_ops 806254969 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2460224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1069888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10576384 # Number of bytes read from this memory -system.physmem.bytes_read::total 14109824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1069888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1069888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9320448 # Number of bytes written to this memory -system.physmem.bytes_written::total 9320448 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38441 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165256 # Number of read requests responded to by this memory -system.physmem.num_reads::total 220466 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145632 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145632 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 207184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2048123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2732376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1804910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1804910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1804910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 109190 # number of replacements -system.cpu.l2cache.tagsinuse 64839.015299 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3984882 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.977685 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989365 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2515284 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1610495 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1610495 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 337 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 158131 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1505908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2673415 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 103321 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 8437 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1055749 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1505908 # number of overall hits -system.cpu.l2cache.overall_hits::total 2673415 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35983 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3384 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3384 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130218 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130218 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16718 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166201 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 182971 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16718 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166201 # number of overall misses -system.cpu.l2cache.overall_misses::total 182971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2414500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 887508500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1921141998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2811377498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 38315000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 38315000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6787419499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6787419499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2414500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 887508500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8708561497 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9598796997 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2414500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 887508500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8708561497 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9598796997 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103367 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8443 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1072467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1383760 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2568037 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1610495 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1610495 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3721 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3721 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103367 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8443 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1072467 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1672109 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2856386 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103367 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8443 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1072467 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1672109 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2856386 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000711 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015588 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026004 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.020542 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.909433 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.909433 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.451599 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.451599 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000711 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015588 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.099396 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.064057 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000711 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015588 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.099396 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.064057 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.130435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52083.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53087.002034 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53390.267571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53293.224992 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11322.399527 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11322.399527 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52123.512103 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52123.512103 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52460.756060 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52460.756060 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98965 # number of writebacks -system.cpu.l2cache.writebacks::total 98965 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16717 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35981 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52750 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3384 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3384 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130218 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130218 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16717 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 166199 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 182968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16717 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 166199 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 182968 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1856000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683651500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1481312999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2167060499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 135806000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 135806000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5218894001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5218894001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1856000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683651500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6700207000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7385954500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1856000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683651500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6700207000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7385954500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47573 # number of replacements -system.iocache.tagsinuse 0.184801 # Cycle average of tags in use +host_inst_rate 133696 # Simulator instruction rate (inst/s) +host_op_rate 264282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1679641336 # Simulator tick rate (ticks/s) +host_mem_usage 368820 # Number of bytes of host memory used +host_seconds 3051.42 # Real time elapsed on the host +sim_insts 407963822 # Number of instructions simulated +sim_ops 806434654 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2463488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1076608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10836416 # Number of bytes read from this memory +system.physmem.bytes_read::total 14379776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1076608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1076608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9553280 # Number of bytes written to this memory +system.physmem.bytes_written::total 9553280 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16822 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169319 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224684 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149270 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 480653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2114301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2805648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1863947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1863947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1863947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 480653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 210058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2114301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4669595 # Total bandwidth to/from this memory (bytes/s) +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.091712 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996693675000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.184801 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.011550 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.011550 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.091712 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.005732 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.005732 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses -system.iocache.demand_misses::total 47628 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses -system.iocache.overall_misses::total 47628 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137681932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 137681932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9939428160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9939428160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10077110092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10077110092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10077110092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10077110092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138301932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 138301932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9924152160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9924152160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10062454092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10062454092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10062454092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10062454092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +87,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151632.083700 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 151632.083700 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212744.609589 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212744.609589 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211579.534979 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211579.534979 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72537008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151646.855263 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151646.855263 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212417.640411 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212417.640411 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211254.074824 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211254.074824 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 71289012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8981 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8825 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8076.718406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8078.075014 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 908 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47628 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47628 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47628 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47628 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90434000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90434000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7509668946 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7509668946 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7600102946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7600102946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90847000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90847000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7494384978 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7494384978 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7585231978 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7585231978 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,18 +129,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99596.916300 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 99596.916300 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160737.777098 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160737.777098 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99612.938596 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99612.938596 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160410.637372 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160410.637372 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -393,141 +150,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 465816448 # number of cpu cycles simulated +system.cpu.numCycles 448616710 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86514848 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86514848 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1196192 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82053392 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79452542 # Number of BTB hits +system.cpu.BPredUnit.lookups 86513922 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86513922 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1185612 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81821696 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79447101 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31181464 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427226624 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86514848 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79452542 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164016210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5124580 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 155814 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 72471814 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36433 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 65503 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9296745 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 539923 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4055 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 271815204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.102878 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406830 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27982708 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427301680 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86513922 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79447101 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164025545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5056665 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 120243 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63002299 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 57009 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9269960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 518545 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3708 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 259058563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.256074 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417846 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108229721 39.82% 39.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1589699 0.58% 40.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71960202 26.47% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971866 0.36% 67.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1623537 0.60% 67.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2454126 0.90% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122252 0.41% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1424890 0.52% 69.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82438911 30.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95463641 36.85% 36.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1593246 0.62% 37.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71955070 27.78% 65.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 970468 0.37% 65.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1621274 0.63% 66.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2451045 0.95% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1124441 0.43% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1422902 0.55% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82456476 31.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271815204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185727 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.917157 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34976255 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69906357 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159691682 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3353316 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3887594 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840157503 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1253 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3887594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37933620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43316590 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11886084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159761513 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15029803 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836332638 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33622 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7171271 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5982447 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16586 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998051723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816227596 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816227024 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 572 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964187470 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33864246 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 467105 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 474137 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 32047540 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336278 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10273791 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1251259 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 987046 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829985579 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1254715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824362930 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185325 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23972130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36446956 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 204607 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271815204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.032807 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.413784 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 259058563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192846 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952487 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31703593 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60473195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159750936 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3297057 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3833782 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840221922 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1208 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3833782 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34472569 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37379630 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10860587 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159949927 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12562068 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836350803 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21427 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5922094 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4820401 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7659 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998159477 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816297556 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816296596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 960 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964421570 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33737900 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28941579 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17313500 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10257423 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1154419 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 952791 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829902104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256068 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824407567 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167070 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23703242 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36101298 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203347 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 259058563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.182321 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385461 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82518813 30.36% 30.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18405041 6.77% 37.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10590940 3.90% 41.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7611334 2.80% 43.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75787785 27.88% 71.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3621369 1.33% 73.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72414876 26.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 725602 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 139444 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72075437 27.82% 27.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15729256 6.07% 33.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10360511 4.00% 37.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7565386 2.92% 40.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75947592 29.32% 70.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3904357 1.51% 71.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72537575 28.00% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 784064 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 154385 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271815204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 259058563 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 330736 32.15% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548005 53.27% 85.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150045 14.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 356821 33.57% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553408 52.07% 85.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152587 14.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308450 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796558014 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 305253 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796599749 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -556,246 +313,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18020026 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9476440 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18032887 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9469678 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824362930 # Type of FU issued -system.cpu.iq.rate 1.769716 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1028786 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1921889039 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855222885 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819729616 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825083173 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1659720 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824407567 # Type of FU issued +system.cpu.iq.rate 1.837666 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1062816 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001289 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1909237330 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854871180 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819733271 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 242 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 64 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825165021 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3372872 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25465 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11865 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1866399 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3332196 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26785 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11385 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1841480 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917615 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932351 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11661 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3887594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28830241 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2469402 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831240294 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338803 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336278 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10273791 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725681 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1777576 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17730 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11865 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 713088 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 629130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1342218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822392031 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17604275 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1970898 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3833782 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26055488 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116129 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831158172 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342184 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17313500 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10257423 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725671 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616608 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15691 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11385 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 710592 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 622404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1332996 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822394271 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17607905 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2013295 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26833761 # number of memory reference insts executed -system.cpu.iew.exec_branches 83292230 # Number of branches executed -system.cpu.iew.exec_stores 9229486 # Number of stores executed -system.cpu.iew.exec_rate 1.765485 # Inst execution rate -system.cpu.iew.wb_sent 821862423 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819729668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639700217 # num instructions producing a value -system.cpu.iew.wb_consumers 1045258728 # num instructions consuming a value +system.cpu.iew.exec_refs 26830923 # number of memory reference insts executed +system.cpu.iew.exec_branches 83287562 # Number of branches executed +system.cpu.iew.exec_stores 9223018 # Number of stores executed +system.cpu.iew.exec_rate 1.833178 # Inst execution rate +system.cpu.iew.wb_sent 821886032 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819733335 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640537929 # num instructions producing a value +system.cpu.iew.wb_consumers 1046481965 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.759770 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612002 # average fanout of values written-back +system.cpu.iew.wb_rate 1.827247 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612087 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24883748 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050106 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1201289 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267943051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.009053 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862554 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24617298 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052719 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1189640 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255240182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.159513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.852385 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95668224 35.70% 35.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12347484 4.61% 40.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3939395 1.47% 41.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74898098 27.95% 69.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2419496 0.90% 70.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1554494 0.58% 71.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1057385 0.39% 71.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70928163 26.47% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5130312 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83212701 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11927297 4.67% 37.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4018442 1.57% 38.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74971615 29.37% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2476707 0.97% 69.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1494205 0.59% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000959 0.39% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70934027 27.79% 97.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5204229 2.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267943051 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407858031 # Number of instructions committed -system.cpu.commit.committedOps 806254969 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255240182 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407963822 # Number of instructions committed +system.cpu.commit.committedOps 806434654 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22370795 # Number of memory references committed -system.cpu.commit.loads 13963403 # Number of loads committed -system.cpu.commit.membars 471705 # Number of memory barriers committed -system.cpu.commit.branches 82181312 # Number of branches committed +system.cpu.commit.refs 22397244 # Number of memory references committed +system.cpu.commit.loads 13981301 # Number of loads committed +system.cpu.commit.membars 473469 # Number of memory barriers committed +system.cpu.commit.branches 82197284 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735195017 # Number of committed integer instructions. +system.cpu.commit.int_insts 735369790 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5130312 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5204229 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1093872885 # The number of ROB reads -system.cpu.rob.rob_writes 1666184214 # The number of ROB writes -system.cpu.timesIdled 1421273 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194001244 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9862059849 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407858031 # Number of Instructions Simulated -system.cpu.committedOps 806254969 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407858031 # Number of Instructions Simulated -system.cpu.cpi 1.142104 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.142104 # CPI: Total CPI of All Threads -system.cpu.ipc 0.875577 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.875577 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508209791 # number of integer regfile reads -system.cpu.int_regfile_writes 977816443 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 265196274 # number of misc regfile reads -system.cpu.misc_regfile_writes 402502 # number of misc regfile writes -system.cpu.icache.replacements 1071989 # number of replacements -system.cpu.icache.tagsinuse 510.817098 # Cycle average of tags in use -system.cpu.icache.total_refs 8149627 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072501 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.598713 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.817098 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997690 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997690 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8149627 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8149627 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8149627 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8149627 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8149627 # number of overall hits -system.cpu.icache.overall_hits::total 8149627 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1147113 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1147113 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1147113 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1147113 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1147113 # number of overall misses -system.cpu.icache.overall_misses::total 1147113 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18981109491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18981109491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18981109491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18981109491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18981109491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18981109491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9296740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9296740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9296740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9296740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9296740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9296740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123389 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123389 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123389 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123389 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123389 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123389 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16546.852395 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16546.852395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16546.852395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16546.852395 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3167993 # number of cycles access was blocked +system.cpu.rob.rob_reads 1081009655 # The number of ROB reads +system.cpu.rob.rob_writes 1665958243 # The number of ROB writes +system.cpu.timesIdled 1218536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189558147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9801971615 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407963822 # Number of Instructions Simulated +system.cpu.committedOps 806434654 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407963822 # Number of Instructions Simulated +system.cpu.cpi 1.099648 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.099648 # CPI: Total CPI of All Threads +system.cpu.ipc 0.909382 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.909382 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508373932 # number of integer regfile reads +system.cpu.int_regfile_writes 977906784 # number of integer regfile writes +system.cpu.fp_regfile_reads 64 # number of floating regfile reads +system.cpu.misc_regfile_reads 265175533 # number of misc regfile reads +system.cpu.misc_regfile_writes 402332 # number of misc regfile writes +system.cpu.icache.replacements 1068558 # number of replacements +system.cpu.icache.tagsinuse 510.894483 # Cycle average of tags in use +system.cpu.icache.total_refs 8130546 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1069070 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.605251 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.894483 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997841 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997841 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8130546 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8130546 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8130546 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8130546 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8130546 # number of overall hits +system.cpu.icache.overall_hits::total 8130546 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139410 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139410 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139410 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139410 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139410 # number of overall misses +system.cpu.icache.overall_misses::total 1139410 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15243937992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15243937992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15243937992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15243937992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15243937992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15243937992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9269956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9269956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9269956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9269956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9269956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9269956 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13378.799547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13378.799547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13378.799547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13378.799547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13378.799547 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2477494 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 401 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7900.231920 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9753.913386 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72595 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72595 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 72595 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 72595 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 72595 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 72595 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1074518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1074518 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1074518 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1074518 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1074518 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14814669993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14814669993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14814669993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14814669993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14814669993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14814669993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13787.270193 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13787.270193 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68152 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68152 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68152 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68152 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68152 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68152 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071258 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071258 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071258 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071258 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071258 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071258 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12539776496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12539776496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12539776496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12539776496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12539776496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12539776496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115562 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115562 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115562 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11705.654937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11705.654937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11705.654937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11705.654937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9931 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.048032 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 33329 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9947 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.350658 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5125253660500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.048032 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.378002 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.378002 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 33326 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 33326 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9803 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.028064 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28000 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9816 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.852486 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5098956249000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028064 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376754 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376754 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28010 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28010 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 33329 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 33329 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 33329 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 33329 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10825 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10825 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10825 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10825 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10825 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10825 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 178140000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 178140000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 178140000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 178140000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 178140000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 178140000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 44151 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 44151 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28013 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28013 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28013 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28013 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10692 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10692 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10692 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10692 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10692 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10692 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117857500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117857500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117857500 # 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number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 44154 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245181 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245181 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245165 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.245165 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245165 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.245165 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16456.351039 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16456.351039 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16456.351039 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38705 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38705 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38705 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38705 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.276265 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.276265 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.276243 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.276243 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.276243 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.276243 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11022.961092 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11022.961092 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11022.961092 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,78 +561,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10825 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10825 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10825 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10825 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10825 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10825 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 145034027 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 145034027 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 145034027 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 145034027 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 145034027 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 145034027 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245181 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245181 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245165 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245165 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13398.062540 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1616 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1616 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10692 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10692 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10692 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10692 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10692 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10692 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96471005 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96471005 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96471005 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96471005 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96471005 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96471005 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.276265 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.276265 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.276243 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.276243 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.276243 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9022.727740 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9022.727740 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9022.727740 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109056 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.865602 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139886 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109072 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.282511 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108962066000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.865602 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866600 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.866600 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139886 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139886 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139886 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139886 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139886 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110096 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110096 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110096 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110096 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110096 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110096 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2001823500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2001823500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2001823500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2001823500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2001823500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2001823500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249982 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 249982 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249982 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 249982 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249982 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 249982 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.440416 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.440416 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.440416 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.440416 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.440416 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.440416 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18182.527067 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18182.527067 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109091 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 11.986906 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 138731 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109107 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.271513 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.986906 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749182 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.749182 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138731 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 138731 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138731 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 138731 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138731 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 138731 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110113 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110113 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110113 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110113 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110113 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110113 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1378090500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1378090500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1378090500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1378090500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1378090500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1378090500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248844 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 248844 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248844 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 248844 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248844 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 248844 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442498 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442498 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442498 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442498 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442498 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442498 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12515.238891 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12515.238891 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12515.238891 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12515.238891 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -884,146 +641,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35215 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35215 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110096 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110096 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110096 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110096 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110096 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110096 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1668892003 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1668892003 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1668892003 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.440416 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.440416 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.440416 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15158.516231 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 32856 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 32856 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110113 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110113 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110113 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110113 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110113 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110113 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1157860508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1157860508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1157860508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442498 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442498 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442498 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442498 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.202637 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.202637 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1672208 # number of replacements -system.cpu.dcache.tagsinuse 511.998155 # Cycle average of tags in use -system.cpu.dcache.total_refs 19212274 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1672720 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.485649 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998155 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11127928 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11127928 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8079547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8079547 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48812772000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10760956984 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10760956984 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 59573728984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 59573728984 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 59573728984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 59573728984 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13398949 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13398949 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398111 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398111 # 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