diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
3 files changed, 2931 insertions, 2747 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 6ae80aee8..e98e38022 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137972 # Number of seconds simulated -sim_ticks 5137971999000 # Number of ticks simulated -final_tick 5137971999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.141960 # Number of seconds simulated +sim_ticks 5141959613000 # Number of ticks simulated +final_tick 5141959613000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151274 # Simulator instruction rate (inst/s) -host_op_rate 299020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1905679647 # Simulator tick rate (ticks/s) -host_mem_usage 770140 # Number of bytes of host memory used -host_seconds 2696.14 # Real time elapsed on the host -sim_insts 407854776 # Number of instructions simulated -sim_ops 806198141 # Number of ops (including micro ops) simulated +host_inst_rate 152486 # Simulator instruction rate (inst/s) +host_op_rate 301416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1922658876 # Simulator tick rate (ticks/s) +host_mem_usage 770128 # Number of bytes of host memory used +host_seconds 2674.40 # Real time elapsed on the host +sim_insts 407807707 # Number of instructions simulated +sim_ops 806107146 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2477120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1034624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10750336 # Number of bytes read from this memory -system.physmem.bytes_read::total 14265472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1034624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1034624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9529024 # Number of bytes written to this memory -system.physmem.bytes_written::total 9529024 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38705 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167974 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222898 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148891 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148891 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2092331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2776479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201368 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201368 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1854627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1854627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1854627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2092331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4631107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222898 # Number of read requests accepted -system.physmem.writeReqs 148891 # Number of write requests accepted -system.physmem.readBursts 222898 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148891 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14252672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12800 # Total number of bytes read from write queue -system.physmem.bytesWritten 9527360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14265472 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9529024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 200 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2476992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1035072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10749056 # Number of bytes read from this memory +system.physmem.bytes_read::total 14265280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1035072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1035072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9521344 # Number of bytes written to this memory +system.physmem.bytes_written::total 9521344 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38703 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16173 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222895 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148771 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148771 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 481721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2090459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2774289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1851696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1851696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1851696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 481721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2090459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4625984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222895 # Number of read requests accepted +system.physmem.writeReqs 148771 # Number of write requests accepted +system.physmem.readBursts 222895 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148771 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14256576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 9520064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14265280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9521344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1701 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14548 # Per bank write bursts -system.physmem.perBankRdBursts::1 13887 # Per bank write bursts -system.physmem.perBankRdBursts::2 14162 # Per bank write bursts -system.physmem.perBankRdBursts::3 13520 # Per bank write bursts -system.physmem.perBankRdBursts::4 14300 # Per bank write bursts -system.physmem.perBankRdBursts::5 13581 # Per bank write bursts -system.physmem.perBankRdBursts::6 13426 # Per bank write bursts -system.physmem.perBankRdBursts::7 13413 # Per bank write bursts -system.physmem.perBankRdBursts::8 13607 # Per bank write bursts -system.physmem.perBankRdBursts::9 13662 # Per bank write bursts -system.physmem.perBankRdBursts::10 13602 # Per bank write bursts -system.physmem.perBankRdBursts::11 13631 # Per bank write bursts -system.physmem.perBankRdBursts::12 14336 # Per bank write bursts -system.physmem.perBankRdBursts::13 14588 # Per bank write bursts -system.physmem.perBankRdBursts::14 14340 # Per bank write bursts -system.physmem.perBankRdBursts::15 14095 # Per bank write bursts -system.physmem.perBankWrBursts::0 9881 # Per bank write bursts -system.physmem.perBankWrBursts::1 9301 # Per bank write bursts -system.physmem.perBankWrBursts::2 9417 # Per bank write bursts -system.physmem.perBankWrBursts::3 9104 # Per bank write bursts -system.physmem.perBankWrBursts::4 9702 # Per bank write bursts -system.physmem.perBankWrBursts::5 8858 # Per bank write bursts -system.physmem.perBankWrBursts::6 8862 # Per bank write bursts -system.physmem.perBankWrBursts::7 8906 # Per bank write bursts -system.physmem.perBankWrBursts::8 8978 # Per bank write bursts -system.physmem.perBankWrBursts::9 9056 # Per bank write bursts -system.physmem.perBankWrBursts::10 9081 # Per bank write bursts -system.physmem.perBankWrBursts::11 9102 # Per bank write bursts -system.physmem.perBankWrBursts::12 9605 # Per bank write bursts -system.physmem.perBankWrBursts::13 9854 # Per bank write bursts -system.physmem.perBankWrBursts::14 9646 # Per bank write bursts -system.physmem.perBankWrBursts::15 9512 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1680 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14406 # Per bank write bursts +system.physmem.perBankRdBursts::1 13692 # Per bank write bursts +system.physmem.perBankRdBursts::2 14137 # Per bank write bursts +system.physmem.perBankRdBursts::3 13444 # Per bank write bursts +system.physmem.perBankRdBursts::4 14027 # Per bank write bursts +system.physmem.perBankRdBursts::5 13372 # Per bank write bursts +system.physmem.perBankRdBursts::6 13359 # Per bank write bursts +system.physmem.perBankRdBursts::7 13805 # Per bank write bursts +system.physmem.perBankRdBursts::8 13762 # Per bank write bursts +system.physmem.perBankRdBursts::9 13592 # Per bank write bursts +system.physmem.perBankRdBursts::10 13956 # Per bank write bursts +system.physmem.perBankRdBursts::11 13564 # Per bank write bursts +system.physmem.perBankRdBursts::12 14528 # Per bank write bursts +system.physmem.perBankRdBursts::13 14698 # Per bank write bursts +system.physmem.perBankRdBursts::14 14291 # Per bank write bursts +system.physmem.perBankRdBursts::15 14126 # Per bank write bursts +system.physmem.perBankWrBursts::0 9807 # Per bank write bursts +system.physmem.perBankWrBursts::1 9166 # Per bank write bursts +system.physmem.perBankWrBursts::2 9421 # Per bank write bursts +system.physmem.perBankWrBursts::3 8835 # Per bank write bursts +system.physmem.perBankWrBursts::4 9422 # Per bank write bursts +system.physmem.perBankWrBursts::5 8917 # Per bank write bursts +system.physmem.perBankWrBursts::6 8763 # Per bank write bursts +system.physmem.perBankWrBursts::7 9221 # Per bank write bursts +system.physmem.perBankWrBursts::8 9116 # Per bank write bursts +system.physmem.perBankWrBursts::9 9134 # Per bank write bursts +system.physmem.perBankWrBursts::10 9470 # Per bank write bursts +system.physmem.perBankWrBursts::11 8904 # Per bank write bursts +system.physmem.perBankWrBursts::12 9718 # Per bank write bursts +system.physmem.perBankWrBursts::13 9806 # Per bank write bursts +system.physmem.perBankWrBursts::14 9580 # Per bank write bursts +system.physmem.perBankWrBursts::15 9471 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 5137971883500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5141959559500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222898 # Read request sizes (log2) +system.physmem.readPktSize::6 222895 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148891 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 173419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 836 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148771 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 173187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,224 +156,223 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.994064 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.175651 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 374.202346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15813 31.71% 31.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11064 22.19% 53.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5080 10.19% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2824 5.66% 69.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1980 3.97% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1284 2.57% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 922 1.85% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 716 1.44% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10185 20.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49868 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8142 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.350037 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 531.765782 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 8141 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 74587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.776409 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.138812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.199277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28275 37.91% 37.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16828 22.56% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7503 10.06% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4244 5.69% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3057 4.10% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2068 2.77% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1382 1.85% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1175 1.58% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10055 13.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8285 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.884007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 527.034010 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 8284 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8142 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.283591 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.627324 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.611364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 6056 74.38% 74.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1276 15.67% 90.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 101 1.24% 91.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 41 0.50% 91.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 52 0.64% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 70 0.86% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 65 0.80% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 71 0.87% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 51 0.63% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 44 0.54% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 56 0.69% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 33 0.41% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 34 0.42% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 29 0.36% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 35 0.43% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 23 0.28% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 19 0.23% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 12 0.15% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 12 0.15% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 9 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 6 0.07% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 7 0.09% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 2 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 13 0.16% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 13 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 4 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::74-75 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 2 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8142 # Writes before turning the bus around for reads -system.physmem.totQLat 5275412250 # Total ticks spent queuing -system.physmem.totMemAccLat 9510468500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1113490000 # Total ticks spent in databus transfers -system.physmem.totBankLat 3121566250 # Total ticks spent accessing banks -system.physmem.avgQLat 23688.64 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14017.04 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 8285 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8285 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.954255 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.428609 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.676130 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 6158 74.33% 74.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1338 16.15% 90.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 52 0.63% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 77 0.93% 92.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 47 0.57% 92.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 55 0.66% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 103 1.24% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 89 1.07% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 47 0.57% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 58 0.70% 96.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 37 0.45% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 45 0.54% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 69 0.83% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 27 0.33% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 11 0.13% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 16 0.19% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 22 0.27% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 4 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 7 0.08% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 2 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 5 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 4 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-89 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8285 # Writes before turning the bus around for reads +system.physmem.totQLat 4923822749 # Total ticks spent queuing +system.physmem.totMemAccLat 9100553999 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1113795000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22103.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42705.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 40853.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.02 # Average write queue length when enqueuing -system.physmem.readRowHits 186969 # Number of row buffer hits during reads -system.physmem.writeRowHits 110725 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes -system.physmem.avgGap 13819590.91 # Average gap between requests -system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 5100645 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662331 # Transaction distribution -system.membus.trans_dist::ReadResp 662323 # Transaction distribution -system.membus.trans_dist::WriteReq 13764 # Transaction distribution -system.membus.trans_dist::WriteResp 13764 # Transaction distribution -system.membus.trans_dist::Writeback 148891 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1718 # Transaction distribution -system.membus.trans_dist::ReadExReq 179464 # Transaction distribution -system.membus.trans_dist::ReadExResp 179461 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721276 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 133006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 133006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1857568 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18330624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20122575 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5463872 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25593019 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25593019 # Total data (bytes) -system.membus.snoop_data_through_bus 613952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250521000 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing +system.physmem.readRowHits 186870 # Number of row buffer hits during reads +system.physmem.writeRowHits 110052 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.97 # Row buffer hit rate for writes +system.physmem.avgGap 13834893.59 # Average gap between requests +system.physmem.pageHitRate 79.92 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4934274417750 # Time in different power states +system.physmem.memoryStateTime::REF 171701140000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 35983950250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 5095093 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662466 # Transaction distribution +system.membus.trans_dist::ReadResp 662464 # Transaction distribution +system.membus.trans_dist::WriteReq 13782 # Transaction distribution +system.membus.trans_dist::WriteResp 13782 # Transaction distribution +system.membus.trans_dist::Writeback 148771 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution +system.membus.trans_dist::ReadExReq 179320 # Transaction distribution +system.membus.trans_dist::ReadExResp 179319 # Transaction distribution +system.membus.trans_dist::MessageReq 1645 # Transaction distribution +system.membus.trans_dist::MessageResp 1645 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475021 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721191 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132996 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1857477 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550161 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20114933 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5463680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25585193 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25585193 # Total data (bytes) +system.membus.snoop_data_through_bus 613568 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250592000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583253500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583283000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1611616249 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1610033997 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3152435901 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3152758703 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429736248 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429601748 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47579 # number of replacements -system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use +system.iocache.tags.replacements 47571 # number of replacements +system.iocache.tags.tagsinuse 0.128712 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992993838000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992977133000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128712 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008045 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.008045 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428697 # Number of tag accesses -system.iocache.tags.data_accesses 428697 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses -system.iocache.ReadReq_misses::total 913 # number of ReadReq misses +system.iocache.tags.tag_accesses 428634 # Number of tag accesses +system.iocache.tags.data_accesses 428634 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses +system.iocache.ReadReq_misses::total 906 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses -system.iocache.demand_misses::total 47633 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses -system.iocache.overall_misses::total 47633 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149265435 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149265435 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11474717915 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11474717915 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11623983350 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11623983350 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11623983350 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11623983350 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses +system.iocache.demand_misses::total 47626 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses +system.iocache.overall_misses::total 47626 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147491196 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 147491196 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11109159898 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11109159898 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11256651094 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11256651094 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11256651094 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11256651094 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -382,40 +381,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163488.975904 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 163488.975904 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245606.119756 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 245606.119756 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 244032.148930 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244032.148930 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 244032.148930 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 177888 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162793.814570 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 237781.675899 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 236355.165120 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 236355.165120 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 159859 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 14382 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14672 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.368794 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.895515 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101762935 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101762935 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9043225919 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9043225919 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9144988854 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9144988854 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9144988854 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100353196 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100353196 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8677810402 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8677810402 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8778163598 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8778163598 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -424,18 +423,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111459.950712 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 111459.950712 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193562.198609 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 193562.198609 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 191988.513300 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -445,16 +444,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 637649 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225561 # Transaction distribution -system.iobus.trans_dist::ReadResp 225561 # Transaction distribution -system.iobus.trans_dist::WriteReq 57591 # Transaction distribution -system.iobus.trans_dist::WriteResp 57591 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.throughput 637150 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225562 # Transaction distribution +system.iobus.trans_dist::ReadResp 225562 # Transaction distribution +system.iobus.trans_dist::WriteReq 57606 # Transaction distribution +system.iobus.trans_dist::WriteResp 57606 # Transaction distribution +system.iobus.trans_dist::MessageReq 1645 # Transaction distribution +system.iobus.trans_dist::MessageResp 1645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -470,15 +469,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569626 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -494,20 +493,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276222 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276222 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3918904 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276200 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3930346 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -537,155 +536,155 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 425268102 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424685346 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53403752 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53671252 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85606951 # Number of BP lookups -system.cpu.branchPred.condPredicted 85606951 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 878900 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79252981 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77536604 # Number of BTB hits +system.cpu.branchPred.lookups 85633263 # Number of BP lookups +system.cpu.branchPred.condPredicted 85633263 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 884686 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79267379 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77548662 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.834306 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1442152 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179942 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.831747 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440338 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180105 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 453123649 # number of cpu cycles simulated +system.cpu.numCycles 453234333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25513299 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422793316 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85606951 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78978756 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162666775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3977899 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 109317 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 70887668 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43514 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89257 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8479758 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 384207 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2414 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262364646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.182537 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25483623 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422835891 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85633263 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78989000 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162683938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4002747 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 108573 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 70983982 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43526 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 92374 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8487571 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384793 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2466 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262469836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.181706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411661 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100112047 38.16% 38.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1537808 0.59% 38.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71834602 27.38% 66.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 894624 0.34% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1560586 0.59% 67.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2393199 0.91% 67.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1018516 0.39% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1331320 0.51% 68.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81681944 31.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100201994 38.18% 38.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1531970 0.58% 38.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71824716 27.36% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 909581 0.35% 66.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1572022 0.60% 67.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2391233 0.91% 67.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1015593 0.39% 68.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1327813 0.51% 68.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81694914 31.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262364646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.933064 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29407134 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68048451 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158512522 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3341909 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3054630 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832669874 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3054630 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32105381 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42832622 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12466754 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158806940 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13098319 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829768905 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20738 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6073581 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5148249 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991466417 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800660067 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1107048961 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 106 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964157062 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27309353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 454429 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 460129 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29597584 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16731616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9822119 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1090956 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 912656 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824999655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1185445 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 821065367 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 147374 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19153823 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29264539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 130709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262364646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.129482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399412 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262469836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188938 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.932930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29410093 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68121182 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158520657 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3344277 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3073627 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832752013 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3073627 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32108860 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42947155 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12423337 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158815296 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13101561 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829828808 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20476 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6069323 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5155919 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991491995 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800757525 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1107104494 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964043985 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27448008 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 454148 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459927 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29603104 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16744391 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9834089 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1098610 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 922271 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825029586 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184674 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 821050392 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 152353 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19282759 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29404306 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 129800 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262469836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.128170 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399623 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75980319 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15750588 6.00% 34.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10556494 4.02% 38.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7365908 2.81% 41.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75746368 28.87% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3736962 1.42% 72.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72307682 27.56% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 774907 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145418 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76068971 28.98% 28.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15764450 6.01% 34.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10561557 4.02% 39.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7380977 2.81% 41.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75732754 28.85% 70.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3744713 1.43% 72.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72297753 27.55% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 770490 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 148171 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262364646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262469836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 352804 33.38% 33.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 895 0.08% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548620 51.91% 85.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 154313 14.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 351121 33.32% 33.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 242 0.02% 33.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 235 0.02% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548827 52.08% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153397 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 307554 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793584898 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150109 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124066 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 310274 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793553745 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150127 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124319 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -712,297 +711,332 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17676623 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9222117 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17682976 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9228951 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 821065367 # Type of FU issued -system.cpu.iq.rate 1.812012 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1056873 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905808819 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845349453 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817155578 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 173 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821814606 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 80 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1693534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 821050392 # Type of FU issued +system.cpu.iq.rate 1.811536 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1053822 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905885622 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845507474 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817131376 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 174 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 198 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821793858 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694774 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2731831 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17734 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12108 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1395931 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2743773 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18703 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12097 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1404751 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932011 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12232 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931902 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12205 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3054630 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30960729 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2157350 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826185100 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241589 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16731616 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9822119 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 690497 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620390 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12858 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12108 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 495281 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1001721 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819661058 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17373288 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404308 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3073627 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31062869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2159597 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826214260 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 248339 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16744391 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9834089 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 689465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620816 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13300 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12097 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498594 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 510068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1008662 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819639552 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17378500 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1410839 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26412112 # number of memory reference insts executed -system.cpu.iew.exec_branches 83101028 # Number of branches executed -system.cpu.iew.exec_stores 9038824 # Number of stores executed -system.cpu.iew.exec_rate 1.808913 # Inst execution rate -system.cpu.iew.wb_sent 819257147 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817155626 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638657480 # num instructions producing a value -system.cpu.iew.wb_consumers 1044041746 # num instructions consuming a value +system.cpu.iew.exec_refs 26423310 # number of memory reference insts executed +system.cpu.iew.exec_branches 83104184 # Number of branches executed +system.cpu.iew.exec_stores 9044810 # Number of stores executed +system.cpu.iew.exec_rate 1.808423 # Inst execution rate +system.cpu.iew.wb_sent 819235043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817131426 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638623234 # num instructions producing a value +system.cpu.iew.wb_consumers 1043962608 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.803383 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611716 # average fanout of values written-back +system.cpu.iew.wb_rate 1.802890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19877862 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054736 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 888910 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259310016 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.109013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863250 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19998130 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054874 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 894775 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259396209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.107629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863349 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87730314 33.83% 33.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11862694 4.57% 38.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3835821 1.48% 39.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74768182 28.83% 68.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2381229 0.92% 69.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1479438 0.57% 70.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 861979 0.33% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70857593 27.33% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5532766 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87828444 33.86% 33.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11868241 4.58% 38.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3842531 1.48% 39.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74752258 28.82% 68.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2384729 0.92% 69.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1479281 0.57% 70.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859408 0.33% 70.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70845236 27.31% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5536081 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259310016 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407854776 # Number of instructions committed -system.cpu.commit.committedOps 806198141 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259396209 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407807707 # Number of instructions committed +system.cpu.commit.committedOps 806107146 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22425972 # Number of memory references committed -system.cpu.commit.loads 13999784 # Number of loads committed -system.cpu.commit.membars 474669 # Number of memory barriers committed -system.cpu.commit.branches 82177261 # Number of branches committed +system.cpu.commit.refs 22429955 # Number of memory references committed +system.cpu.commit.loads 14000617 # Number of loads committed +system.cpu.commit.membars 474711 # Number of memory barriers committed +system.cpu.commit.branches 82167469 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735033306 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155486 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5532766 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734952495 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155627 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174437 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783236239 97.16% 97.18% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144862 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121653 0.02% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14000617 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8429338 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 806107146 # Class of committed instruction +system.cpu.commit.bw_lim_events 5536081 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079774887 # The number of ROB reads -system.cpu.rob.rob_writes 1655221365 # The number of ROB writes -system.cpu.timesIdled 1257777 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190759003 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9822826051 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407854776 # Number of Instructions Simulated -system.cpu.committedOps 806198141 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407854776 # Number of Instructions Simulated -system.cpu.cpi 1.110993 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.110993 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900096 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.900096 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088904390 # number of integer regfile reads -system.cpu.int_regfile_writes 653903158 # number of integer regfile writes -system.cpu.fp_regfile_reads 48 # number of floating regfile reads -system.cpu.cc_regfile_reads 415697548 # number of cc regfile reads -system.cpu.cc_regfile_writes 321557341 # number of cc regfile writes -system.cpu.misc_regfile_reads 264102486 # number of misc regfile reads -system.cpu.misc_regfile_writes 402568 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53587278 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3014875 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3014340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1579042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 336648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 289942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1911181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6131826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18757 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 150026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8211790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61153920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207959183 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 582080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5191488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274886671 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274861071 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 468864 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4035423910 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1079887016 # The number of ROB reads +system.cpu.rob.rob_writes 1655298855 # The number of ROB writes +system.cpu.timesIdled 1259672 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190764497 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9830690598 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407807707 # Number of Instructions Simulated +system.cpu.committedOps 806107146 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407807707 # Number of Instructions Simulated +system.cpu.cpi 1.111392 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111392 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088844162 # number of integer regfile reads +system.cpu.int_regfile_writes 653876789 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.cc_regfile_reads 415644137 # number of cc regfile reads +system.cpu.cc_regfile_writes 321521730 # number of cc regfile writes +system.cpu.misc_regfile_reads 264115519 # number of misc regfile reads +system.cpu.misc_regfile_writes 402672 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53624827 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3015737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3015197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1584798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 336401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 289692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6128379 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8215578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61059136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207801717 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 607680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5615104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 275083637 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 275059381 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 677312 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4044441846 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 568500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1436807344 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1434613560 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3142634309 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3141764506 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14495745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14738244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 103414152 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 107967138 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 955079 # number of replacements -system.cpu.icache.tags.tagsinuse 509.954947 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7470392 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 955591 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.817562 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147668859250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.954947 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996006 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 953583 # number of replacements +system.cpu.icache.tags.tagsinuse 509.342760 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7479724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 954095 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.839601 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147639960250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.342760 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994810 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994810 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9435405 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9435405 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7470392 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7470392 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7470392 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7470392 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7470392 # number of overall hits -system.cpu.icache.overall_hits::total 7470392 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1009362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1009362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1009362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1009362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1009362 # number of overall misses -system.cpu.icache.overall_misses::total 1009362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14063763284 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14063763284 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14063763284 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14063763284 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14063763284 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14063763284 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8479754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8479754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8479754 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8479754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8479754 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8479754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13933.319546 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13933.319546 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13933.319546 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13933.319546 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13933.319546 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4512 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9441724 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9441724 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7479724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7479724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7479724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7479724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7479724 # number of overall hits +system.cpu.icache.overall_hits::total 7479724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1007844 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1007844 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1007844 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1007844 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1007844 # number of overall misses +system.cpu.icache.overall_misses::total 1007844 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14035582232 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14035582232 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14035582232 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14035582232 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14035582232 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14035582232 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8487568 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8487568 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8487568 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8487568 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8487568 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8487568 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118744 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118744 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118744 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118744 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118744 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118744 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13926.343990 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13926.343990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13926.343990 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13926.343990 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4168 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 173 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.080925 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.936842 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53711 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53711 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53711 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53711 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53711 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53711 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955651 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 955651 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 955651 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 955651 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 955651 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 955651 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11613116903 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11613116903 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11613116903 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11613116903 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11613116903 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11613116903 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112698 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112698 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112698 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112698 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12152.048083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12152.048083 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12152.048083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12152.048083 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53688 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53688 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53688 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53688 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53688 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53688 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954156 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 954156 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 954156 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 954156 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 954156 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 954156 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587558437 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11587558437 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587558437 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11587558437 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587558437 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11587558437 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112418 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112418 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112418 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112418 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12144.301809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12144.301809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12144.301809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12144.301809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8788 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 5.050842 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 20362 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8802 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.313338 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5105053160000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 5.050842 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.315678 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.315678 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 8939 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.031288 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21114 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8953 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.358316 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031288 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376956 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376956 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 69716 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 69716 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20363 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20363 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 71741 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 71741 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21134 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21134 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20365 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 20365 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20365 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 20365 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9662 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9662 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9662 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9662 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9662 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9662 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 109674498 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 109674498 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 109674498 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 109674498 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 109674498 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 109674498 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30025 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30025 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21136 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21136 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21136 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21136 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 107949749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 107949749 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 107949749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 107949749 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 107949749 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 107949749 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30957 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30957 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30027 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30027 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30027 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30027 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.321799 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.321799 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.321777 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.321777 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.321777 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.321777 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11351.117574 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11351.117574 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11351.117574 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11351.117574 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11351.117574 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11351.117574 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30959 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30959 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30959 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30959 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.317311 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.317311 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.317291 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.317291 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.317291 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.317291 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10989.488853 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10989.488853 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10989.488853 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10989.488853 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10989.488853 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1011,85 +1045,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1311 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1311 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9662 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9662 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9662 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9662 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9662 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9662 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 90345008 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 90345008 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 90345008 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 90345008 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 90345008 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 90345008 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.321799 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.321799 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.321777 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.321777 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.321777 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9350.549369 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9350.549369 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9350.549369 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1983 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1983 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88296261 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 88296261 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 88296261 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 88296261 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 88296261 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 88296261 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.317311 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.317311 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.317291 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.317291 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8988.726560 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 67950 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 13.831671 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92323 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 67966 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.358370 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101646178000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.831671 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.864479 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.864479 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 70861 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 12.940736 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 90199 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70877 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.272613 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 12.940736 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.808796 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.808796 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 391373 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 391373 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92323 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92323 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92323 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92323 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92323 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92323 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68909 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68909 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68909 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68909 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68909 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68909 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 862549215 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 862549215 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 862549215 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 862549215 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 862549215 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 862549215 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161232 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 161232 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161232 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 161232 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161232 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 161232 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.427390 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.427390 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.427390 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.427390 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.427390 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.427390 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12517.221481 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12517.221481 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12517.221481 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12517.221481 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12517.221481 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 396218 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 396218 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90199 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 90199 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90199 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 90199 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90199 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 90199 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71940 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71940 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71940 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71940 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71940 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71940 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 878693205 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 878693205 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 878693205 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 878693205 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 878693205 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 878693205 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162139 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 162139 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162139 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 162139 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162139 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 162139 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.443693 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.443693 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.443693 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.443693 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.443693 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.443693 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1098,153 +1132,153 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 16529 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 16529 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68909 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68909 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68909 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68909 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68909 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68909 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 724629911 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 724629911 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 724629911 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 724629911 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 724629911 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 724629911 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.427390 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.427390 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.427390 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.427390 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.751368 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.751368 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 22838 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 22838 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71940 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71940 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71940 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71940 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71940 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71940 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 734698929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 734698929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 734698929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 734698929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 734698929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 734698929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.443693 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.443693 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.443693 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1659840 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996448 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18992605 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1660352 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.438903 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40084250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996448 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1658766 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994288 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19002910 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1659278 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.452517 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994288 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87845319 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87845319 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10889826 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10889826 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8100117 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8100117 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18989943 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18989943 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18989943 # number of overall hits -system.cpu.dcache.overall_hits::total 18989943 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2239768 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2239768 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316527 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316527 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2556295 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2556295 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2556295 # number of overall misses -system.cpu.dcache.overall_misses::total 2556295 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32903838390 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32903838390 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11976667737 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11976667737 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44880506127 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44880506127 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44880506127 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44880506127 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13129594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13129594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8416644 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8416644 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21546238 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21546238 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21546238 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21546238 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170589 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170589 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118642 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118642 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118642 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118642 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14690.735107 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14690.735107 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37837.744448 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37837.744448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17556.857142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17556.857142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17556.857142 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 388578 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87874474 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87874474 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10896738 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10896738 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8103479 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8103479 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19000217 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19000217 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19000217 # number of overall hits +system.cpu.dcache.overall_hits::total 19000217 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2237270 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2237270 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316309 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316309 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2553579 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2553579 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2553579 # number of overall misses +system.cpu.dcache.overall_misses::total 2553579 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32758938054 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32758938054 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12034849454 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12034849454 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 44793787508 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 44793787508 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 44793787508 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 44793787508 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13134008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13134008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8419788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8419788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21553796 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21553796 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21553796 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21553796 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170342 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170342 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037567 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037567 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118475 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118475 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118475 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118475 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17541.571069 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17541.571069 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 388234 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42159 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.175396 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.208805 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561202 # number of writebacks -system.cpu.dcache.writebacks::total 1561202 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 869210 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 869210 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363380000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363380000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536381000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536381000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899761000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899761000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104387 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104387 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034696 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034696 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17335.555974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17335.555974 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1559977 # number of writebacks +system.cpu.dcache.writebacks::total 1559977 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867558 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 867558 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24476 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 24476 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 892034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 892034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 892034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 892034 # 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average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176012 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.515897 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50592.226872 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.121398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.097025 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2916.382816 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11302.331606 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000154 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.044500 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.172460 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6269 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53720 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977402 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 34623360 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 34623360 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79812.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64343.947730 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66562.066340 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65880.735022 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10624.341649 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10624.341649 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56430.635104 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56430.635104 # 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average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 60 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16173 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36021 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52259 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1437 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1437 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132861 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132861 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 60 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168882 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185120 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 60 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168882 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185120 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4324750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 315250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1030094767 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2339275539 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3374010306 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15289917 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15289917 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7567196573 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7567196573 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4324750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 315250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1030094767 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9906472112 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10941206879 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4324750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1030094767 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9906472112 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10941206879 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251381500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251381500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373144500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373144500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624526000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624526000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026314 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021817 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814626 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814626 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.458657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.458657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068946 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000666 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016952 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101825 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068946 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index cc51e20ce..69bdeab1f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.304497 # Nu sim_ticks 5304496750000 # Number of ticks simulated final_tick 5304496750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156851 # Simulator instruction rate (inst/s) -host_op_rate 300747 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7785889362 # Simulator tick rate (ticks/s) -host_mem_usage 816820 # Number of bytes of host memory used -host_seconds 681.30 # Real time elapsed on the host +host_inst_rate 145026 # Simulator instruction rate (inst/s) +host_op_rate 278074 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7198918941 # Simulator tick rate (ticks/s) +host_mem_usage 818088 # Number of bytes of host memory used +host_seconds 736.85 # Real time elapsed on the host sim_insts 106862058 # Number of instructions simulated sim_ops 204897478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -234,9 +234,7 @@ system.physmem.wrQLenPdf::63 0 # Wh system.physmem.totQLat 0 # Total ticks spent queuing system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 0 # Total ticks spent in databus transfers -system.physmem.totBankLat 0 # Total ticks spent accessing banks system.physmem.avgQLat nan # Average queueing delay per DRAM burst -system.physmem.avgBankLat nan # Average bank access latency per DRAM burst system.physmem.avgBusLat nan # Average bus latency per DRAM burst system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s @@ -255,137 +253,11 @@ system.physmem.readRowHitRate nan # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state -system.iobus.throughput 383259 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 858443 # Transaction distribution -system.iobus.trans_dist::ReadResp 858443 # Transaction distribution -system.iobus.trans_dist::WriteReq 37726 # Transaction distribution -system.iobus.trans_dist::WriteResp 37726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1924 # Transaction distribution -system.iobus.trans_dist::MessageResp 1924 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703384 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1796186 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 484 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972069 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10485 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2032994 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2032994 # Total data (bytes) -system.iobus.reqLayer0.occupancy 45000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10111500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1076000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 95000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1240500 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 41494500 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 23487000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 469626032 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 7795368 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2413900 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1790216000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 80190500 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.physmem.memoryStateTime::IDLE 5127363440000 # Time in different power states +system.physmem.memoryStateTime::REF 177128640000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 0 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 2 # delay histogram for all message system.ruby.delayHist::max_bucket 19 # delay histogram for all message @@ -590,6 +462,136 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.throughput 383259 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 858443 # Transaction distribution +system.iobus.trans_dist::ReadResp 858443 # Transaction distribution +system.iobus.trans_dist::WriteReq 37726 # Transaction distribution +system.iobus.trans_dist::WriteResp 37726 # Transaction distribution +system.iobus.trans_dist::MessageReq 1924 # Transaction distribution +system.iobus.trans_dist::MessageResp 1924 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1796186 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 484 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972069 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10485 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2032994 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2032994 # Total data (bytes) +system.iobus.reqLayer0.occupancy 45000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 10111500 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 1076000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 95000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 1240500 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 41494500 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 23487000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 469626032 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 7795368 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2413900 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1790216000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 80190500 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 10608993500 # number of cpu cycles simulated @@ -617,6 +619,41 @@ system.cpu0.num_busy_cycles 526834059.049901 system.cpu0.not_idle_fraction 0.049659 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.950341 # Percentage of idle cycles system.cpu0.Branches 11678784 # Number of branches fetched +system.cpu0.op_class::No_OpClass 146088 0.13% 0.13% # Class of executed instruction +system.cpu0.op_class::IntAlu 102315691 88.54% 88.66% # Class of executed instruction +system.cpu0.op_class::IntMult 88423 0.08% 88.74% # Class of executed instruction +system.cpu0.op_class::IntDiv 60803 0.05% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 88.79% # Class of executed instruction +system.cpu0.op_class::MemRead 7847946 6.79% 95.58% # Class of executed instruction +system.cpu0.op_class::MemWrite 5106253 4.42% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 115565204 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks @@ -645,6 +682,41 @@ system.cpu1.num_busy_cycles 320373991.077311 system.cpu1.not_idle_fraction 0.030207 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969793 # Percentage of idle cycles system.cpu1.Branches 10261767 # Number of branches fetched +system.cpu1.op_class::No_OpClass 160875 0.18% 0.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 75501866 84.52% 84.70% # Class of executed instruction +system.cpu1.op_class::IntMult 96299 0.11% 84.80% # Class of executed instruction +system.cpu1.op_class::IntDiv 67676 0.08% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.88% # Class of executed instruction +system.cpu1.op_class::MemRead 8734970 9.78% 94.66% # Class of executed instruction +system.cpu1.op_class::MemWrite 4772103 5.34% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 89333789 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.ruby.network.routers0.throttle0.link_utilization 0.041639 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 4c7c80e7e..66a37e2a3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.139775 # Number of seconds simulated -sim_ticks 5139775442500 # Number of ticks simulated -final_tick 5139775442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133875 # Number of seconds simulated +sim_ticks 5133874673500 # Number of ticks simulated +final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235748 # Simulator instruction rate (inst/s) -host_op_rate 468611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4967362364 # Simulator tick rate (ticks/s) -host_mem_usage 954112 # Number of bytes of host memory used -host_seconds 1034.71 # Real time elapsed on the host -sim_insts 243931071 # Number of instructions simulated -sim_ops 484875903 # Number of ops (including micro ops) simulated +host_inst_rate 230895 # Simulator instruction rate (inst/s) +host_op_rate 458967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4861072606 # Simulator tick rate (ticks/s) +host_mem_usage 966208 # Number of bytes of host memory used +host_seconds 1056.12 # Real time elapsed on the host +sim_insts 243852608 # Number of instructions simulated +sim_ops 484724489 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2452480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 439552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5834944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 98048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1717440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 432064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2820032 # Number of bytes read from this memory -system.physmem.bytes_read::total 13796608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 439552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 98048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 432064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9118784 # Number of bytes written to this memory -system.physmem.bytes_written::total 9118784 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38320 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6868 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 91171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1532 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 26835 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 44063 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215572 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142481 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142481 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 477157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 85520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1135253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 334147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 84063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 548668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2684282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 85520 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19076 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 84063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1774160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1774160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1774160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 477157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 85520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1135253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 334147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 84063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 548668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4458442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98736 # Number of read requests accepted -system.physmem.writeReqs 74818 # Number of write requests accepted -system.physmem.readBursts 98736 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 74818 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6312704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.physmem.bytesWritten 4788352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6319104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4788352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 500480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5911104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 139776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1689280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 309696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2752128 # Number of bytes read from this memory +system.physmem.bytes_read::total 13749568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 500480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 139776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 309696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 949952 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9083392 # Number of bytes written to this memory +system.physmem.bytes_written::total 9083392 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38210 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7820 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 92361 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 26395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4839 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 43002 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214837 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141928 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141928 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 97486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1151392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 329046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 60324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 536072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2678205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 97486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 60324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 185036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1769305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1769305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1769305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 97486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1151392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 27226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 329046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 60324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 536072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4447510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 96612 # Number of read requests accepted +system.physmem.writeReqs 73475 # Number of write requests accepted +system.physmem.readBursts 96612 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 73475 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6177024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 4701248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6183168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4702400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 734 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6153 # Per bank write bursts -system.physmem.perBankRdBursts::1 6286 # Per bank write bursts -system.physmem.perBankRdBursts::2 6219 # Per bank write bursts -system.physmem.perBankRdBursts::3 6279 # Per bank write bursts -system.physmem.perBankRdBursts::4 6331 # Per bank write bursts -system.physmem.perBankRdBursts::5 6377 # Per bank write bursts -system.physmem.perBankRdBursts::6 5798 # Per bank write bursts -system.physmem.perBankRdBursts::7 6202 # Per bank write bursts -system.physmem.perBankRdBursts::8 5707 # Per bank write bursts -system.physmem.perBankRdBursts::9 6391 # Per bank write bursts -system.physmem.perBankRdBursts::10 5673 # Per bank write bursts -system.physmem.perBankRdBursts::11 6223 # Per bank write bursts -system.physmem.perBankRdBursts::12 6101 # Per bank write bursts -system.physmem.perBankRdBursts::13 6086 # Per bank write bursts -system.physmem.perBankRdBursts::14 6643 # Per bank write bursts -system.physmem.perBankRdBursts::15 6167 # Per bank write bursts -system.physmem.perBankWrBursts::0 4924 # Per bank write bursts -system.physmem.perBankWrBursts::1 4781 # Per bank write bursts -system.physmem.perBankWrBursts::2 4796 # Per bank write bursts -system.physmem.perBankWrBursts::3 4885 # Per bank write bursts -system.physmem.perBankWrBursts::4 4841 # Per bank write bursts -system.physmem.perBankWrBursts::5 4959 # Per bank write bursts -system.physmem.perBankWrBursts::6 4374 # Per bank write bursts -system.physmem.perBankWrBursts::7 4731 # Per bank write bursts -system.physmem.perBankWrBursts::8 4283 # Per bank write bursts -system.physmem.perBankWrBursts::9 4855 # Per bank write bursts -system.physmem.perBankWrBursts::10 4375 # Per bank write bursts -system.physmem.perBankWrBursts::11 4455 # Per bank write bursts -system.physmem.perBankWrBursts::12 4488 # Per bank write bursts -system.physmem.perBankWrBursts::13 4484 # Per bank write bursts -system.physmem.perBankWrBursts::14 5021 # Per bank write bursts -system.physmem.perBankWrBursts::15 4566 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 831 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5404 # Per bank write bursts +system.physmem.perBankRdBursts::1 5964 # Per bank write bursts +system.physmem.perBankRdBursts::2 6149 # Per bank write bursts +system.physmem.perBankRdBursts::3 6338 # Per bank write bursts +system.physmem.perBankRdBursts::4 5414 # Per bank write bursts +system.physmem.perBankRdBursts::5 6001 # Per bank write bursts +system.physmem.perBankRdBursts::6 5201 # Per bank write bursts +system.physmem.perBankRdBursts::7 6053 # Per bank write bursts +system.physmem.perBankRdBursts::8 5779 # Per bank write bursts +system.physmem.perBankRdBursts::9 5783 # Per bank write bursts +system.physmem.perBankRdBursts::10 5919 # Per bank write bursts +system.physmem.perBankRdBursts::11 5801 # Per bank write bursts +system.physmem.perBankRdBursts::12 6766 # Per bank write bursts +system.physmem.perBankRdBursts::13 6809 # Per bank write bursts +system.physmem.perBankRdBursts::14 6844 # Per bank write bursts +system.physmem.perBankRdBursts::15 6291 # Per bank write bursts +system.physmem.perBankWrBursts::0 4307 # Per bank write bursts +system.physmem.perBankWrBursts::1 4604 # Per bank write bursts +system.physmem.perBankWrBursts::2 4694 # Per bank write bursts +system.physmem.perBankWrBursts::3 4750 # Per bank write bursts +system.physmem.perBankWrBursts::4 4088 # Per bank write bursts +system.physmem.perBankWrBursts::5 4371 # Per bank write bursts +system.physmem.perBankWrBursts::6 3767 # Per bank write bursts +system.physmem.perBankWrBursts::7 4522 # Per bank write bursts +system.physmem.perBankWrBursts::8 4168 # Per bank write bursts +system.physmem.perBankWrBursts::9 4368 # Per bank write bursts +system.physmem.perBankWrBursts::10 4606 # Per bank write bursts +system.physmem.perBankWrBursts::11 4444 # Per bank write bursts +system.physmem.perBankWrBursts::12 5448 # Per bank write bursts +system.physmem.perBankWrBursts::13 5248 # Per bank write bursts +system.physmem.perBankWrBursts::14 5481 # Per bank write bursts +system.physmem.perBankWrBursts::15 4591 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 5135962999500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5132874544500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98736 # Read request sizes (log2) +system.physmem.readPktSize::6 96612 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 74818 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 76556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 73475 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1759 # 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What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,474 +161,464 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 61 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 371.369637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.870030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 366.414967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7224 31.60% 31.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5292 23.15% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2324 10.16% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1423 6.22% 71.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 882 3.86% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 607 2.65% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 442 1.93% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 389 1.70% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4280 18.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22863 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.004867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 117.614100 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 4100 99.78% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 6 0.15% 99.93% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3261 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.633118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.344584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.042030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13828 38.72% 38.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8395 23.51% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3582 10.03% 72.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1962 5.49% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1409 3.95% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 988 2.77% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 701 1.96% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 566 1.59% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4278 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35709 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4100 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.539756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 117.618727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 4089 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.20% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4109 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.208323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.187975 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.583219 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 44 1.07% 1.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 6 0.15% 1.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 4 0.10% 1.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 4 0.10% 1.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-9 2 0.05% 1.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 4 0.10% 1.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2755 67.05% 68.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 853 20.76% 89.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 55 1.34% 90.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 41 1.00% 91.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 36 0.88% 92.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 45 1.10% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 25 0.61% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 36 0.88% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 20 0.49% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 26 0.63% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 28 0.68% 96.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 10 0.24% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 24 0.58% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 13 0.32% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 21 0.51% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 18 0.44% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 6 0.15% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 4 0.10% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 10 0.24% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 2 0.05% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 4 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 9 0.22% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4109 # Writes before turning the bus around for reads -system.physmem.totQLat 2553947750 # Total ticks spent queuing -system.physmem.totMemAccLat 4444375250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 493180000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1397247500 # Total ticks spent accessing banks -system.physmem.avgQLat 25892.65 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14165.70 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 4100 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4100 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.916341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.808533 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.372443 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 61 1.49% 1.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 8 0.20% 1.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 2 0.05% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 3 0.07% 1.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-9 1 0.02% 1.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10-11 1 0.02% 1.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-13 1 0.02% 1.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 5 0.12% 2.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2769 67.54% 69.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 821 20.02% 89.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 36 0.88% 90.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 38 0.93% 91.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 31 0.76% 92.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 30 0.73% 92.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 54 1.32% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 53 1.29% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 24 0.59% 96.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 28 0.68% 96.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 12 0.29% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 22 0.54% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 34 0.83% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 16 0.39% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 10 0.24% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 6 0.15% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 8 0.20% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 2 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 4 0.10% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 5 0.12% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 2 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 2 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 8 0.20% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4100 # Writes before turning the bus around for reads +system.physmem.totQLat 2438372750 # Total ticks spent queuing +system.physmem.totMemAccLat 4248047750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 482580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25263.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45058.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.23 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44013.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.06 # Average write queue length when enqueuing -system.physmem.readRowHits 80976 # Number of row buffer hits during reads -system.physmem.writeRowHits 55952 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.78 # Row buffer hit rate for writes -system.physmem.avgGap 29592881.75 # Average gap between requests -system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6444852 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 422305 # Transaction distribution -system.membus.trans_dist::ReadResp 422303 # Transaction distribution -system.membus.trans_dist::WriteReq 6370 # Transaction distribution -system.membus.trans_dist::WriteResp 6370 # Transaction distribution -system.membus.trans_dist::Writeback 74818 # Transaction distribution -system.membus.trans_dist::UpgradeReq 747 # Transaction distribution -system.membus.trans_dist::UpgradeResp 747 # Transaction distribution -system.membus.trans_dist::ReadExReq 78043 # Transaction distribution -system.membus.trans_dist::ReadExResp 78043 # Transaction distribution -system.membus.trans_dist::MessageReq 885 # Transaction distribution -system.membus.trans_dist::MessageResp 885 # Transaction distribution +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.46 # Average write queue length when enqueuing +system.physmem.readRowHits 79177 # Number of row buffer hits during reads +system.physmem.writeRowHits 55086 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes +system.physmem.avgGap 30177935.67 # Average gap between requests +system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4939989046000 # Time in different power states +system.physmem.memoryStateTime::REF 171431260000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22454250000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 6437004 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 422289 # Transaction distribution +system.membus.trans_dist::ReadResp 422287 # Transaction distribution +system.membus.trans_dist::WriteReq 6118 # Transaction distribution +system.membus.trans_dist::WriteResp 6118 # Transaction distribution +system.membus.trans_dist::Writeback 73475 # Transaction distribution +system.membus.trans_dist::UpgradeReq 843 # Transaction distribution +system.membus.trans_dist::UpgradeResp 843 # Transaction distribution +system.membus.trans_dist::ReadExReq 76388 # Transaction distribution +system.membus.trans_dist::ReadExResp 76388 # Transaction distribution +system.membus.trans_dist::MessageReq 850 # Transaction distribution +system.membus.trans_dist::MessageResp 850 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 309432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 212160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 204215 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1019134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 66106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 66106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1087010 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158682 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995073 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8391680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9545435 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2715776 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2715776 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12264751 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32837413 # Total data (bytes) -system.membus.snoop_data_through_bus 287680 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 162853500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1010391 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 69253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 69253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1081344 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158115 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995025 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8047552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9200692 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2838016 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2838016 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12042108 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32720690 # Total data (bytes) +system.membus.snoop_data_through_bus 326080 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 162128500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315156500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315102000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1770000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 821391499 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 806327999 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 885000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 850000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1625485201 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1598914090 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 213559749 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 224687998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104632 # number of replacements -system.l2c.tags.tagsinuse 64756.494280 # Cycle average of tags in use -system.l2c.tags.total_refs 3664896 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168700 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.724339 # Average number of references to valid blocks. +system.l2c.tags.replacements 103794 # number of replacements +system.l2c.tags.tagsinuse 64810.608353 # Cycle average of tags in use +system.l2c.tags.total_refs 3657966 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167984 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.775681 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51511.220399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131167 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1228.361726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4265.224240 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 282.161159 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1465.784470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.322385 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.042344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1365.490726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4627.755664 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.785999 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51486.278563 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125055 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1295.377972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4270.696448 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 302.542141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1483.932036 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.824361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1349.140567 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4614.691210 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.785618 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.018743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004305 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022366 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000158 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020836 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070614 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988106 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64068 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2732 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53790 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977600 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33688290 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.065166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.022643 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020586 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.070415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988931 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64190 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3206 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7166 # 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number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22061 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 11617 # number of overall hits -system.l2c.overall_hits::cpu0.inst 344470 # number of overall hits -system.l2c.overall_hits::cpu0.data 593859 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10165 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5243 # number of overall hits -system.l2c.overall_hits::cpu1.inst 139799 # number of overall hits -system.l2c.overall_hits::cpu1.data 255874 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 54188 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10719 # number of overall hits -system.l2c.overall_hits::cpu2.inst 354261 # number of overall hits -system.l2c.overall_hits::cpu2.data 624058 # number of overall hits -system.l2c.overall_hits::total 2426314 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6868 # 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average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56714.310331 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58676.929595 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57833.612239 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59669.871795 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57688.480622 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63887.891920 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60453.779111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59694.875694 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59669.871795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57688.480622 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68904.761905 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63887.891920 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60453.779111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59694.875694 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -776,44 +750,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47572 # number of replacements -system.iocache.tags.tagsinuse 0.107425 # Cycle average of tags in use +system.iocache.tags.replacements 47575 # number of replacements +system.iocache.tags.tagsinuse 0.089403 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000219024509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.107425 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006714 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006714 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000209950509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.089403 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005588 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005588 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428643 # Number of tag accesses -system.iocache.tags.data_accesses 428643 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.tags.tag_accesses 428670 # Number of tag accesses +system.iocache.tags.data_accesses 428670 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses -system.iocache.demand_misses::total 47627 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses -system.iocache.overall_misses::total 47627 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128792785 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128792785 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5668191006 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5668191006 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 5796983791 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5796983791 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 5796983791 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5796983791 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131527041 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131527041 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5824382656 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5824382656 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 5955909697 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5955909697 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 5955909697 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5955909697 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -822,56 +796,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 141998.660419 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 141998.660419 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 121322.581464 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 121322.581464 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121716.332983 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 121716.332983 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121716.332983 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 88529 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144535.209890 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 144535.209890 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 124665.724658 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 124665.724658 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125045.343208 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125045.343208 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 88795 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7334 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8200 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.071039 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.828659 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 744 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 744 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 22928 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 22928 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 23672 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 23672 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 23672 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 23672 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90079785 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90079785 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4474936508 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4474936508 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4565016293 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4565016293 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4565016293 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.820287 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.820287 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.490753 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.490753 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.497029 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.497029 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.497029 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121074.979839 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 121074.979839 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195173.434578 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 195173.434578 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 192844.554453 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 733 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24176 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 24176 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 24909 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 24909 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 24909 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 24909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93385041 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93385041 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4566242660 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4566242660 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4659627701 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4659627701 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.805495 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.805495 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.517466 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.517466 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.522969 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.522969 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127401.147340 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127401.147340 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 188875.027300 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 188875.027300 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -885,476 +859,510 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52329028 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1794981 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1794440 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6370 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6370 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 902417 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 170908 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 147982 # Transaction distribution +system.toL2Bus.throughput 52260442 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1795853 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1795321 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6118 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6118 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 903975 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 804 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 804 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 176511 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 152342 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1004724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3613728 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 35279 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 136436 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4790167 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32150080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119808027 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 127712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 515032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152600851 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268845429 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 114024 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5038805323 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006951 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3618137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34540 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 139444 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4799072 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32221504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120018356 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 123320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 517264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152880444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268161042 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 137520 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5048228823 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2262930320 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2267749080 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4696428413 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4703679799 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19332464 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19140467 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 72173756 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 74891774 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276348 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149977 # Transaction distribution -system.iobus.trans_dist::ReadResp 149977 # Transaction distribution -system.iobus.trans_dist::WriteReq 28411 # Transaction distribution -system.iobus.trans_dist::WriteResp 28411 # Transaction distribution -system.iobus.trans_dist::MessageReq 885 # Transaction distribution -system.iobus.trans_dist::MessageResp 885 # Transaction distribution +system.iobus.throughput 1277477 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 149797 # Transaction distribution +system.iobus.trans_dist::ReadResp 149797 # Transaction distribution +system.iobus.trans_dist::WriteReq 29441 # Transaction distribution +system.iobus.trans_dist::WriteResp 29441 # Transaction distribution +system.iobus.trans_dist::MessageReq 850 # Transaction distribution +system.iobus.trans_dist::MessageResp 850 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5466 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 558 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287032 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287110 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 224 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 309432 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 47344 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 47344 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1770 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1770 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 358546 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 308658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 360176 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3245 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 279 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143516 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143555 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6724 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 158682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1503808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1503808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3540 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3540 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1666030 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6560144 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2116890 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 158115 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1583592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1583592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1745107 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6558405 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2044244 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4753000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4518000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 383000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 367000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 33000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143517000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143556000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 264000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 178000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10048000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9750000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 209101042 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 220209699 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303949000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 303393000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 28759251 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 30099002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 885000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 850000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1144797664 # number of cpu cycles simulated +system.cpu0.numCycles 1160444400 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72999922 # Number of instructions committed -system.cpu0.committedOps 148305710 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 136279674 # Number of integer alu accesses +system.cpu0.committedInsts 72635405 # Number of instructions committed +system.cpu0.committedOps 147758080 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 135731001 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1016299 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14345558 # number of instructions that are conditional controls -system.cpu0.num_int_insts 136279674 # number of integer instructions +system.cpu0.num_func_calls 1010341 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14309822 # number of instructions that are conditional controls +system.cpu0.num_int_insts 135731001 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 250792350 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116890419 # number of times the integer registers were written +system.cpu0.num_int_register_reads 249546871 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116495894 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84577193 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56435831 # number of times the CC registers were written -system.cpu0.num_mem_refs 14370687 # number of memory refs -system.cpu0.num_load_insts 10454117 # Number of load instructions -system.cpu0.num_store_insts 3916570 # Number of store instructions -system.cpu0.num_idle_cycles 1087719763.352511 # Number of idle cycles -system.cpu0.num_busy_cycles 57077900.647489 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049859 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950141 # Percentage of idle cycles -system.cpu0.Branches 15728655 # Number of branches fetched +system.cpu0.num_cc_register_reads 84252648 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56217158 # number of times the CC registers were written +system.cpu0.num_mem_refs 14168966 # number of memory refs +system.cpu0.num_load_insts 10366088 # Number of load instructions +system.cpu0.num_store_insts 3802878 # Number of store instructions +system.cpu0.num_idle_cycles 1101978015.213226 # Number of idle cycles +system.cpu0.num_busy_cycles 58466384.786774 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050383 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949617 # Percentage of idle cycles +system.cpu0.Branches 15683494 # Number of branches fetched +system.cpu0.op_class::No_OpClass 100234 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 133376064 90.27% 90.33% # Class of executed instruction +system.cpu0.op_class::IntMult 62929 0.04% 90.38% # Class of executed instruction +system.cpu0.op_class::IntDiv 50413 0.03% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.41% # Class of executed instruction +system.cpu0.op_class::MemRead 10366088 7.02% 97.43% # Class of executed instruction +system.cpu0.op_class::MemWrite 3802878 2.57% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 147758606 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 853193 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.838528 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129757026 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 853705 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.992815 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147468978000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 295.878537 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 138.959383 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 76.000608 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.577888 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.271405 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.148439 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997732 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 850385 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003982 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.112257 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003862 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003982 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112257 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003862 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11933.084812 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12143.078073 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12079.025728 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11933.084812 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12143.078073 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12079.025728 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11933.084812 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12143.078073 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12079.025728 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1636224 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999323 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19637131 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1636736 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.997739 # 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Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011063 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 243.807235 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 263.156885 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.035294 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.476186 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.513978 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009835 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88232962 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88232962 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5302290 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2343807 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3905907 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11552004 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3762855 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1548346 # 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miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038273 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036160 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.037483 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037598 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.070381 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.067816 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.135217 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093013 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070381 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.067816 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135217 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093013 # 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number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2596900 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4890422 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13240104 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3798594 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1694395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2905116 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8398105 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9551376 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4291295 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7795538 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21638209 # 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average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10881.588659 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34858.390247 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30079.869474 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17222.814847 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18717.945559 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17655.422797 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11868.668449 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18717.945559 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17655.422797 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11868.668449 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 173678 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11795 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11797 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.272319 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.722218 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1545523 # number of writebacks -system.cpu0.dcache.writebacks::total 1545523 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 357871 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 357871 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17395 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 17395 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 375266 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 375266 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 375266 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 375266 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 225063 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 578353 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 803416 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 58088 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90563 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 148651 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 283151 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 668916 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 952067 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 283151 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 668916 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 952067 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2737161496 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8309689554 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11046851050 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1998659220 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2996226317 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4994885537 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4735820716 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11305915871 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16041736587 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4735820716 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11305915871 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16041736587 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30467694000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33225580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63693274500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 404660000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 790542000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1195202000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30872354000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34016122500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64888476500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087612 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119442 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060636 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036160 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031444 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017698 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067816 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086622 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.043977 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067816 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086622 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.043977 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12161.756913 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14367.850697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13749.851945 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34407.437336 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33084.441958 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33601.425735 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16725.424653 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16901.846975 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16849.377814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16725.424653 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16901.846975 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16849.377814 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1542066 # number of writebacks +system.cpu0.dcache.writebacks::total 1542066 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 371761 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 371761 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17373 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17373 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 389134 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 389134 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 389134 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 389134 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 223619 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 577178 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 800797 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62158 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90935 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 153093 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 285777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 668113 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 953890 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 285777 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 668113 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 953890 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2734176493 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8368429033 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11102605526 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032053179 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2876927496 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4908980675 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4766229672 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11245356529 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16011586201 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4766229672 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11245356529 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16011586201 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30475246000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33186567000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63661813000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 395642000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 753351500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1148993500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30870888000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33939918500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64810806500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086110 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118022 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036684 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031302 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.044084 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044084 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12226.941776 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14498.870423 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13864.444455 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32691.740066 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31637.185858 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32065.350310 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1365,307 +1373,377 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608015730 # number of cpu cycles simulated +system.cpu1.numCycles 2606021866 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34716890 # Number of instructions committed -system.cpu1.committedOps 67541836 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62669042 # Number of integer alu accesses +system.cpu1.committedInsts 34914128 # Number of instructions committed +system.cpu1.committedOps 67869824 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62995293 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 430919 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6413966 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62669042 # number of integer instructions +system.cpu1.num_func_calls 438942 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62995293 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 115548964 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54160900 # number of times the integer registers were written +system.cpu1.num_int_register_reads 116271698 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54373004 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35562537 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26614034 # number of times the CC registers were written -system.cpu1.num_mem_refs 4364452 # number of memory refs -system.cpu1.num_load_insts 2756893 # Number of load instructions -system.cpu1.num_store_insts 1607559 # Number of store instructions -system.cpu1.num_idle_cycles 2483429860.768801 # Number of idle cycles -system.cpu1.num_busy_cycles 124585869.231199 # Number of busy cycles -system.cpu1.not_idle_fraction 0.047770 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.952230 # Percentage of idle cycles -system.cpu1.Branches 7003911 # Number of branches fetched +system.cpu1.num_cc_register_reads 35773637 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26686134 # number of times the CC registers were written +system.cpu1.num_mem_refs 4480510 # number of memory refs +system.cpu1.num_load_insts 2784988 # Number of load instructions +system.cpu1.num_store_insts 1695522 # Number of store instructions +system.cpu1.num_idle_cycles 2483027078.364504 # Number of idle cycles +system.cpu1.num_busy_cycles 122994787.635496 # Number of busy cycles +system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles +system.cpu1.Branches 7029914 # Number of branches fetched +system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 63308001 93.28% 93.32% # Class of executed instruction +system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction +system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction +system.cpu1.op_class::MemRead 2784988 4.10% 97.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 1695522 2.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 67870139 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28782114 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28782114 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 316524 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26348266 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25752004 # Number of BTB hits +system.cpu2.branchPred.lookups 28758894 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28758894 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 306803 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26351534 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25737629 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.736997 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 537542 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63717 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155552038 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.670325 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 530881 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 61512 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154845080 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9686701 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141772190 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28782114 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26289546 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54340809 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1470890 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 70055 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24627328 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7901 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 23768 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 376 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3150040 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 144648 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2015 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 89899907 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.110146 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.408280 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9460785 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 141747704 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28758894 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26268510 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54302787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1434244 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 58972 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 24471854 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6545 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 20028 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3117082 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 139514 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1749 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 89437217 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.124405 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.409858 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 35694732 39.70% 39.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 594255 0.66% 40.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23712499 26.38% 66.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 314699 0.35% 67.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 599600 0.67% 67.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 812421 0.90% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 338881 0.38% 69.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 517837 0.58% 69.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27314983 30.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 35270123 39.44% 39.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 589507 0.66% 40.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23704151 26.50% 66.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 307246 0.34% 66.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 603965 0.68% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 802586 0.90% 68.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 334965 0.37% 68.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 517417 0.58% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27307257 30.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 89899907 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185032 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.911413 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 11154829 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23540580 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 30801007 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1287318 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1141583 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278785410 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1141583 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12143079 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13933433 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4524497 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 30930733 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5252059 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277791777 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7238 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2464468 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2117220 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 331976691 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 604531856 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371338716 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321781805 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10194886 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 148461 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 149473 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11392573 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6171654 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3395563 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 345995 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 292325 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276091246 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 414813 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274477250 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 60541 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7173454 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11041443 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 56132 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 89899907 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.053143 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.400877 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 89437217 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185727 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.915416 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10926187 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 23367960 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 31523393 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1298286 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1115198 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278635226 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 49 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1115198 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11921655 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13834152 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4411879 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 31656208 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5292001 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277656292 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6764 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2483668 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2130930 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 331880087 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 604361998 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371268132 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 6 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321920244 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9959841 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 147988 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 148926 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11485411 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6218482 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3410117 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 341148 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 274139 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276004640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 412430 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274449569 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 59781 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7023554 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10820295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 55045 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 89437217 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.068628 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.396853 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26563563 29.55% 29.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6130901 6.82% 36.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3934206 4.38% 40.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2710119 3.01% 43.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25036419 27.85% 71.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1342117 1.49% 73.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23840310 26.52% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 288717 0.32% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 53555 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 26098480 29.18% 29.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6131096 6.86% 36.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3936751 4.40% 40.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2730796 3.05% 43.49% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25025448 27.98% 71.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1337810 1.50% 72.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23830586 26.65% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 291775 0.33% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 54475 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 89899907 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 89437217 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 122290 33.50% 33.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 245 0.07% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 189949 52.03% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 52573 14.40% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 125312 33.75% 33.75% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 120 0.03% 33.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 109 0.03% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 191005 51.44% 85.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 54802 14.76% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 80536 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264658650 96.42% 96.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54855 0.02% 96.47% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48402 0.02% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6455691 2.35% 98.84% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3179116 1.16% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 76601 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264560846 96.40% 96.42% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54414 0.02% 96.44% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50942 0.02% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6508971 2.37% 98.83% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3197795 1.17% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274477250 # Type of FU issued -system.cpu2.iq.rate 1.764537 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 365057 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001330 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 639321511 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 283683445 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273115126 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274761742 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 634301 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274449569 # Type of FU issued +system.cpu2.iq.rate 1.772414 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 371348 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001353 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 638809448 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 283444416 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273102485 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 12 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274744310 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 6 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 641561 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1002623 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6718 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4440 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 510444 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 993516 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6753 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4280 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 500329 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656391 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10280 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656426 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10045 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1141583 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9227965 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 815382 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276506059 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 71664 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6171654 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3395563 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 234992 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 633068 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3849 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4440 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 176570 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 182317 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 358887 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273973436 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6342946 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 503814 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1115198 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9119918 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 823405 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276417070 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 70631 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6218482 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3410117 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 233790 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 637954 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3900 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4280 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 173413 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 173644 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347057 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273959168 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6398525 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 490400 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9455734 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27867681 # Number of branches executed -system.cpu2.iew.exec_stores 3112788 # Number of stores executed -system.cpu2.iew.exec_rate 1.761298 # Inst execution rate -system.cpu2.iew.wb_sent 273823666 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273115144 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212986974 # num instructions producing a value -system.cpu2.iew.wb_consumers 348231532 # num instructions consuming a value +system.cpu2.iew.exec_refs 9531292 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27864904 # Number of branches executed +system.cpu2.iew.exec_stores 3132767 # Number of stores executed +system.cpu2.iew.exec_rate 1.769247 # Inst execution rate +system.cpu2.iew.wb_sent 273810478 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273102491 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212979431 # num instructions producing a value +system.cpu2.iew.wb_consumers 348314367 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.755780 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611625 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.763714 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611457 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7474898 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 358681 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 318992 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 88758324 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.031021 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870805 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7316358 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357385 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 309115 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 88322018 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.046767 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.870309 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 31301057 35.27% 35.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4393147 4.95% 40.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1229186 1.38% 41.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24655081 27.78% 69.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 868070 0.98% 70.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 585819 0.66% 71.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 347474 0.39% 71.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302544 26.25% 97.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2075946 2.34% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30852434 34.93% 34.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4395307 4.98% 39.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1238857 1.40% 41.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24650858 27.91% 69.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 865215 0.98% 70.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 585749 0.66% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 347954 0.39% 71.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23291491 26.37% 97.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2094153 2.37% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 88758324 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136214259 # Number of instructions committed -system.cpu2.commit.committedOps 269028357 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 88322018 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136303075 # Number of instructions committed +system.cpu2.commit.committedOps 269096585 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8054150 # Number of memory references committed -system.cpu2.commit.loads 5169031 # Number of loads committed -system.cpu2.commit.membars 165004 # Number of memory barriers committed -system.cpu2.commit.branches 27530478 # Number of branches committed +system.cpu2.commit.refs 8134753 # Number of memory references committed +system.cpu2.commit.loads 5224965 # Number of loads committed +system.cpu2.commit.membars 164376 # Number of memory barriers committed +system.cpu2.commit.branches 27532187 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245624895 # Number of committed integer instructions. -system.cpu2.commit.function_calls 430032 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2075946 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 245708361 # Number of committed integer instructions. +system.cpu2.commit.function_calls 429087 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 43848 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 260815603 96.92% 96.94% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52558 0.02% 96.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 49823 0.02% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.98% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5224965 1.94% 98.92% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2909788 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 269096585 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2094153 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 363157720 # The number of ROB reads -system.cpu2.rob.rob_writes 554152180 # The number of ROB writes -system.cpu2.timesIdled 477715 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65652131 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4906975665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136214259 # Number of Instructions Simulated -system.cpu2.committedOps 269028357 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136214259 # Number of Instructions Simulated -system.cpu2.cpi 1.141966 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.141966 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.875683 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.875683 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364409735 # number of integer regfile reads -system.cpu2.int_regfile_writes 218808578 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73042 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139320542 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107246688 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88724841 # number of misc regfile reads -system.cpu2.misc_regfile_writes 132896 # number of misc regfile writes +system.cpu2.rob.rob_reads 362613065 # The number of ROB reads +system.cpu2.rob.rob_writes 553944877 # The number of ROB writes +system.cpu2.timesIdled 473034 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65407863 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4900873955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136303075 # Number of Instructions Simulated +system.cpu2.committedOps 269096585 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136303075 # Number of Instructions Simulated +system.cpu2.cpi 1.136035 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.136035 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.880254 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.880254 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364552649 # number of integer regfile reads +system.cpu2.int_regfile_writes 218803003 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72918 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 139316304 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107298284 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88761943 # number of misc regfile reads +system.cpu2.misc_regfile_writes 132629 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |