diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
9 files changed, 2758 insertions, 2724 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 04fd84fb1..1ab0a28be 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,13 +20,14 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 +load_offset=0 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -161,6 +162,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -1535,7 +1537,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1558,7 +1560,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1747,9 +1749,9 @@ system=system pio=system.iobus.master[9] [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1760,27 +1762,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[3] [system.smbios_table] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 4c2ae2163..86995b769 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 22:15:55 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:16:40 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5133933067000 because m5_exit instruction encountered +Exiting @ tick 5137926173000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 4f3c9bdb3..aa05e00b0 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.141960 # Number of seconds simulated -sim_ticks 5141959613000 # Number of ticks simulated -final_tick 5141959613000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137926 # Number of seconds simulated +sim_ticks 5137926173000 # Number of ticks simulated +final_tick 5137926173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152486 # Simulator instruction rate (inst/s) -host_op_rate 301416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1922658876 # Simulator tick rate (ticks/s) -host_mem_usage 770128 # Number of bytes of host memory used -host_seconds 2674.40 # Real time elapsed on the host -sim_insts 407807707 # Number of instructions simulated -sim_ops 806107146 # Number of ops (including micro ops) simulated +host_inst_rate 165389 # Simulator instruction rate (inst/s) +host_op_rate 326926 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2083966500 # Simulator tick rate (ticks/s) +host_mem_usage 742788 # Number of bytes of host memory used +host_seconds 2465.46 # Real time elapsed on the host +sim_insts 407759509 # Number of instructions simulated +sim_ops 806020953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2476992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 2427584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1035072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10749056 # Number of bytes read from this memory -system.physmem.bytes_read::total 14265280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1035072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1035072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9521344 # Number of bytes written to this memory -system.physmem.bytes_written::total 9521344 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1035776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10808512 # Number of bytes read from this memory +system.physmem.bytes_read::total 14275968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1035776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1035776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9555328 # Number of bytes written to this memory +system.physmem.bytes_written::total 9555328 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16173 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167954 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222895 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148771 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148771 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 747 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168883 # Number of read requests responded to by this memory +system.physmem.num_reads::total 223062 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149302 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149302 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 472483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 735 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2090459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2774289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1851696 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1851696 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1851696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2103672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2778547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1859764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1859764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1859764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 472483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2090459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4625984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222895 # Number of read requests accepted -system.physmem.writeReqs 148771 # Number of write requests accepted -system.physmem.readBursts 222895 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148771 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14256576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 9520064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14265280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9521344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 201594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2103672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4638310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 223062 # Number of read requests accepted +system.physmem.writeReqs 149302 # Number of write requests accepted +system.physmem.readBursts 223062 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149302 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14267968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue +system.physmem.bytesWritten 9553728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14275968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9555328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1680 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14406 # Per bank write bursts -system.physmem.perBankRdBursts::1 13692 # Per bank write bursts -system.physmem.perBankRdBursts::2 14137 # Per bank write bursts -system.physmem.perBankRdBursts::3 13444 # Per bank write bursts -system.physmem.perBankRdBursts::4 14027 # Per bank write bursts -system.physmem.perBankRdBursts::5 13372 # Per bank write bursts -system.physmem.perBankRdBursts::6 13359 # Per bank write bursts -system.physmem.perBankRdBursts::7 13805 # Per bank write bursts -system.physmem.perBankRdBursts::8 13762 # Per bank write bursts -system.physmem.perBankRdBursts::9 13592 # Per bank write bursts -system.physmem.perBankRdBursts::10 13956 # Per bank write bursts -system.physmem.perBankRdBursts::11 13564 # Per bank write bursts -system.physmem.perBankRdBursts::12 14528 # Per bank write bursts -system.physmem.perBankRdBursts::13 14698 # Per bank write bursts -system.physmem.perBankRdBursts::14 14291 # Per bank write bursts -system.physmem.perBankRdBursts::15 14126 # Per bank write bursts -system.physmem.perBankWrBursts::0 9807 # Per bank write bursts -system.physmem.perBankWrBursts::1 9166 # Per bank write bursts -system.physmem.perBankWrBursts::2 9421 # Per bank write bursts -system.physmem.perBankWrBursts::3 8835 # Per bank write bursts -system.physmem.perBankWrBursts::4 9422 # Per bank write bursts -system.physmem.perBankWrBursts::5 8917 # Per bank write bursts -system.physmem.perBankWrBursts::6 8763 # Per bank write bursts -system.physmem.perBankWrBursts::7 9221 # Per bank write bursts -system.physmem.perBankWrBursts::8 9116 # Per bank write bursts -system.physmem.perBankWrBursts::9 9134 # Per bank write bursts -system.physmem.perBankWrBursts::10 9470 # Per bank write bursts -system.physmem.perBankWrBursts::11 8904 # Per bank write bursts -system.physmem.perBankWrBursts::12 9718 # Per bank write bursts -system.physmem.perBankWrBursts::13 9806 # Per bank write bursts -system.physmem.perBankWrBursts::14 9580 # Per bank write bursts -system.physmem.perBankWrBursts::15 9471 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1775 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14642 # Per bank write bursts +system.physmem.perBankRdBursts::1 13963 # Per bank write bursts +system.physmem.perBankRdBursts::2 14587 # Per bank write bursts +system.physmem.perBankRdBursts::3 13341 # Per bank write bursts +system.physmem.perBankRdBursts::4 14143 # Per bank write bursts +system.physmem.perBankRdBursts::5 13526 # Per bank write bursts +system.physmem.perBankRdBursts::6 13007 # Per bank write bursts +system.physmem.perBankRdBursts::7 13123 # Per bank write bursts +system.physmem.perBankRdBursts::8 13660 # Per bank write bursts +system.physmem.perBankRdBursts::9 13743 # Per bank write bursts +system.physmem.perBankRdBursts::10 13657 # Per bank write bursts +system.physmem.perBankRdBursts::11 13667 # Per bank write bursts +system.physmem.perBankRdBursts::12 14668 # Per bank write bursts +system.physmem.perBankRdBursts::13 14755 # Per bank write bursts +system.physmem.perBankRdBursts::14 14289 # Per bank write bursts +system.physmem.perBankRdBursts::15 14166 # Per bank write bursts +system.physmem.perBankWrBursts::0 10056 # Per bank write bursts +system.physmem.perBankWrBursts::1 9321 # Per bank write bursts +system.physmem.perBankWrBursts::2 9829 # Per bank write bursts +system.physmem.perBankWrBursts::3 8830 # Per bank write bursts +system.physmem.perBankWrBursts::4 9558 # Per bank write bursts +system.physmem.perBankWrBursts::5 8986 # Per bank write bursts +system.physmem.perBankWrBursts::6 8593 # Per bank write bursts +system.physmem.perBankWrBursts::7 8747 # Per bank write bursts +system.physmem.perBankWrBursts::8 8969 # Per bank write bursts +system.physmem.perBankWrBursts::9 9193 # Per bank write bursts +system.physmem.perBankWrBursts::10 9160 # Per bank write bursts +system.physmem.perBankWrBursts::11 9087 # Per bank write bursts +system.physmem.perBankWrBursts::12 9894 # Per bank write bursts +system.physmem.perBankWrBursts::13 9881 # Per bank write bursts +system.physmem.perBankWrBursts::14 9649 # Per bank write bursts +system.physmem.perBankWrBursts::15 9524 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5141959559500 # Total gap between requests +system.physmem.totGap 5137926057000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222895 # Read request sizes (log2) +system.physmem.readPktSize::6 223062 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148771 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 173187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 376 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149302 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 173856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 347 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -156,223 +156,225 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 9176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1335 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.776409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.138812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.199277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28275 37.91% 37.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16828 22.56% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7503 10.06% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4244 5.69% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3057 4.10% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2068 2.77% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1382 1.85% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1175 1.58% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10055 13.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74587 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8285 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.884007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 527.034010 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 8284 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 75897 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.867900 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.633012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.529129 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 29529 38.91% 38.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16915 22.29% 61.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7566 9.97% 71.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4259 5.61% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2981 3.93% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2008 2.65% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1459 1.92% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1171 1.54% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10009 13.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75897 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.835320 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 526.600201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 8306 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8285 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8285 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.954255 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.428609 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.676130 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 6158 74.33% 74.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1338 16.15% 90.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 52 0.63% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 77 0.93% 92.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 47 0.57% 92.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 55 0.66% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 103 1.24% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 89 1.07% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 47 0.57% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 58 0.70% 96.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 37 0.45% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 45 0.54% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 69 0.83% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 27 0.33% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 11 0.13% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 16 0.19% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 22 0.27% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 4 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 7 0.08% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 2 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 5 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 4 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-89 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8285 # Writes before turning the bus around for reads -system.physmem.totQLat 4923822749 # Total ticks spent queuing -system.physmem.totMemAccLat 9100553999 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1113795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22103.81 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 8307 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.970025 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.437156 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.734930 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 6174 74.32% 74.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1334 16.06% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 66 0.79% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 64 0.77% 91.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 51 0.61% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 45 0.54% 93.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 113 1.36% 94.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 87 1.05% 95.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 56 0.67% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 56 0.67% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 34 0.41% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 52 0.63% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 60 0.72% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 31 0.37% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 10 0.12% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 10 0.12% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 28 0.34% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 7 0.08% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 4 0.05% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 3 0.04% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 5 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 4 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 2 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 3 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 2 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 2 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::90-91 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8307 # Writes before turning the bus around for reads +system.physmem.totQLat 4966355250 # Total ticks spent queuing +system.physmem.totMemAccLat 9146424000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1114685000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22276.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40853.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41026.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing -system.physmem.readRowHits 186870 # Number of row buffer hits during reads -system.physmem.writeRowHits 110052 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.97 # Row buffer hit rate for writes -system.physmem.avgGap 13834893.59 # Average gap between requests -system.physmem.pageHitRate 79.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4934274417750 # Time in different power states -system.physmem.memoryStateTime::REF 171701140000 # Time in different power states +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.93 # Average write queue length when enqueuing +system.physmem.readRowHits 185691 # Number of row buffer hits during reads +system.physmem.writeRowHits 110625 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.09 # Row buffer hit rate for writes +system.physmem.avgGap 13798127.79 # Average gap between requests +system.physmem.pageHitRate 79.60 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4930575819000 # Time in different power states +system.physmem.memoryStateTime::REF 171566460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35983950250 # Time in different power states +system.physmem.memoryStateTime::ACT 35783789000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 5095093 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662466 # Transaction distribution -system.membus.trans_dist::ReadResp 662464 # Transaction distribution -system.membus.trans_dist::WriteReq 13782 # Transaction distribution -system.membus.trans_dist::WriteResp 13782 # Transaction distribution -system.membus.trans_dist::Writeback 148771 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution -system.membus.trans_dist::ReadExReq 179320 # Transaction distribution -system.membus.trans_dist::ReadExResp 179319 # Transaction distribution -system.membus.trans_dist::MessageReq 1645 # Transaction distribution -system.membus.trans_dist::MessageResp 1645 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475021 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721191 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1857477 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550161 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20114933 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5463680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5463680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25585193 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25585193 # Total data (bytes) -system.membus.snoop_data_through_bus 613568 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250592000 # Layer occupancy (ticks) +system.membus.throughput 5117506 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662560 # Transaction distribution +system.membus.trans_dist::ReadResp 662552 # Transaction distribution +system.membus.trans_dist::WriteReq 13764 # Transaction distribution +system.membus.trans_dist::WriteResp 13764 # Transaction distribution +system.membus.trans_dist::Writeback 149302 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2261 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1794 # Transaction distribution +system.membus.trans_dist::ReadExReq 180173 # Transaction distribution +system.membus.trans_dist::ReadExResp 180170 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132228 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132228 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1859247 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241801 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18417024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20208974 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5414272 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5414272 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25629818 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25629818 # Total data (bytes) +system.membus.snoop_data_through_bus 663552 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250523000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583283000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583102000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1610033997 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1620731000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3152758703 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3164060842 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429601748 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429649499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47571 # number of replacements -system.iocache.tags.tagsinuse 0.128712 # Cycle average of tags in use +system.iocache.tags.replacements 47575 # number of replacements +system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992977133000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128712 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008045 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.008045 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992948576000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428634 # Number of tag accesses -system.iocache.tags.data_accesses 428634 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses -system.iocache.ReadReq_misses::total 906 # number of ReadReq misses +system.iocache.tags.tag_accesses 428670 # Number of tag accesses +system.iocache.tags.data_accesses 428670 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses -system.iocache.demand_misses::total 47626 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses -system.iocache.overall_misses::total 47626 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147491196 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 147491196 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11109159898 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11109159898 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11256651094 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11256651094 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11256651094 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11256651094 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151620185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151620185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11039278588 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11039278588 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11190898773 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11190898773 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11190898773 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11190898773 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -381,40 +383,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162793.814570 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162793.814570 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 237781.675899 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 237781.675899 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 236355.165120 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 236355.165120 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 236355.165120 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 159859 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166615.587912 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166615.587912 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 236285.928682 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 236285.928682 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 234954.834621 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 234954.834621 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 159238 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 14672 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14593 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.895515 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.911944 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100353196 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100353196 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8677810402 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8677810402 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8778163598 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8778163598 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8778163598 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104274685 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104274685 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8607905090 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8607905090 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8712179775 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8712179775 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -423,18 +425,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110765.116998 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110765.116998 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 185740.804837 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 185740.804837 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 184314.525637 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 184314.525637 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114587.565934 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114587.565934 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 184244.543878 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 184244.543878 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -444,22 +446,22 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 637150 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225562 # Transaction distribution -system.iobus.trans_dist::ReadResp 225562 # Transaction distribution -system.iobus.trans_dist::WriteReq 57606 # Transaction distribution -system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1645 # Transaction distribution -system.iobus.trans_dist::MessageResp 1645 # Transaction distribution +system.iobus.throughput 637650 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225557 # Transaction distribution +system.iobus.trans_dist::ReadResp 225557 # Transaction distribution +system.iobus.trans_dist::WriteReq 57591 # Transaction distribution +system.iobus.trans_dist::WriteResp 57591 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427354 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -469,21 +471,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569626 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569582 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213677 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -493,20 +495,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276200 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276200 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3930346 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241801 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276197 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3919904 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -518,7 +520,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 213678000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -536,273 +538,274 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424685346 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424855274 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460165000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53671252 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53596501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85633263 # Number of BP lookups -system.cpu.branchPred.condPredicted 85633263 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 884686 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79267379 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77548662 # Number of BTB hits +system.cpu.branchPred.lookups 85854110 # Number of BP lookups +system.cpu.branchPred.condPredicted 85854110 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 890492 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79431123 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77651636 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.831747 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440338 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180105 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.759711 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1460640 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181048 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 453234333 # number of cpu cycles simulated +system.cpu.numCycles 452853570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25483623 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422835891 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85633263 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78989000 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162683938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4002747 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 108573 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 70983982 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43526 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92374 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8487571 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 384793 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2466 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262469836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.181706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411661 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25683785 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 423946474 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85854110 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79112276 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162997927 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4233083 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 105681 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 69250991 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42777 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 91487 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 266 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8611652 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 409614 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2534 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 261469410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.201181 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.413215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100201994 38.18% 38.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1531970 0.58% 38.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71824716 27.36% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 909581 0.35% 66.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1572022 0.60% 67.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2391233 0.91% 67.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1015593 0.39% 68.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1327813 0.51% 68.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81694914 31.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98890192 37.82% 37.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1558006 0.60% 38.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71842115 27.48% 65.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 921619 0.35% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1585920 0.61% 66.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2431144 0.93% 67.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1036910 0.40% 68.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1345104 0.51% 68.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81858400 31.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262469836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188938 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.932930 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29410093 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68121182 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158520657 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3344277 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3073627 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832752013 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3073627 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32108860 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42947155 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12423337 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158815296 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13101561 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829828808 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20476 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6069323 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5155919 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991491995 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800757525 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1107104494 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964043985 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27448008 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 454148 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 459927 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29603104 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16744391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9834089 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1098610 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 922271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825029586 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184674 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 821050392 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 152353 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19282759 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29404306 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 129800 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262469836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.128170 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399623 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 261469410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.189585 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.936167 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29046589 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 66961601 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159616384 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2548340 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3296496 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 834624632 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3296496 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31320829 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 35759496 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12826241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159575235 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 18691113 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 831621243 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 271968 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7201596 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 103405 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 9490411 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 993545092 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1805477878 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1109904628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 111 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963933701 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 29611389 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 457228 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 464601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 24223020 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16966534 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9968316 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1221781 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 988150 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 826572087 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1194475 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 821819105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 208862 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20915933 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32275833 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 139879 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 261469410 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.143079 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.407689 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76068971 28.98% 28.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15764450 6.01% 34.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10561557 4.02% 39.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7380977 2.81% 41.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75732754 28.85% 70.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3744713 1.43% 72.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72297753 27.55% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 770490 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 148171 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76437702 29.23% 29.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14614697 5.59% 34.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10065724 3.85% 38.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7027094 2.69% 41.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75658650 28.94% 70.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3979218 1.52% 71.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72575299 27.76% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 879014 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 232012 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262469836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 261469410 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 351121 33.32% 33.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 242 0.02% 33.34% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 235 0.02% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548827 52.08% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153397 14.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 395534 35.48% 35.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 246 0.02% 35.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 260 0.02% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 578947 51.93% 87.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 139812 12.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 310274 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793553745 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150127 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124319 0.02% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17682976 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9228951 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 313841 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 794169455 96.64% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150148 0.02% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125336 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17790783 2.16% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9269542 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 821050392 # Type of FU issued -system.cpu.iq.rate 1.811536 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1053822 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905885622 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845507474 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817131376 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 174 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 198 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 821819105 # Type of FU issued +system.cpu.iq.rate 1.814757 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1114799 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001357 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906543911 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 848693742 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817833447 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 176 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821793858 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 822619981 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1694774 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1787791 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2743773 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18703 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12097 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1404751 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2974113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13012 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1545780 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931902 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12205 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1935112 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35450 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3073627 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31062869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2159597 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826214260 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 248339 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16744391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9834089 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620816 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13300 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12097 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498594 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 510068 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1008662 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819639552 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17378500 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1410839 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3296496 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15966541 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12762115 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 827766562 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 204474 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16966534 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9968316 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 698992 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1766485 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10560079 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13012 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 503157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 519909 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1023066 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 820377360 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17471183 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1441744 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26423310 # number of memory reference insts executed -system.cpu.iew.exec_branches 83104184 # Number of branches executed -system.cpu.iew.exec_stores 9044810 # Number of stores executed -system.cpu.iew.exec_rate 1.808423 # Inst execution rate -system.cpu.iew.wb_sent 819235043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817131426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638623234 # num instructions producing a value -system.cpu.iew.wb_consumers 1043962608 # num instructions consuming a value +system.cpu.iew.exec_refs 26545601 # number of memory reference insts executed +system.cpu.iew.exec_branches 83164783 # Number of branches executed +system.cpu.iew.exec_stores 9074418 # Number of stores executed +system.cpu.iew.exec_rate 1.811573 # Inst execution rate +system.cpu.iew.wb_sent 819943769 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817833497 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640559141 # num instructions producing a value +system.cpu.iew.wb_consumers 1047723157 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.805956 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611382 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19998130 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054874 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 894775 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259396209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.107629 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863349 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21640086 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054596 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 900184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258172914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.122020 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.868515 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87828444 33.86% 33.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11868241 4.58% 38.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3842531 1.48% 39.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74752258 28.82% 68.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2384729 0.92% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1479281 0.57% 70.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 859408 0.33% 70.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70845236 27.31% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5536081 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87519981 33.90% 33.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11178946 4.33% 38.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3524931 1.37% 39.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74556840 28.88% 68.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2487891 0.96% 69.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1503617 0.58% 70.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865491 0.34% 70.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70822706 27.43% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5712511 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259396209 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407807707 # Number of instructions committed -system.cpu.commit.committedOps 806107146 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 258172914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407759509 # Number of instructions committed +system.cpu.commit.committedOps 806020953 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22429955 # Number of memory references committed -system.cpu.commit.loads 14000617 # Number of loads committed -system.cpu.commit.membars 474711 # Number of memory barriers committed -system.cpu.commit.branches 82167469 # Number of branches committed +system.cpu.commit.refs 22414956 # Number of memory references committed +system.cpu.commit.loads 13992420 # Number of loads committed +system.cpu.commit.membars 474659 # Number of memory barriers committed +system.cpu.commit.branches 82156165 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734952495 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155627 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174437 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783236239 97.16% 97.18% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144862 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121653 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734866809 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155346 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174342 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783165220 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144784 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121651 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -829,213 +832,213 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 14000617 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8429338 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13992420 1.74% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8422536 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806107146 # Class of committed instruction -system.cpu.commit.bw_lim_events 5536081 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806020953 # Class of committed instruction +system.cpu.commit.bw_lim_events 5712511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079887016 # The number of ROB reads -system.cpu.rob.rob_writes 1655298855 # The number of ROB writes -system.cpu.timesIdled 1259672 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190764497 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9830690598 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407807707 # Number of Instructions Simulated -system.cpu.committedOps 806107146 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.111392 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111392 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088844162 # number of integer regfile reads -system.cpu.int_regfile_writes 653876789 # number of integer regfile writes +system.cpu.rob.rob_reads 1080043164 # The number of ROB reads +system.cpu.rob.rob_writes 1658634797 # The number of ROB writes +system.cpu.timesIdled 1275471 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191384160 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9823003775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407759509 # Number of Instructions Simulated +system.cpu.committedOps 806020953 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.110590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.110590 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.900422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1089597141 # number of integer regfile reads +system.cpu.int_regfile_writes 654482969 # number of integer regfile writes system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.cc_regfile_reads 415644137 # number of cc regfile reads -system.cpu.cc_regfile_writes 321521730 # number of cc regfile writes -system.cpu.misc_regfile_reads 264115519 # number of misc regfile reads -system.cpu.misc_regfile_writes 402672 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53624827 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3015737 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3015197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13782 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13782 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1584798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 336401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 289692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6128379 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8215578 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61059136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207801717 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 607680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5615104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 275083637 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 275059381 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 677312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4044441846 # Layer occupancy (ticks) +system.cpu.cc_regfile_reads 415870022 # number of cc regfile reads +system.cpu.cc_regfile_writes 321677512 # number of cc regfile writes +system.cpu.misc_regfile_reads 264445635 # number of misc regfile reads +system.cpu.misc_regfile_writes 402422 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53724216 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3026047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3025482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1581183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 156212 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8229172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61697728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207710542 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 574144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5436928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 275419342 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 275396046 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 635008 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4043112921 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 568500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 546000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1434613560 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1449735220 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141764506 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3140330868 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14738244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14620748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 107967138 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 106945143 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 953583 # number of replacements -system.cpu.icache.tags.tagsinuse 509.342760 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7479724 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 954095 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.839601 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147639960250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.342760 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994810 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994810 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 963566 # number of replacements +system.cpu.icache.tags.tagsinuse 509.311037 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7590970 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 964078 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.873813 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147613206250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.311037 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994748 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994748 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 177 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9441724 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9441724 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7479724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7479724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7479724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7479724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7479724 # number of overall hits -system.cpu.icache.overall_hits::total 7479724 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1007844 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1007844 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1007844 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1007844 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1007844 # number of overall misses -system.cpu.icache.overall_misses::total 1007844 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14035582232 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14035582232 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14035582232 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14035582232 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14035582232 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14035582232 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8487568 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8487568 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8487568 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8487568 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8487568 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8487568 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118744 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118744 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118744 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118744 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118744 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118744 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13926.343990 # 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number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 964196 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 964196 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 964196 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 964196 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 964196 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 964196 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11690907021 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11690907021 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11690907021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11690907021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11690907021 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11690907021 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.111964 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.111964 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111964 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.111964 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12125.031654 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12125.031654 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8939 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.031288 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 21114 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8953 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.358316 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104803925000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031288 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376956 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376956 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 71741 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 71741 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21134 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21134 # 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Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 68718 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 68718 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 19738 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 19738 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21136 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21136 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21136 # 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number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 107949749 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 107949749 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30957 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30957 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 19740 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 19740 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 19740 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 19740 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9746 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9746 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9746 # 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number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 29484 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30959 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30959 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30959 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30959 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.317311 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.317311 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.317291 # 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number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 29486 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29486 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 29486 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.330552 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.330552 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.330530 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.330530 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.330530 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.330530 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10870.690437 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10870.690437 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10870.690437 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10870.690437 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1044,85 +1047,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1983 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1983 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88296261 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 88296261 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 88296261 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 88296261 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 88296261 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 88296261 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.317311 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.317311 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.317291 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.317291 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.317291 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8988.726560 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8988.726560 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8988.726560 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1636 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1636 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9746 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9746 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9746 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9746 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9746 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9746 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86450253 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86450253 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86450253 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86450253 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86450253 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86450253 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.330552 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.330552 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.330530 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.330530 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8870.331726 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 70861 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 12.940736 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 90199 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 70877 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.272613 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101635052500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 12.940736 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.808796 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.808796 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 70197 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.820412 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92434 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70211 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.316517 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101611575500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.820412 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.926276 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.926276 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 396218 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 396218 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90199 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90199 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90199 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90199 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90199 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90199 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71940 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 71940 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71940 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 71940 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71940 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 71940 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 878693205 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 878693205 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 878693205 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 878693205 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 878693205 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 878693205 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162139 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 162139 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162139 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 162139 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162139 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 162139 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.443693 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.443693 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.443693 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.443693 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.443693 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.443693 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12214.250834 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12214.250834 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12214.250834 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12214.250834 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12214.250834 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 398660 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 398660 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92440 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92440 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92440 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92440 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92440 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92440 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71260 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71260 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71260 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71260 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71260 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71260 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 875246716 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 875246716 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 875246716 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 875246716 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 875246716 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 875246716 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 163700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 163700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 163700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 163700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 163700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 163700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435308 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435308 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435308 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435308 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435308 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435308 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12282.440584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12282.440584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12282.440584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12282.440584 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1131,153 +1134,153 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22838 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22838 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71940 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71940 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71940 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 71940 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71940 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 71940 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 734698929 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 734698929 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 734698929 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 734698929 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 734698929 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 734698929 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.443693 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.443693 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.443693 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.443693 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10212.662344 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10212.662344 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10212.662344 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20047 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20047 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71260 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71260 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71260 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71260 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71260 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71260 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 732616430 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 732616430 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 732616430 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 732616430 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 732616430 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 732616430 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435308 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435308 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435308 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10280.892927 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1658766 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994288 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19002910 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659278 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.452517 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1657713 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996506 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19009946 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1658225 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.464033 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994288 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996506 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87874474 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87874474 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10896738 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10896738 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8103479 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8103479 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19000217 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19000217 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19000217 # number of overall hits -system.cpu.dcache.overall_hits::total 19000217 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2237270 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2237270 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316309 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316309 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553579 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553579 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553579 # number of overall misses -system.cpu.dcache.overall_misses::total 2553579 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32758938054 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32758938054 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12034849454 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12034849454 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44793787508 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44793787508 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44793787508 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44793787508 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13134008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13134008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8419788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8419788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21553796 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21553796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21553796 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21553796 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170342 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170342 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037567 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037567 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118475 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118475 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14642.371307 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14642.371307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38047.761695 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38047.761695 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17541.571069 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17541.571069 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17541.571069 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 388234 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87793833 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87793833 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10909808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10909808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8097329 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8097329 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19007137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19007137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19007137 # number of overall hits +system.cpu.dcache.overall_hits::total 19007137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2211100 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2211100 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315662 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2526762 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2526762 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2526762 # number of overall misses +system.cpu.dcache.overall_misses::total 2526762 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32878750930 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32878750930 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12078727781 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12078727781 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 44957478711 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 44957478711 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 44957478711 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 44957478711 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13120908 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13120908 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8412991 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412991 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21533899 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21533899 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21533899 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21533899 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168517 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.168517 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037521 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037521 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117339 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117339 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117339 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117339 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14869.861576 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14869.861576 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38264.750844 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38264.750844 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17792.526052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17792.526052 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 428041 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42159 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 36530 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.208805 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.717520 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1559977 # number of writebacks -system.cpu.dcache.writebacks::total 1559977 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867558 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867558 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24476 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24476 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 892034 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 892034 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 892034 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 892034 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369712 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369712 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291833 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291833 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1661545 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1661545 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1661545 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1661545 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17680675970 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17680675970 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11138475501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11138475501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28819151471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28819151471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28819151471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28819151471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364609500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364609500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539074000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539074000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903683500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903683500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104287 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104287 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.316471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.316471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38167.292599 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38167.292599 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17344.791427 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17344.791427 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1559500 # number of writebacks +system.cpu.dcache.writebacks::total 1559500 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840350 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 840350 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25845 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25845 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 866195 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 866195 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 866195 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069072 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.069072 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63692.250479 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64941.993254 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64563.238983 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10640.164927 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10640.164927 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56955.740006 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56955.740006 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63201.326063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66455.955442 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65453.757057 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10641.745265 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10641.745265 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57113.589053 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57113.589053 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72079.166667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63692.250479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58659.135444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59103.321516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 8b1d3ad58..61d45995b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -28,7 +28,7 @@ Built 1 zonelists. Total pages: 30612 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.008 MHz processor.
+time.c: Detected 1999.999 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -44,7 +44,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812560
+result 7812524
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 42bed7716..bf000969d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,14 +20,14 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 load_offset=0 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/z/stever/hg/gem5/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1597,7 +1597,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1620,7 +1620,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 246bb0fe6..56f83c534 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -3,6 +3,7 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unimplemented function 8 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index ad22be7e5..6a57a8844 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 12 2014 12:50:47 -gem5 started May 12 2014 15:35:34 -gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /z/stever/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:18:32 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 80c9b1902..307acd090 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133875 # Number of seconds simulated -sim_ticks 5133874673500 # Number of ticks simulated -final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.135764 # Number of seconds simulated +sim_ticks 5135763847500 # Number of ticks simulated +final_tick 5135763847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236000 # Simulator instruction rate (inst/s) -host_op_rate 469116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4968557721 # Simulator tick rate (ticks/s) -host_mem_usage 928744 # Number of bytes of host memory used -host_seconds 1033.27 # Real time elapsed on the host -sim_insts 243852609 # Number of instructions simulated -sim_ops 484724493 # Number of ops (including micro ops) simulated +host_inst_rate 259782 # Simulator instruction rate (inst/s) +host_op_rate 516376 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5470381356 # Simulator tick rate (ticks/s) +host_mem_usage 959692 # Number of bytes of host memory used +host_seconds 938.83 # Real time elapsed on the host +sim_insts 243891279 # Number of instructions simulated +sim_ops 484789360 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 500480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5911104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 139776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1689280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 309696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2752128 # Number of bytes read from this memory -system.physmem.bytes_read::total 13749568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 500480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 139776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 309696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 949952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9083392 # Number of bytes written to this memory -system.physmem.bytes_written::total 9083392 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38210 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 92361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 26395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 43002 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214837 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141928 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141928 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 97486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1151392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 329046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 60324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 536072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2678205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 97486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 60324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 185036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1769305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1769305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1769305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 97486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1151392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 329046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 60324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 536072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4447510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 96612 # Number of read requests accepted -system.physmem.writeReqs 73475 # Number of write requests accepted -system.physmem.readBursts 96612 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 73475 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6177024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 4701248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6183168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4702400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2442432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 470912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6169536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 114240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1582592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 379456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2632640 # Number of bytes read from this memory +system.physmem.bytes_read::total 13794368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 470912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 114240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 379456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9131520 # Number of bytes written to this memory +system.physmem.bytes_written::total 9131520 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7358 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 96399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24728 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41135 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215537 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142680 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 91693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1201289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 22244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 308151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 512609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2685943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 91693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 22244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73885 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1778026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1778026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1778026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 91693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1201289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 22244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 308151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 512609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4463968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 94056 # Number of read requests accepted +system.physmem.writeReqs 72760 # Number of write requests accepted +system.physmem.readBursts 94056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 72760 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6015488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4096 # Total number of bytes read from write queue +system.physmem.bytesWritten 4656640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6019584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4656640 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 64 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 831 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5404 # Per bank write bursts -system.physmem.perBankRdBursts::1 5964 # Per bank write bursts -system.physmem.perBankRdBursts::2 6149 # Per bank write bursts -system.physmem.perBankRdBursts::3 6338 # Per bank write bursts -system.physmem.perBankRdBursts::4 5414 # Per bank write bursts -system.physmem.perBankRdBursts::5 6001 # Per bank write bursts -system.physmem.perBankRdBursts::6 5201 # Per bank write bursts -system.physmem.perBankRdBursts::7 6053 # Per bank write bursts -system.physmem.perBankRdBursts::8 5779 # Per bank write bursts -system.physmem.perBankRdBursts::9 5783 # Per bank write bursts -system.physmem.perBankRdBursts::10 5919 # Per bank write bursts -system.physmem.perBankRdBursts::11 5801 # Per bank write bursts -system.physmem.perBankRdBursts::12 6766 # Per bank write bursts -system.physmem.perBankRdBursts::13 6809 # Per bank write bursts -system.physmem.perBankRdBursts::14 6844 # Per bank write bursts -system.physmem.perBankRdBursts::15 6291 # Per bank write bursts -system.physmem.perBankWrBursts::0 4307 # Per bank write bursts -system.physmem.perBankWrBursts::1 4604 # Per bank write bursts -system.physmem.perBankWrBursts::2 4694 # Per bank write bursts -system.physmem.perBankWrBursts::3 4750 # Per bank write bursts -system.physmem.perBankWrBursts::4 4088 # Per bank write bursts -system.physmem.perBankWrBursts::5 4371 # Per bank write bursts -system.physmem.perBankWrBursts::6 3767 # Per bank write bursts -system.physmem.perBankWrBursts::7 4522 # Per bank write bursts -system.physmem.perBankWrBursts::8 4168 # Per bank write bursts -system.physmem.perBankWrBursts::9 4368 # Per bank write bursts -system.physmem.perBankWrBursts::10 4606 # Per bank write bursts -system.physmem.perBankWrBursts::11 4444 # Per bank write bursts -system.physmem.perBankWrBursts::12 5448 # Per bank write bursts -system.physmem.perBankWrBursts::13 5248 # Per bank write bursts -system.physmem.perBankWrBursts::14 5481 # Per bank write bursts -system.physmem.perBankWrBursts::15 4591 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 766 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5609 # Per bank write bursts +system.physmem.perBankRdBursts::1 5668 # Per bank write bursts +system.physmem.perBankRdBursts::2 5585 # Per bank write bursts +system.physmem.perBankRdBursts::3 5594 # Per bank write bursts +system.physmem.perBankRdBursts::4 6037 # Per bank write bursts +system.physmem.perBankRdBursts::5 6612 # Per bank write bursts +system.physmem.perBankRdBursts::6 5733 # Per bank write bursts +system.physmem.perBankRdBursts::7 5990 # Per bank write bursts +system.physmem.perBankRdBursts::8 5523 # Per bank write bursts +system.physmem.perBankRdBursts::9 5460 # Per bank write bursts +system.physmem.perBankRdBursts::10 5647 # Per bank write bursts +system.physmem.perBankRdBursts::11 6128 # Per bank write bursts +system.physmem.perBankRdBursts::12 6059 # Per bank write bursts +system.physmem.perBankRdBursts::13 6267 # Per bank write bursts +system.physmem.perBankRdBursts::14 6194 # Per bank write bursts +system.physmem.perBankRdBursts::15 5886 # Per bank write bursts +system.physmem.perBankWrBursts::0 4545 # Per bank write bursts +system.physmem.perBankWrBursts::1 4402 # Per bank write bursts +system.physmem.perBankWrBursts::2 4127 # Per bank write bursts +system.physmem.perBankWrBursts::3 4299 # Per bank write bursts +system.physmem.perBankWrBursts::4 4675 # Per bank write bursts +system.physmem.perBankWrBursts::5 5126 # Per bank write bursts +system.physmem.perBankWrBursts::6 4327 # Per bank write bursts +system.physmem.perBankWrBursts::7 4679 # Per bank write bursts +system.physmem.perBankWrBursts::8 4360 # Per bank write bursts +system.physmem.perBankWrBursts::9 4207 # Per bank write bursts +system.physmem.perBankWrBursts::10 4528 # Per bank write bursts +system.physmem.perBankWrBursts::11 4822 # Per bank write bursts +system.physmem.perBankWrBursts::12 4836 # Per bank write bursts +system.physmem.perBankWrBursts::13 4641 # Per bank write bursts +system.physmem.perBankWrBursts::14 4944 # Per bank write bursts +system.physmem.perBankWrBursts::15 4242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5132874544500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 5131947184500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 96612 # Read request sizes (log2) +system.physmem.readPktSize::6 94056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 73475 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1283 # What read queue length does an incoming req see +system.physmem.writePktSize::6 72760 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -161,464 +165,474 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 3779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.633118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.344584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.042030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13828 38.72% 38.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8395 23.51% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3582 10.03% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1962 5.49% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1409 3.95% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 988 2.77% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 701 1.96% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 566 1.59% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4278 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35709 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4100 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.539756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 117.618727 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 4089 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 8 0.20% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4100 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4100 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.916341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.808533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.372443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 61 1.49% 1.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 8 0.20% 1.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 2 0.05% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 3 0.07% 1.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-9 1 0.02% 1.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10-11 1 0.02% 1.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-13 1 0.02% 1.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 5 0.12% 2.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2769 67.54% 69.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 821 20.02% 89.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 36 0.88% 90.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 38 0.93% 91.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 31 0.76% 92.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 30 0.73% 92.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 54 1.32% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 53 1.29% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 24 0.59% 96.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 28 0.68% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 12 0.29% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 22 0.54% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 34 0.83% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 16 0.39% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 10 0.24% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 6 0.15% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 8 0.20% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 2 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 5 0.12% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 2 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 8 0.20% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4100 # Writes before turning the bus around for reads -system.physmem.totQLat 2438372750 # Total ticks spent queuing -system.physmem.totMemAccLat 4248047750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 482580000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25263.92 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::25 4031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.746690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.799684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.095227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14318 40.08% 40.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8282 23.18% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3507 9.82% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1954 5.47% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1307 3.66% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 922 2.58% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 623 1.74% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 530 1.48% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4280 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35723 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.627954 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 119.433357 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 3969 99.77% 99.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.18% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3978 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3978 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.290598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.208175 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.685696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 45 1.13% 1.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 5 0.13% 1.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 3 0.08% 1.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 4 0.10% 1.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10-11 1 0.03% 1.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 5 0.13% 1.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2627 66.04% 67.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 818 20.56% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 28 0.70% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 32 0.80% 89.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 32 0.80% 90.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 35 0.88% 91.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 65 1.63% 93.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 48 1.21% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 35 0.88% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 29 0.73% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 29 0.73% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 26 0.65% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 31 0.78% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 18 0.45% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 10 0.25% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 17 0.43% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 8 0.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 6 0.15% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 2 0.05% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 7 0.18% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 3 0.08% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3978 # Writes before turning the bus around for reads +system.physmem.totQLat 2424873249 # Total ticks spent queuing +system.physmem.totMemAccLat 4187223249 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 469960000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25798.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44013.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44548.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.91 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.46 # Average write queue length when enqueuing -system.physmem.readRowHits 79177 # Number of row buffer hits during reads -system.physmem.writeRowHits 55086 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes -system.physmem.avgGap 30177935.67 # Average gap between requests -system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4939989054000 # Time in different power states -system.physmem.memoryStateTime::REF 171431260000 # Time in different power states +system.physmem.avgWrQLen 6.97 # Average write queue length when enqueuing +system.physmem.readRowHits 76538 # Number of row buffer hits during reads +system.physmem.writeRowHits 54491 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.89 # Row buffer hit rate for writes +system.physmem.avgGap 30764118.46 # Average gap between requests +system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4942425043001 # Time in different power states +system.physmem.memoryStateTime::REF 171494180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22454242000 # Time in different power states +system.physmem.memoryStateTime::ACT 21844559499 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6437004 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 422289 # Transaction distribution -system.membus.trans_dist::ReadResp 422287 # Transaction distribution -system.membus.trans_dist::WriteReq 6118 # Transaction distribution -system.membus.trans_dist::WriteResp 6118 # Transaction distribution -system.membus.trans_dist::Writeback 73475 # Transaction distribution -system.membus.trans_dist::UpgradeReq 843 # Transaction distribution -system.membus.trans_dist::UpgradeResp 843 # Transaction distribution -system.membus.trans_dist::ReadExReq 76388 # Transaction distribution -system.membus.trans_dist::ReadExResp 76388 # Transaction distribution -system.membus.trans_dist::MessageReq 850 # Transaction distribution -system.membus.trans_dist::MessageResp 850 # Transaction distribution +system.membus.throughput 6452408 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 421921 # Transaction distribution +system.membus.trans_dist::ReadResp 421919 # Transaction distribution +system.membus.trans_dist::WriteReq 5915 # Transaction distribution +system.membus.trans_dist::WriteResp 5915 # Transaction distribution +system.membus.trans_dist::Writeback 72760 # Transaction distribution +system.membus.trans_dist::UpgradeReq 778 # Transaction distribution +system.membus.trans_dist::UpgradeResp 778 # Transaction distribution +system.membus.trans_dist::ReadExReq 75224 # Transaction distribution +system.membus.trans_dist::ReadExResp 75224 # Transaction distribution +system.membus.trans_dist::MessageReq 825 # Transaction distribution +system.membus.trans_dist::MessageResp 825 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 204215 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196326 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1010391 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 69253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 69253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1081344 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158115 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995025 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8047552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9200692 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2838016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2838016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12042108 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32720690 # Total data (bytes) -system.membus.snoop_data_through_bus 326080 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 162128500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1002050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1075932 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 157715 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995169 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7734720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 8887604 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2941504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2941504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 11832408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32744958 # Total data (bytes) +system.membus.snoop_data_through_bus 393088 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 161596500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315102000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315113000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1650000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 806327999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 794070497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 850000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 825000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1598914090 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1569908183 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 224687998 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 236956000 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 103794 # number of replacements -system.l2c.tags.tagsinuse 64810.608353 # Cycle average of tags in use -system.l2c.tags.total_refs 3657966 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167984 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.775681 # Average number of references to valid blocks. +system.l2c.tags.replacements 104346 # number of replacements +system.l2c.tags.tagsinuse 64811.945905 # Cycle average of tags in use +system.l2c.tags.total_refs 3669840 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168730 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.749778 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51486.278563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1295.377972 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4270.696448 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 302.542141 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1483.932036 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.824361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1349.140567 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4614.691210 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.785618 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51276.768453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1221.298902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4234.138382 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002961 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 249.507225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1581.676468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.253356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1493.843089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4747.335130 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.782421 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019766 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022643 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020586 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988931 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64190 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3206 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7166 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53256 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979462 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33587388 # Number of tag accesses -system.l2c.tags.data_accesses 33587388 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20605 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 339595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 520668 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10906 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 151391 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 219548 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 53731 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 8985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 345046 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 563659 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2251830 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.018636 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064608 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.024134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000111 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65028.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63366.377635 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59959.493595 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59502.614100 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -750,44 +770,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.089403 # Cycle average of tags in use +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.095086 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000209950509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.089403 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005588 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005588 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000199085509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095086 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005943 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005943 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428670 # Number of tag accesses -system.iocache.tags.data_accesses 428670 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131527041 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 131527041 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5824382656 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5824382656 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 5955909697 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5955909697 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 5955909697 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5955909697 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses +system.iocache.demand_misses::total 47628 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses +system.iocache.overall_misses::total 47628 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130701291 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130701291 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6017123258 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6017123258 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6147824549 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6147824549 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6147824549 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6147824549 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -796,60 +816,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144535.209890 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 144535.209890 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 124665.724658 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 124665.724658 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.343208 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.343208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 88795 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143944.153084 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 143944.153084 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 128791.165625 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 128791.165625 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129080.048480 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129080.048480 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 86048 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8200 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7909 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.828659 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.879757 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 733 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24176 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 24176 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 24909 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 24909 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 24909 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 24909 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93385041 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93385041 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4566242660 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4566242660 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4659627701 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4659627701 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.805495 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.805495 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.517466 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.517466 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.522969 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.522969 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127401.147340 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127401.147340 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 188875.027300 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 188875.027300 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 735 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 735 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 25536 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 25536 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 26271 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 26271 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 26271 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 26271 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92456791 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92456791 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4688241758 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4688241758 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4780698549 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4780698549 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.809471 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.809471 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.546575 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.546575 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.551587 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.551587 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -859,510 +879,511 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52260442 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1795853 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1795321 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6118 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6118 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 903975 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 804 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 804 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 176511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 152342 # Transaction distribution +system.toL2Bus.throughput 52407719 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1793633 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1793101 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 5915 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 5915 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 899960 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 730 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 730 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 172146 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 146613 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006951 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3618137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34540 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 139444 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4799072 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32221504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120018356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 123320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 517264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152880444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268161042 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 137520 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5048228823 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 999818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3602290 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 141650 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4778107 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31993152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119401652 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152041460 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 269011854 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 141816 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5025953302 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2267749080 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2251918114 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4703679799 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4677619434 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19140467 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19272449 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 74891774 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 76057203 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1277477 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149797 # Transaction distribution -system.iobus.trans_dist::ReadResp 149797 # Transaction distribution -system.iobus.trans_dist::WriteReq 29441 # Transaction distribution -system.iobus.trans_dist::WriteResp 29441 # Transaction distribution -system.iobus.trans_dist::MessageReq 850 # Transaction distribution -system.iobus.trans_dist::MessageResp 850 # Transaction distribution +system.iobus.throughput 1276582 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 149714 # Transaction distribution +system.iobus.trans_dist::ReadResp 149714 # Transaction distribution +system.iobus.trans_dist::WriteReq 30624 # Transaction distribution +system.iobus.trans_dist::WriteResp 30624 # Transaction distribution +system.iobus.trans_dist::MessageReq 825 # Transaction distribution +system.iobus.trans_dist::MessageResp 825 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4890 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 558 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 38 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 588 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287110 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 308658 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49818 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49818 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 360176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 308134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 52542 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 52542 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 362326 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2760 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 279 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 19 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143555 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143604 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 312 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 158115 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1583592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1583592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1745107 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6558405 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2044244 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 157715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1670648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1670648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3300 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1831663 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6556225 # Total data (bytes) +system.iobus.reqLayer0.occupancy 1987954 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4518000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4046000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 367000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 387000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143556000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143605000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 178000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 124000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9750000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9774000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 220209699 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 232428549 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303393000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 303046000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30099002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 31488000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 850000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 825000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1160444400 # number of cpu cycles simulated +system.cpu0.numCycles 1167096017 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72635405 # Number of instructions committed -system.cpu0.committedOps 147758080 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 135731001 # Number of integer alu accesses +system.cpu0.committedInsts 72932334 # Number of instructions committed +system.cpu0.committedOps 148186849 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136173063 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1010341 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14309822 # number of instructions that are conditional controls -system.cpu0.num_int_insts 135731001 # number of integer instructions +system.cpu0.num_func_calls 1014433 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14332221 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136173063 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 249546871 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116495894 # number of times the integer registers were written +system.cpu0.num_int_register_reads 250637191 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116800630 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84252648 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56217158 # number of times the CC registers were written -system.cpu0.num_mem_refs 14168966 # number of memory refs -system.cpu0.num_load_insts 10366088 # Number of load instructions -system.cpu0.num_store_insts 3802878 # Number of store instructions -system.cpu0.num_idle_cycles 1101978015.213226 # Number of idle cycles -system.cpu0.num_busy_cycles 58466384.786774 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050383 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949617 # Percentage of idle cycles -system.cpu0.Branches 15683494 # Number of branches fetched -system.cpu0.op_class::No_OpClass 100234 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 133376064 90.27% 90.33% # Class of executed instruction -system.cpu0.op_class::IntMult 62929 0.04% 90.38% # Class of executed instruction -system.cpu0.op_class::IntDiv 50413 0.03% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::MemRead 10366088 7.02% 97.43% # Class of executed instruction -system.cpu0.op_class::MemWrite 3802878 2.57% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 84487712 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56367816 # number of times the CC registers were written +system.cpu0.num_mem_refs 14369378 # number of memory refs +system.cpu0.num_load_insts 10451844 # Number of load instructions +system.cpu0.num_store_insts 3917534 # Number of store instructions +system.cpu0.num_idle_cycles 1108227141.183960 # Number of idle cycles +system.cpu0.num_busy_cycles 58868875.816040 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050440 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949560 # Percentage of idle cycles +system.cpu0.Branches 15712912 # Number of branches fetched +system.cpu0.op_class::No_OpClass 100385 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 133601927 90.16% 90.23% # Class of executed instruction +system.cpu0.op_class::IntMult 62763 0.04% 90.27% # Class of executed instruction +system.cpu0.op_class::IntDiv 53014 0.04% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::MemRead 10451844 7.05% 97.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 3917534 2.64% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # 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number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 353426 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 499925 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1731523249 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4361398381 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6092921630 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1731523249 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4361398381 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6092921630 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1731523249 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4361398381 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6092921630 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003826 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003815 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111155 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11819.352002 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.035294 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.476186 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.513978 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009835 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.563820 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 233.097338 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.338124 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534304 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.455268 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010426 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 210 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88185539 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88185539 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5216887 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2373282 # 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miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135622 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093511 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14231.485281 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16237.347483 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10881.588659 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34858.390247 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30079.869474 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17222.814847 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18717.945559 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17655.422797 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 11868.668449 # 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miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038599 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037581 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.036150 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037575 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.070756 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.067885 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.133005 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092236 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070756 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.067885 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133005 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092236 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14287.058948 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15864.418213 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10571.977280 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32826.883677 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30575.551351 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16393.968289 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17333.894211 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 11491.423730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18321.478835 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17333.894211 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11491.423730 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 80099 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11797 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 18060 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.722218 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.435161 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1542066 # number of writebacks -system.cpu0.dcache.writebacks::total 1542066 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 371761 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 371761 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17373 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 17373 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 389134 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 389134 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 389134 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 389134 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 223619 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 577178 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 800797 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62158 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 90935 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 153093 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 285777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 668113 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 953890 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 285777 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 668113 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 953890 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2734176493 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8368429033 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11102605526 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032053179 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2876927496 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4908980675 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4766229672 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11245356529 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16011586201 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4766229672 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11245356529 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16011586201 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30475246000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33186567000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63661813000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 395642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 753351500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1148993500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30870888000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33939918500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64810806500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086110 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118022 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060483 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036684 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031302 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044084 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044084 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12226.941776 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14498.870423 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13864.444455 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32691.740066 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31637.185858 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32065.350310 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1546042 # number of writebacks +system.cpu0.dcache.writebacks::total 1546042 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 343252 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 343252 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17347 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17347 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 360599 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 360599 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 360599 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 360599 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 225418 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 575479 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 800897 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62696 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84608 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 147304 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 288114 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 660087 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 948201 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 288114 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 660087 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 948201 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2768607746 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8066658535 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10835266281 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1923226701 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2756691504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4679918205 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4691834447 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10823350039 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15515184486 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4691834447 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10823350039 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15515184486 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30492689000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33165040000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63657729000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 394150500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 725206000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1119356500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30886839500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33890246000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64777085500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087511 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118564 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060350 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037581 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030000 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017533 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.043751 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.043751 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1373,376 +1394,377 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606021866 # number of cpu cycles simulated +system.cpu1.numCycles 2604023259 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34914129 # Number of instructions committed -system.cpu1.committedOps 67869828 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62995297 # Number of integer alu accesses +system.cpu1.committedInsts 34762499 # Number of instructions committed +system.cpu1.committedOps 67606793 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62736553 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 438942 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62995297 # number of integer instructions +system.cpu1.num_func_calls 437056 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6403696 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62736553 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 116271710 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54373007 # number of times the integer registers were written +system.cpu1.num_int_register_reads 115724590 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54164636 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35773638 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26686136 # number of times the CC registers were written -system.cpu1.num_mem_refs 4480512 # number of memory refs -system.cpu1.num_load_insts 2784989 # Number of load instructions -system.cpu1.num_store_insts 1695523 # Number of store instructions -system.cpu1.num_idle_cycles 2483027076.334052 # Number of idle cycles -system.cpu1.num_busy_cycles 122994789.665948 # Number of busy cycles -system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles -system.cpu1.Branches 7029914 # Number of branches fetched -system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 63308003 93.28% 93.32% # Class of executed instruction -system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction -system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::MemRead 2784989 4.10% 97.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 1695523 2.50% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 35537675 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26584960 # number of times the CC registers were written +system.cpu1.num_mem_refs 4433444 # number of memory refs +system.cpu1.num_load_insts 2764122 # Number of load instructions +system.cpu1.num_store_insts 1669322 # Number of store instructions +system.cpu1.num_idle_cycles 2476870816.288117 # Number of idle cycles +system.cpu1.num_busy_cycles 127152442.711883 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048829 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951171 # Percentage of idle cycles +system.cpu1.Branches 7001569 # Number of branches fetched +system.cpu1.op_class::No_OpClass 28648 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 63095899 93.33% 93.37% # Class of executed instruction +system.cpu1.op_class::IntMult 28577 0.04% 93.41% # Class of executed instruction +system.cpu1.op_class::IntDiv 20525 0.03% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::MemRead 2764122 4.09% 97.53% # Class of executed instruction +system.cpu1.op_class::MemWrite 1669322 2.47% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 67870143 # Class of executed instruction +system.cpu1.op_class::total 67607093 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28758894 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28758894 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 306803 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26351534 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25737629 # Number of BTB hits +system.cpu2.branchPred.lookups 28894520 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28894520 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 314484 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26386768 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25807983 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.670325 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 530881 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 61512 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154845080 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.806533 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 541788 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 61672 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154118891 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9460785 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141747704 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28758894 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26268510 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54302787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1434244 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 58972 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24471854 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6545 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 20028 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3117082 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 139514 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1749 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 89437217 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.124405 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.409858 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9526926 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142222809 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28894520 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26349771 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54464711 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1558370 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 64917 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 23183087 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6096 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 25004 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3179586 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 151181 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1925 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88503258 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.167922 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.413230 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 35270123 39.44% 39.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 589507 0.66% 40.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23704151 26.50% 66.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 307246 0.34% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 603965 0.68% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 802586 0.90% 68.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 334965 0.37% 68.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 517417 0.58% 69.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27307257 30.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34173678 38.61% 38.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 596420 0.67% 39.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23721602 26.80% 66.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 320974 0.36% 66.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 619988 0.70% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 815233 0.92% 68.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 353145 0.40% 68.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 523827 0.59% 69.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27378391 30.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 89437217 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185727 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.915416 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10926187 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23367960 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 31523393 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1298286 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1115198 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278635226 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 49 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1115198 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11921655 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13834152 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4411879 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 31656208 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5292001 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277656292 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6764 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2483668 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2130930 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 331880087 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 604361998 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371268132 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321920244 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9959841 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 147988 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 148926 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11485411 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6218482 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3410117 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 341148 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 274139 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276004640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 412430 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274449569 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 59781 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7023554 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10820295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 55045 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 89437217 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.068628 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.396853 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88503258 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.187482 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.922812 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10770329 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22316529 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 33210052 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 993418 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1230628 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279539625 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 15 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1230628 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11632631 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 11620518 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4366536 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 33251587 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 6419117 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278526444 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 145793 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2942087 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 39888 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 2722851 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 332982462 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 606515542 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 372413837 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321866415 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11116047 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 145000 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 146469 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 9034946 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6263244 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3375371 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 381006 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 309187 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276743563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 411647 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274777165 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 83308 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7862427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12385425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 57804 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88503258 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.104712 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400001 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26098480 29.18% 29.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6131096 6.86% 36.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3936751 4.40% 40.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2730796 3.05% 43.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25025448 27.98% 71.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1337810 1.50% 72.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23830586 26.65% 99.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 291775 0.33% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 54475 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25772149 29.12% 29.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5479119 6.19% 35.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3780646 4.27% 39.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2658058 3.00% 42.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25098242 28.36% 70.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1415095 1.60% 72.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23897363 27.00% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 310729 0.35% 99.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 91857 0.10% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 89437217 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88503258 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 125312 33.75% 33.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 120 0.03% 33.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 109 0.03% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 191005 51.44% 85.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 54802 14.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 130084 34.74% 34.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 34.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 103 0.03% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 196279 52.42% 87.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 48005 12.82% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 76601 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264560846 96.40% 96.42% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54414 0.02% 96.44% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50942 0.02% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6508971 2.37% 98.83% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3197795 1.17% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 79957 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264964709 96.43% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54296 0.02% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50937 0.02% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6495012 2.36% 98.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3132254 1.14% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274449569 # Type of FU issued -system.cpu2.iq.rate 1.772414 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 371348 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001353 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 638809448 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 283444416 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273102485 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 12 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274744310 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 6 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 641561 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274777165 # Type of FU issued +system.cpu2.iq.rate 1.782891 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 374471 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001363 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 638559252 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285021199 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273394851 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275071659 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 655974 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 993516 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6753 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4280 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 500329 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1102337 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6308 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4079 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 550460 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656426 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10045 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656385 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 7890 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1115198 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9119918 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 823405 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276417070 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 70631 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6218482 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3410117 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 233790 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 637954 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3900 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4280 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 173413 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 173644 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 347057 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273959168 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6398525 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 490400 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1230628 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6003858 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2680102 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277155210 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55656 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6263266 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3375371 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 233323 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 631738 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1840063 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4079 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 177700 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 182074 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 359774 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 274266101 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6377623 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 511064 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9531292 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27864904 # Number of branches executed -system.cpu2.iew.exec_stores 3132767 # Number of stores executed -system.cpu2.iew.exec_rate 1.769247 # Inst execution rate -system.cpu2.iew.wb_sent 273810478 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273102491 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212979431 # num instructions producing a value -system.cpu2.iew.wb_consumers 348314367 # num instructions consuming a value +system.cpu2.iew.exec_refs 9440682 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27899539 # Number of branches executed +system.cpu2.iew.exec_stores 3063059 # Number of stores executed +system.cpu2.iew.exec_rate 1.779575 # Inst execution rate +system.cpu2.iew.wb_sent 274107922 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273394865 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 213810949 # num instructions producing a value +system.cpu2.iew.wb_consumers 349940477 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.763714 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611457 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.773922 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.610992 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7316358 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357385 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 309115 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 88322018 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.046767 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870309 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8157845 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 353843 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 317282 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 87272630 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.082246 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.874009 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30852434 34.93% 34.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4395307 4.98% 39.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1238857 1.40% 41.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24650858 27.91% 69.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 865215 0.98% 70.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 585749 0.66% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 347954 0.39% 71.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23291491 26.37% 97.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2094153 2.37% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30201439 34.61% 34.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4017102 4.60% 39.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1154677 1.32% 40.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24628965 28.22% 68.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 905267 1.04% 69.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 589610 0.68% 70.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 344278 0.39% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23302755 26.70% 97.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2128537 2.44% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 88322018 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136303075 # Number of instructions committed -system.cpu2.commit.committedOps 269096585 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 87272630 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136196446 # Number of instructions committed +system.cpu2.commit.committedOps 268995718 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8134753 # Number of memory references committed -system.cpu2.commit.loads 5224965 # Number of loads committed -system.cpu2.commit.membars 164376 # Number of memory barriers committed -system.cpu2.commit.branches 27532187 # Number of branches committed +system.cpu2.commit.refs 7985840 # Number of memory references committed +system.cpu2.commit.loads 5160929 # Number of loads committed +system.cpu2.commit.membars 163767 # Number of memory barriers committed +system.cpu2.commit.branches 27540439 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245708361 # Number of committed integer instructions. -system.cpu2.commit.function_calls 429087 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 43848 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 260815603 96.92% 96.94% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52558 0.02% 96.96% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 49823 0.02% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5224965 1.94% 98.92% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2909788 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 245590309 # Number of committed integer instructions. +system.cpu2.commit.function_calls 428081 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46387 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 260861796 96.98% 96.99% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52266 0.02% 97.01% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 49429 0.02% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5160929 1.92% 98.95% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2824911 1.05% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 269096585 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2094153 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 268995718 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2128537 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 362613065 # The number of ROB reads -system.cpu2.rob.rob_writes 553944877 # The number of ROB writes -system.cpu2.timesIdled 473034 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65407863 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4900873955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136303075 # Number of Instructions Simulated -system.cpu2.committedOps 269096585 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.136035 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.136035 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.880254 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.880254 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364552649 # number of integer regfile reads -system.cpu2.int_regfile_writes 218803003 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72918 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139316304 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107298284 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88761943 # number of misc regfile reads -system.cpu2.misc_regfile_writes 132629 # number of misc regfile writes +system.cpu2.rob.rob_reads 362270810 # The number of ROB reads +system.cpu2.rob.rob_writes 555542201 # The number of ROB writes +system.cpu2.timesIdled 475518 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65615633 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4908375985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136196446 # Number of Instructions Simulated +system.cpu2.committedOps 268995718 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.131593 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.131593 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.883710 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.883710 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364616127 # number of integer regfile reads +system.cpu2.int_regfile_writes 219111496 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72926 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes +system.cpu2.cc_regfile_reads 139466740 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107376389 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88828545 # number of misc regfile reads +system.cpu2.misc_regfile_writes 129118 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 08dac49a9..72fbd3738 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -44,7 +44,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812444
+result 7812464
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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