diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2555 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3105 |
2 files changed, 2798 insertions, 2862 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 2fadfdb24..daa556624 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.121937 # Number of seconds simulated -sim_ticks 5121937205500 # Number of ticks simulated -final_tick 5121937205500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.154240 # Number of seconds simulated +sim_ticks 5154239928000 # Number of ticks simulated +final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250170 # Simulator instruction rate (inst/s) -host_op_rate 494496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3139783576 # Simulator tick rate (ticks/s) -host_mem_usage 754660 # Number of bytes of host memory used -host_seconds 1631.30 # Real time elapsed on the host -sim_insts 408103625 # Number of instructions simulated -sim_ops 806672783 # Number of ops (including micro ops) simulated +host_inst_rate 177928 # Simulator instruction rate (inst/s) +host_op_rate 351699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2247974259 # Simulator tick rate (ticks/s) +host_mem_usage 809460 # Number of bytes of host memory used +host_seconds 2292.84 # Real time elapsed on the host +sim_insts 407959851 # Number of instructions simulated +sim_ops 806389826 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1046784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10762752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1048832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10760128 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11842240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9571648 # Number of bytes written to this memory -system.physmem.bytes_written::total 9571648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16356 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168168 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11841856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1048832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1048832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9579968 # Number of bytes written to this memory +system.physmem.bytes_written::total 9579968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168127 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185035 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149557 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2101305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2312063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1868755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1868755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1868755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2101305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4180818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185035 # Number of read requests accepted -system.physmem.writeReqs 196277 # Number of write requests accepted -system.physmem.readBursts 185035 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196277 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11833600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 12404928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11842240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12561728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2419 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1772 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11869 # Per bank write bursts -system.physmem.perBankRdBursts::1 11279 # Per bank write bursts -system.physmem.perBankRdBursts::2 11900 # Per bank write bursts -system.physmem.perBankRdBursts::3 11555 # Per bank write bursts -system.physmem.perBankRdBursts::4 12140 # Per bank write bursts -system.physmem.perBankRdBursts::5 11427 # Per bank write bursts -system.physmem.perBankRdBursts::6 11446 # Per bank write bursts -system.physmem.perBankRdBursts::7 11418 # Per bank write bursts -system.physmem.perBankRdBursts::8 11156 # Per bank write bursts -system.physmem.perBankRdBursts::9 11288 # Per bank write bursts -system.physmem.perBankRdBursts::10 11167 # Per bank write bursts -system.physmem.perBankRdBursts::11 11604 # Per bank write bursts -system.physmem.perBankRdBursts::12 11474 # Per bank write bursts -system.physmem.perBankRdBursts::13 12255 # Per bank write bursts -system.physmem.perBankRdBursts::14 11757 # Per bank write bursts -system.physmem.perBankRdBursts::15 11165 # Per bank write bursts -system.physmem.perBankWrBursts::0 12900 # Per bank write bursts -system.physmem.perBankWrBursts::1 13064 # Per bank write bursts -system.physmem.perBankWrBursts::2 11983 # Per bank write bursts -system.physmem.perBankWrBursts::3 10698 # Per bank write bursts -system.physmem.perBankWrBursts::4 10899 # Per bank write bursts -system.physmem.perBankWrBursts::5 11057 # Per bank write bursts -system.physmem.perBankWrBursts::6 11263 # Per bank write bursts -system.physmem.perBankWrBursts::7 11237 # Per bank write bursts -system.physmem.perBankWrBursts::8 11985 # Per bank write bursts -system.physmem.perBankWrBursts::9 12151 # Per bank write bursts -system.physmem.perBankWrBursts::10 12710 # Per bank write bursts -system.physmem.perBankWrBursts::11 12714 # Per bank write bursts -system.physmem.perBankWrBursts::12 13328 # Per bank write bursts -system.physmem.perBankWrBursts::13 13119 # Per bank write bursts -system.physmem.perBankWrBursts::14 12767 # Per bank write bursts -system.physmem.perBankWrBursts::15 11952 # Per bank write bursts +system.physmem.num_reads::total 185029 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149687 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149687 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 203489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2087627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2297498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1858658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1858658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1858658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2087627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4156156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185029 # Number of read requests accepted +system.physmem.writeReqs 196407 # Number of write requests accepted +system.physmem.readBursts 185029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196407 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11835328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 10911872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11841856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12570048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25884 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1735 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11576 # Per bank write bursts +system.physmem.perBankRdBursts::1 11057 # Per bank write bursts +system.physmem.perBankRdBursts::2 12153 # Per bank write bursts +system.physmem.perBankRdBursts::3 11198 # Per bank write bursts +system.physmem.perBankRdBursts::4 11802 # Per bank write bursts +system.physmem.perBankRdBursts::5 11348 # Per bank write bursts +system.physmem.perBankRdBursts::6 11143 # Per bank write bursts +system.physmem.perBankRdBursts::7 11153 # Per bank write bursts +system.physmem.perBankRdBursts::8 11425 # Per bank write bursts +system.physmem.perBankRdBursts::9 11213 # Per bank write bursts +system.physmem.perBankRdBursts::10 11332 # Per bank write bursts +system.physmem.perBankRdBursts::11 11504 # Per bank write bursts +system.physmem.perBankRdBursts::12 11762 # Per bank write bursts +system.physmem.perBankRdBursts::13 12902 # Per bank write bursts +system.physmem.perBankRdBursts::14 11974 # Per bank write bursts +system.physmem.perBankRdBursts::15 11385 # Per bank write bursts +system.physmem.perBankWrBursts::0 11439 # Per bank write bursts +system.physmem.perBankWrBursts::1 10429 # Per bank write bursts +system.physmem.perBankWrBursts::2 10485 # Per bank write bursts +system.physmem.perBankWrBursts::3 9453 # Per bank write bursts +system.physmem.perBankWrBursts::4 11713 # Per bank write bursts +system.physmem.perBankWrBursts::5 11103 # Per bank write bursts +system.physmem.perBankWrBursts::6 10277 # Per bank write bursts +system.physmem.perBankWrBursts::7 10587 # Per bank write bursts +system.physmem.perBankWrBursts::8 10639 # Per bank write bursts +system.physmem.perBankWrBursts::9 10347 # Per bank write bursts +system.physmem.perBankWrBursts::10 10880 # Per bank write bursts +system.physmem.perBankWrBursts::11 10311 # Per bank write bursts +system.physmem.perBankWrBursts::12 10712 # Per bank write bursts +system.physmem.perBankWrBursts::13 11096 # Per bank write bursts +system.physmem.perBankWrBursts::14 11110 # Per bank write bursts +system.physmem.perBankWrBursts::15 9917 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5121937091000 # Total gap between requests +system.physmem.numWrRetry 48 # Number of times write queue was full causing retry +system.physmem.totGap 5154239876000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185035 # Read request sizes (log2) +system.physmem.readPktSize::6 185029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196277 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196407 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,436 +156,415 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.753643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.995922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.769329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27720 37.03% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17254 23.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7564 10.10% 70.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4205 5.62% 75.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3013 4.02% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2021 2.70% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1360 1.82% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1151 1.54% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10579 14.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74867 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7807 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.681312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.837786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7806 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.148356 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.632665 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.613307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27722 37.68% 37.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17426 23.68% 61.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7585 10.31% 71.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4195 5.70% 77.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2982 4.05% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2040 2.77% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1416 1.92% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1303 1.77% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8911 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73580 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.326437 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.974446 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6766 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7807 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.827334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.378246 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.718812 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6359 81.45% 81.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 60 0.77% 82.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.20% 82.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 274 3.51% 85.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 187 2.40% 88.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.64% 88.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 34 0.44% 89.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 41 0.53% 89.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 177 2.27% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.22% 92.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 12 0.15% 92.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.17% 92.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 35 0.45% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.20% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.10% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 51 0.65% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 104 1.33% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 7 0.09% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 10 0.13% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 27 0.35% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 148 1.90% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 8 0.10% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.08% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 33 0.42% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 12 0.15% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.36% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.05% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.08% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.15% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 7 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.10% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 4 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7807 # Writes before turning the bus around for reads -system.physmem.totQLat 1977045500 # Total ticks spent queuing -system.physmem.totMemAccLat 5443920500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 924500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10692.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6767 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.195508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.700984 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 42.210035 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6335 93.62% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 84 1.24% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.25% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 17 0.25% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.28% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 20 0.30% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 33 0.49% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 32 0.47% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 26 0.38% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 8 0.12% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 61 0.90% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 50 0.74% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.18% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.01% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.13% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 14 0.21% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6767 # Writes before turning the bus around for reads +system.physmem.totQLat 2002245948 # Total ticks spent queuing +system.physmem.totMemAccLat 5469627198 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 924635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10827.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29442.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29577.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing -system.physmem.readRowHits 151994 # Number of row buffer hits during reads -system.physmem.writeRowHits 151865 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes -system.physmem.avgGap 13432404.67 # Average gap between requests -system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 281753640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 153734625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 725665200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 603294480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129490880310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2959572897750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3425368148085 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764386 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4923440733500 # Time in different power states -system.physmem_0.memoryStateTime::REF 171032680000 # Time in different power states +system.physmem.avgWrQLen 23.30 # Average write queue length when enqueuing +system.physmem.readRowHits 151945 # Number of row buffer hits during reads +system.physmem.writeRowHits 129899 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.18 # Row buffer hit rate for writes +system.physmem.avgGap 13512725.27 # Average gap between requests +system.physmem.pageHitRate 79.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 271547640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148165875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 713146200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 553949280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 130302295830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2978239548750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3446878082535 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.747042 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4954509635136 # Time in different power states +system.physmem_0.memoryStateTime::REF 172111160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27462249000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27619022864 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 284240880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 155091750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 716547000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 652704480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129160456155 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2959862743500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3425371705845 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.765080 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4923925616750 # Time in different power states -system.physmem_1.memoryStateTime::REF 171032680000 # Time in different power states +system.physmem_1.actEnergy 284717160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 155351625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 729276600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 550877760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 130834885590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2977772364750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3446976902445 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.766215 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4953723422640 # Time in different power states +system.physmem_1.memoryStateTime::REF 172111160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26978805250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28398444860 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86925803 # Number of BP lookups -system.cpu.branchPred.condPredicted 86925803 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 896443 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80098191 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78212465 # Number of BTB hits +system.cpu.branchPred.lookups 86886659 # Number of BP lookups +system.cpu.branchPred.condPredicted 86886659 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 896606 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80012064 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78173158 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.645732 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1561001 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180305 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.701714 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1555790 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180979 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449601109 # number of cpu cycles simulated +system.cpu.numCycles 452015949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27685322 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429319828 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86925803 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79773466 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418005810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1881156 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 145066 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 56340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 216419 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 69 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 534 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9181154 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 448969 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4854 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447050138 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.052352 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27708415 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429123541 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86886659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79728948 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 420284778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1879978 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 144708 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 58405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207121 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 57 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 651 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9181144 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 450119 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5089 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 449344124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.884391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.047300 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281515886 62.97% 62.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2210439 0.49% 63.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72204596 16.15% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1602689 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2146844 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2305649 0.52% 80.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1524322 0.34% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1908424 0.43% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81631289 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 283935319 63.19% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2153229 0.48% 63.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72170843 16.06% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1584001 0.35% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2141625 0.48% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2336888 0.52% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1524270 0.34% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1887238 0.42% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81610711 18.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447050138 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193340 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954891 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23043701 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264854286 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150758526 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7453047 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 940578 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838760021 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 940578 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25901615 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223330945 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13194802 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154665359 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29016839 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 835288144 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 480498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12432167 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 195018 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13714744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997792221 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1814468169 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1115407405 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 373 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964705167 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33087052 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 465878 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 469687 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39083891 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17351329 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10177979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1302580 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1089364 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829800190 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1202669 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824540368 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243435 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23398238 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36211142 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 151712 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447050138 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.844402 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418243 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 449344124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192220 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.949355 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23005123 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 267198709 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150742142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7458161 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 939989 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838443104 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 939989 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25847202 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 224345308 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13466568 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154654216 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 30090841 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834933758 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 459142 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12335285 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 199811 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14823013 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997303578 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1813575837 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114848675 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 334 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964352232 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32951344 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467055 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 470880 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38821668 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17323479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10180206 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1295686 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1069829 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829469634 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23349289 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.834296 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.415438 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262726585 58.77% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13876357 3.10% 61.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10104726 2.26% 64.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6925504 1.55% 65.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74353941 16.63% 82.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4450821 1.00% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72845421 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1198612 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 568171 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 265024726 58.98% 58.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14037592 3.12% 62.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9914300 2.21% 64.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7059540 1.57% 65.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74309398 16.54% 82.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4399488 0.98% 83.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72817937 16.21% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1206490 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 574653 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447050138 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 449344124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1991949 71.90% 71.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 123 0.00% 71.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1473 0.05% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 615411 22.21% 94.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161409 5.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1987162 71.98% 71.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 137 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 645 0.02% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 611861 22.16% 94.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160804 5.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 289852 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796144481 96.56% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150888 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125650 0.02% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 123 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18436778 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9392596 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 290308 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795868269 96.56% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150766 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125160 0.02% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 92 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18401922 2.23% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9393603 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824540368 # Type of FU issued -system.cpu.iq.rate 1.833938 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2770367 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003360 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2099144137 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854413357 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819991210 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 827020625 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1864655 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824230120 # Type of FU issued +system.cpu.iq.rate 1.823454 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854027763 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1868049 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3351077 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13836 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14513 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1751193 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3330814 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14207 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1754572 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224299 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72996 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207477 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 74768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 940578 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205605732 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9422457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831002859 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153624 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17351329 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10177979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 705669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 415252 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8108448 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14513 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 513988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 533382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1047370 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822936172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18038480 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1469642 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 939989 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205903045 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10169335 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830666192 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152285 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17323479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10180206 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 703380 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 416558 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27207078 # number of memory reference insts executed -system.cpu.iew.exec_branches 83328554 # Number of branches executed -system.cpu.iew.exec_stores 9168598 # Number of stores executed -system.cpu.iew.exec_rate 1.830370 # Inst execution rate -system.cpu.iew.wb_sent 822433213 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819991395 # cumulative count of insts written-back -system.cpu.iew.wb_producers 641244168 # num instructions producing a value -system.cpu.iew.wb_consumers 1050921658 # num instructions consuming a value +system.cpu.iew.exec_refs 27174393 # number of memory reference insts executed +system.cpu.iew.exec_branches 83301836 # Number of branches executed +system.cpu.iew.exec_stores 9170146 # Number of stores executed +system.cpu.iew.exec_rate 1.819883 # Inst execution rate +system.cpu.iew.wb_sent 822114086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819692399 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640992347 # num instructions producing a value +system.cpu.iew.wb_consumers 1050518142 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610173 # average fanout of values written-back +system.cpu.iew.wb_rate 1.813415 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610168 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24200169 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050957 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 908606 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443415424 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675431 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24149765 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1045534 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 907960 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 445713409 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.809212 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.671420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272547704 61.47% 61.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11191107 2.52% 63.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3581688 0.81% 64.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74592593 16.82% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2424395 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1607477 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 945915 0.21% 82.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71066294 16.03% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5458251 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 274913705 61.68% 61.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11179565 2.51% 64.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3571950 0.80% 64.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74564778 16.73% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2421074 0.54% 82.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1628213 0.37% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 937027 0.21% 82.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71052272 15.94% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5444825 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443415424 # Number of insts commited each cycle -system.cpu.commit.committedInsts 408103625 # Number of instructions committed -system.cpu.commit.committedOps 806672783 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 445713409 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407959851 # Number of instructions committed +system.cpu.commit.committedOps 806389826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22427037 # Number of memory references committed -system.cpu.commit.loads 14000251 # Number of loads committed -system.cpu.commit.membars 475479 # Number of memory barriers committed -system.cpu.commit.branches 82225235 # Number of branches committed +system.cpu.commit.refs 22418298 # Number of memory references committed +system.cpu.commit.loads 13992664 # Number of loads committed +system.cpu.commit.membars 471797 # Number of memory barriers committed +system.cpu.commit.branches 82198639 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735463006 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156113 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171674 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783810008 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145072 0.02% 97.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121556 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735203522 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155963 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171777 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783535872 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144976 0.02% 97.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121468 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -612,167 +591,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13997671 1.74% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8426786 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806672783 # Class of committed instruction -system.cpu.commit.bw_lim_events 5458251 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction +system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268751952 # The number of ROB reads -system.cpu.rob.rob_writes 1665400460 # The number of ROB writes -system.cpu.timesIdled 293768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2550971 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9794270972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 408103625 # Number of Instructions Simulated -system.cpu.committedOps 806672783 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.101684 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.101684 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907702 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907702 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092990942 # number of integer regfile reads -system.cpu.int_regfile_writes 656343554 # number of integer regfile writes -system.cpu.fp_regfile_reads 191 # number of floating regfile reads -system.cpu.cc_regfile_reads 416454943 # number of cc regfile reads -system.cpu.cc_regfile_writes 322187827 # number of cc regfile writes -system.cpu.misc_regfile_reads 265705543 # number of misc regfile reads -system.cpu.misc_regfile_writes 400219 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1658771 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995092 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19161993 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659283 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.548357 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995092 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 1270729806 # The number of ROB reads +system.cpu.rob.rob_writes 1664729387 # The number of ROB writes +system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407959851 # Number of Instructions Simulated +system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.107991 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092541258 # number of integer regfile reads +system.cpu.int_regfile_writes 656084038 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.cc_regfile_reads 416293281 # number of cc regfile reads +system.cpu.cc_regfile_writes 322054452 # number of cc regfile writes +system.cpu.misc_regfile_reads 265591845 # number of misc regfile reads +system.cpu.misc_regfile_writes 400328 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1659836 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.989699 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19130413 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1660348 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.521930 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.989699 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88441081 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88441081 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11011311 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11011311 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082990 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082990 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64916 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64916 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19094301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19094301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19159217 # number of overall hits -system.cpu.dcache.overall_hits::total 19159217 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1795762 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1795762 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334107 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334107 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406359 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406359 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2129869 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2129869 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2536228 # number of overall misses -system.cpu.dcache.overall_misses::total 2536228 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26474085005 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26474085005 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12834716256 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12834716256 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39308801261 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39308801261 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39308801261 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39308801261 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12807073 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12807073 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8417097 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8417097 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21224170 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21224170 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21695445 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21695445 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140216 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140216 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039694 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039694 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862255 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.862255 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.116901 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.116901 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14742.535484 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14742.535484 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38414.987582 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38414.987582 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18455.971358 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18455.971358 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.922518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15498.922518 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 371080 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39978 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.282105 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 88364873 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88364873 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10981747 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10981747 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8081553 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8081553 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 64328 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 64328 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19063300 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19063300 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19127628 # number of overall hits +system.cpu.dcache.overall_hits::total 19127628 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1807734 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1807734 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334390 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334390 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406367 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406367 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2142124 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2142124 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2548491 # number of overall misses +system.cpu.dcache.overall_misses::total 2548491 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27237843437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27237843437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13894605384 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13894605384 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41132448821 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41132448821 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41132448821 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41132448821 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12789481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12789481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8415943 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8415943 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 470695 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 470695 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21205424 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21205424 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21676119 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21676119 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.141345 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.141345 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039733 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039733 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863334 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.863334 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101018 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101018 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117571 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117571 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19201.712329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16139.923124 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 413510 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 44186 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.358394 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560107 # number of writebacks -system.cpu.dcache.writebacks::total 1560107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 826960 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 826960 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44237 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44237 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 871197 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 871197 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 871197 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 871197 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968802 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968802 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289870 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289870 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402896 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402896 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1258672 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1258672 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1661568 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1661568 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12247021519 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12247021519 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11168468751 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11168468751 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5577776251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5577776251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23415490270 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23415490270 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993266521 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28993266521 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97397501000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97397501000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2571147000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2571147000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99968648000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99968648000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075646 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075646 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034438 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034438 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854906 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854906 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059304 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059304 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076586 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076586 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12641.408171 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12641.408171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38529.232935 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38529.232935 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13844.208558 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13844.208558 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18603.329755 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18603.329755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17449.340936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17449.340936 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561658 # number of writebacks +system.cpu.dcache.writebacks::total 1561658 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 837908 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 837908 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44444 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44444 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 882352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 882352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 882352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 882352 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969826 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969826 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289946 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289946 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402900 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402900 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1259772 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1259772 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1662672 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1662672 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12862571524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12862571524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12285238213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12285238213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5938147500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5938147500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25147809737 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25147809737 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31085957237 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31085957237 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97453049000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97453049000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2592894500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2592894500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855968 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855968 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059408 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059408 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076705 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076705 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -780,58 +759,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 75411 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.808771 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 114018 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 75427 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.511634 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 193713357500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.808771 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988048 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988048 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 73822 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.784353 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 116295 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 73836 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.575045 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.784353 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986522 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986522 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 457557 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 457557 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114018 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 114018 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114018 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 114018 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114018 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 114018 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 76507 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 76507 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 76507 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 76507 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 76507 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 76507 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935770691 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935770691 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935770691 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 935770691 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935770691 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 935770691 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190525 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 190525 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190525 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 190525 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190525 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 190525 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.401559 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.401559 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.401559 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.401559 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.401559 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.401559 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12231.177422 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12231.177422 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12231.177422 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 457427 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 457427 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116311 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 116311 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116311 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 116311 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116311 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 116311 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74935 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 74935 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74935 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 74935 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74935 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 74935 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914897711 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914897711 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914897711 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 914897711 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914897711 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 914897711 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 191246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 191246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 191246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391825 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391825 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391825 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391825 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391825 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391825 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,180 +819,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22022 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22022 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 76507 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 76507 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 76507 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 76507 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 76507 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 76507 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 782624451 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 782624451 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 782624451 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 782624451 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 782624451 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 782624451 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.401559 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.401559 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.401559 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10229.448952 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20337 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20337 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74935 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74935 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74935 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 74935 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74935 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 74935 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 802357975 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 802357975 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 802357975 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 802357975 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 802357975 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 802357975 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391825 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391825 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391825 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1000352 # number of replacements -system.cpu.icache.tags.tagsinuse 509.220531 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8118136 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1000864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.111128 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147684343000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.220531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994571 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1000631 # number of replacements +system.cpu.icache.tags.tagsinuse 508.729229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8114183 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1001143 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.104919 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148026169000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.729229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.993612 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.993612 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10182088 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10182088 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8118136 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8118136 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8118136 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8118136 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8118136 # number of overall hits -system.cpu.icache.overall_hits::total 8118136 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1063017 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1063017 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1063017 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1063017 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1063017 # number of overall misses -system.cpu.icache.overall_misses::total 1063017 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14764552848 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14764552848 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14764552848 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14764552848 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14764552848 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14764552848 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9181153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9181153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9181153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9181153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9181153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9181153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115783 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115783 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13889.291374 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13889.291374 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13889.291374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13889.291374 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7778 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 283 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.484099 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 10182374 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10182374 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8114183 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8114183 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8114183 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8114183 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8114183 # number of overall hits +system.cpu.icache.overall_hits::total 8114183 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066954 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066954 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066954 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066954 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066954 # number of overall misses +system.cpu.icache.overall_misses::total 1066954 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14925731792 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14925731792 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14925731792 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14925731792 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14925731792 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14925731792 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9181137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9181137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9181137 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9181137 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9181137 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9181137 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116212 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116212 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116212 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116212 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13989.105240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13989.105240 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 10002 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 328 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.493902 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62082 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62082 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62082 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62082 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62082 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62082 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1000935 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1000935 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1000935 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1000935 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1000935 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1000935 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12121618509 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12121618509 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12121618509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12121618509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12121618509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12121618509 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109021 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109021 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109021 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.295383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.295383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65717 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65717 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65717 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65717 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65717 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65717 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001237 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1001237 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1001237 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1001237 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1001237 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1001237 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12740674547 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12740674547 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12740674547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12740674547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12740674547 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12740674547 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109054 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109054 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109054 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 14419 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.299272 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 25752 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 14435 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.783997 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5101096739000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.299272 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.393704 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.393704 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 14933 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.063651 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 25583 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 14948 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.711466 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.063651 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.378978 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.378978 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 97449 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 97449 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25750 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25750 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 98613 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 98613 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25588 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25588 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25752 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25752 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25752 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25752 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15315 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 15315 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15315 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15315 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15315 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15315 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 177860992 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 177860992 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 177860992 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 177860992 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 177860992 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 177860992 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41065 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41065 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25590 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25590 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25590 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25590 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15811 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15811 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15811 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15811 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15811 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15811 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183242996 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183242996 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183242996 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 183242996 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183242996 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 183242996 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41399 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41399 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41067 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41067 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41067 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41067 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372945 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372945 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372927 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.372927 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372927 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.372927 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11613.515638 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11613.515638 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11613.515638 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41401 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41401 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41401 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41401 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381917 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381917 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381899 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.381899 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381899 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.381899 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1022,177 +1001,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3318 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3318 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15315 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15315 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15315 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 15315 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15315 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 15315 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147213024 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147213024 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147213024 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147213024 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147213024 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147213024 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372945 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372945 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372927 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372927 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9612.342409 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3310 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3310 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15811 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15811 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15811 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 15811 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15811 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 15811 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159511522 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159511522 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159511522 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159511522 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159511522 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159511522 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381917 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381917 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381899 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381899 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112445 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64830.405135 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3843138 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176455 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.779706 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112684 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64825.802499 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3846196 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176714 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.765089 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50339.203670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.644782 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.444532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3208.377327 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11267.734824 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768115 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000223 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048956 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.171932 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989233 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64010 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 596 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52806 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976715 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35103909 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35103909 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69111 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12768 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 984459 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1335184 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2401522 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1585447 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1585447 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154410 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154410 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69111 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12768 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 984459 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1489594 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2555932 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69111 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12768 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 984459 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1489594 # number of overall hits -system.cpu.l2cache.overall_hits::total 2555932 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 62 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16359 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35824 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52251 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1504 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1504 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133327 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133327 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16359 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169151 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185578 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16359 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169151 # number of overall misses -system.cpu.l2cache.overall_misses::total 185578 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5303750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1250815250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2830285496 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4086871996 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17716796 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17716796 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9290586712 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9290586712 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5303750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1250815250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12120872208 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13377458708 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5303750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1250815250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12120872208 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13377458708 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69173 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12774 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1000818 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1371008 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2453773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1585447 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1585447 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1813 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1813 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287737 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287737 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69173 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12774 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1000818 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1658745 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2741510 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69173 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12774 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1000818 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1658745 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2741510 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000470 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016346 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026130 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021294 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.829564 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.829564 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463364 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.463364 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000470 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016346 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101975 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.067692 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000470 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016346 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101975 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.067692 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85544.354839 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77916.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76460.373495 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79005.289638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78216.148897 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11779.784574 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11779.784574 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69682.710269 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69682.710269 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72085.369537 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72085.369537 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.517179 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.137228 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3161.997282 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768450 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000237 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048248 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.172226 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989163 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64030 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3484 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5616 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54343 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977020 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 35101682 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 35101682 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67331 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13137 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 984666 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1336353 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2401487 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1585305 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1585305 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 326 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 326 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154346 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154346 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 67331 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 13137 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 984666 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1490699 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2555833 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 67331 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 13137 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 984666 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1490699 # number of overall hits +system.cpu.l2cache.overall_hits::total 2555833 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16391 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 35623 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52085 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1473 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1473 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133459 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133459 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16391 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169082 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185544 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16391 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169082 # number of overall misses +system.cpu.l2cache.overall_misses::total 185544 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6193250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 446000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1375483774 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3059797000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4441920024 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22673320 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 22673320 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10319199473 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10319199473 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6193250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1375483774 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13378996473 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14761119497 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6193250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 446000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1375483774 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13378996473 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14761119497 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001057 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1371976 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2453572 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1585305 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1585305 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67397 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 13142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1001057 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1659781 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2741377 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67397 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 13142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1001057 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1659781 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2741377 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000979 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000380 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021228 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818788 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463713 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.463713 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000979 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000380 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016374 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.067683 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000979 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000380 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016374 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.067683 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93837.121212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89200 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83917.013849 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85893.860708 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 85282.135432 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15392.613714 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15392.613714 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77321.120891 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77321.120891 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79555.897776 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79555.897776 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1201,99 +1180,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102890 # number of writebacks -system.cpu.l2cache.writebacks::total 102890 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 103019 # number of writebacks +system.cpu.l2cache.writebacks::total 103019 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 62 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16356 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35821 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52245 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1504 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1504 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133327 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133327 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16356 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 185572 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16356 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 185572 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4538750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1045537500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2387984748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3438452498 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15960982 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15960982 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7616458286 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7616458286 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4538750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1045537500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10004443034 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11054910784 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4538750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1045537500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10004443034 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11054910784 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89282348000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89282348000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2403570000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2403570000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91685918000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91685918000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026127 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021292 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.829564 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.829564 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463364 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463364 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067690 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.067690 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63923.789435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66664.379777 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65814.001302 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10612.355053 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10612.355053 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57126.150637 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57126.150637 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35622 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52081 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1473 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1473 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133459 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133459 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169081 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185540 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169081 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185540 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5361750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 383000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1170197226 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2615090750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3791032726 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27003455 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27003455 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8650755527 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8650755527 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5361750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170197226 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11265846277 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12441788253 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5361750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 383000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170197226 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11265846277 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12441788253 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88987317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88987317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2410942500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2410942500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91398260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91398260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021227 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818788 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818788 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463713 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463713 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067681 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067681 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76600 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71405.737491 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73412.238224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72791.089380 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18332.284453 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18332.284453 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64819.574004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64819.574004 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1301,69 +1280,69 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3074706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3074138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3070183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3069642 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287746 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287746 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 27 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2001753 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6129358 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 167702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8330220 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64052352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207821235 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1029888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5836480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278739955 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 59032 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4387424 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010858 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103635 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 1585305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46754 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123530 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8320756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64067648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207974818 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1052928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5614976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278710370 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 59545 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4387643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010865 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4339785 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47639 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4339973 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47670 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4387424 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4074051871 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4387643 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4071571970 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1505430236 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1506228195 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141534733 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3139390437 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22981484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 23723987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 114826620 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 112471118 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225722 # Transaction distribution -system.iobus.trans_dist::ReadResp 225722 # Transaction distribution -system.iobus.trans_dist::WriteReq 57753 # Transaction distribution -system.iobus.trans_dist::WriteResp 11033 # Transaction distribution +system.iobus.trans_dist::ReadReq 223900 # Transaction distribution +system.iobus.trans_dist::ReadResp 223900 # Transaction distribution +system.iobus.trans_dist::WriteReq 57738 # Transaction distribution +system.iobus.trans_dist::WriteResp 11018 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.trans_dist::MessageReq 1650 # Transaction distribution +system.iobus.trans_dist::MessageResp 1650 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1373,21 +1352,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 468004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 566576 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1397,19 +1376,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242122 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276590 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 240285 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3274757 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1421,7 +1400,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1439,54 +1418,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448363457 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 257352407 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460639000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 456986000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52378260 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50389253 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47584 # number of replacements -system.iocache.tags.tagsinuse 0.079092 # Cycle average of tags in use +system.iocache.tags.replacements 47582 # number of replacements +system.iocache.tags.tagsinuse 0.177916 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992999647000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079092 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004943 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.004943 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4993302485000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177916 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011120 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.011120 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428751 # Number of tag accesses -system.iocache.tags.data_accesses 428751 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses -system.iocache.ReadReq_misses::total 919 # number of ReadReq misses +system.iocache.tags.tag_accesses 428724 # Number of tag accesses +system.iocache.tags.data_accesses 428724 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses +system.iocache.ReadReq_misses::total 916 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses -system.iocache.demand_misses::total 919 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses -system.iocache.overall_misses::total 919 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149123196 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149123196 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12357582001 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12357582001 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 149123196 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 149123196 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 149123196 # number of overall miss cycles -system.iocache.overall_miss_latency::total 149123196 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses +system.iocache.demand_misses::total 916 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses +system.iocache.overall_misses::total 916 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144791938 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144791938 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8565273216 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8565273216 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144791938 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144791938 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144791938 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144791938 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1495,40 +1474,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162266.807399 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264503.039405 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264503.039405 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 162266.807399 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 162266.807399 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70647 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158069.801310 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158069.801310 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158069.801310 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29224 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9165 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4409 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.708347 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.628260 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101309696 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9928122021 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9928122021 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 101309696 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 101309696 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96734432 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6135821228 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6135821228 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 96734432 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 96734432 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1537,79 +1516,79 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110239.059848 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212502.611751 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212502.611751 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662612 # Transaction distribution -system.membus.trans_dist::ReadResp 662585 # Transaction distribution +system.membus.trans_dist::ReadReq 657690 # Transaction distribution +system.membus.trans_dist::ReadResp 657682 # Transaction distribution system.membus.trans_dist::WriteReq 13919 # Transaction distribution system.membus.trans_dist::WriteResp 13919 # Transaction distribution -system.membus.trans_dist::Writeback 149557 # Transaction distribution +system.membus.trans_dist::Writeback 149687 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2230 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1790 # Transaction distribution -system.membus.trans_dist::ReadExReq 133043 # Transaction distribution -system.membus.trans_dist::ReadExResp 133041 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 27 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476745 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141469 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141469 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1868288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242122 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550121 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18398848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20191091 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26202783 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1603 # Total snoops (count) -system.membus.snoop_fanout::samples 384714 # Request fanout histogram +system.membus.trans_dist::UpgradeReq 2233 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1752 # Transaction distribution +system.membus.trans_dist::ReadExReq 133182 # Transaction distribution +system.membus.trans_dist::ReadExResp 133180 # Transaction distribution +system.membus.trans_dist::MessageReq 1650 # Transaction distribution +system.membus.trans_dist::MessageResp 1650 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1714068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1858835 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240285 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18406720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20185442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26197226 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1640 # Total snoops (count) +system.membus.snoop_fanout::samples 384867 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 384714 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 384867 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 384714 # Request fanout histogram -system.membus.reqLayer0.occupancy 251770499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 384867 # Request fanout histogram +system.membus.reqLayer0.occupancy 357799000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583267500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388520500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1992294999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1203232654 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 33000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3156735730 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 55013740 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2208381292 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 51518747 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 79cf4b255..fa561f06e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,154 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144107 # Number of seconds simulated -sim_ticks 5144107123500 # Number of ticks simulated -final_tick 5144107123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.134221 # Number of seconds simulated +sim_ticks 5134220888000 # Number of ticks simulated +final_tick 5134220888000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 387693 # Simulator instruction rate (inst/s) -host_op_rate 770744 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8185899527 # Simulator tick rate (ticks/s) -host_mem_usage 958064 # Number of bytes of host memory used -host_seconds 628.41 # Real time elapsed on the host -sim_insts 243630211 # Number of instructions simulated -sim_ops 484343866 # Number of ops (including micro ops) simulated +host_inst_rate 274165 # Simulator instruction rate (inst/s) +host_op_rate 545049 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5772363280 # Simulator tick rate (ticks/s) +host_mem_usage 1013712 # Number of bytes of host memory used +host_seconds 889.45 # Real time elapsed on the host +sim_insts 243855553 # Number of instructions simulated +sim_ops 484792888 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 435328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5271168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 167488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2239424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 369088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2863936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 442496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5387840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 144896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1908224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 377856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3143424 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11377408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 435328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 167488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 369088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 971904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9177088 # Number of bytes written to this memory -system.physmem.bytes_written::total 9177088 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 82362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 36 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 44749 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11436096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 442496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 377856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9176704 # Number of bytes written to this memory +system.physmem.bytes_written::total 9176704 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 84185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2264 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 29816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 49116 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177772 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143392 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143392 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 84627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1024700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 435338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 71750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 556741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2211736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 84627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32559 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 71750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1784000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1784000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1784000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 84627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1024700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 435338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 71750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 556741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3995736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 88604 # Number of read requests accepted -system.physmem.writeReqs 101715 # Number of write requests accepted -system.physmem.readBursts 88604 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 101715 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5666496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4160 # Total number of bytes read from write queue -system.physmem.bytesWritten 6448384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5670656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6509760 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 65 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 959 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 894 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5172 # Per bank write bursts -system.physmem.perBankRdBursts::1 4675 # Per bank write bursts -system.physmem.perBankRdBursts::2 4614 # Per bank write bursts -system.physmem.perBankRdBursts::3 5517 # Per bank write bursts -system.physmem.perBankRdBursts::4 6171 # Per bank write bursts -system.physmem.perBankRdBursts::5 5192 # Per bank write bursts -system.physmem.perBankRdBursts::6 5194 # Per bank write bursts -system.physmem.perBankRdBursts::7 5097 # Per bank write bursts -system.physmem.perBankRdBursts::8 5481 # Per bank write bursts -system.physmem.perBankRdBursts::9 5563 # Per bank write bursts -system.physmem.perBankRdBursts::10 5214 # Per bank write bursts -system.physmem.perBankRdBursts::11 5694 # Per bank write bursts -system.physmem.perBankRdBursts::12 5834 # Per bank write bursts -system.physmem.perBankRdBursts::13 6887 # Per bank write bursts -system.physmem.perBankRdBursts::14 6277 # Per bank write bursts -system.physmem.perBankRdBursts::15 5957 # Per bank write bursts -system.physmem.perBankWrBursts::0 6561 # Per bank write bursts -system.physmem.perBankWrBursts::1 6098 # Per bank write bursts -system.physmem.perBankWrBursts::2 5964 # Per bank write bursts -system.physmem.perBankWrBursts::3 5948 # Per bank write bursts -system.physmem.perBankWrBursts::4 7233 # Per bank write bursts -system.physmem.perBankWrBursts::5 6043 # Per bank write bursts -system.physmem.perBankWrBursts::6 6495 # Per bank write bursts -system.physmem.perBankWrBursts::7 6502 # Per bank write bursts -system.physmem.perBankWrBursts::8 5629 # Per bank write bursts -system.physmem.perBankWrBursts::9 6174 # Per bank write bursts -system.physmem.perBankWrBursts::10 5473 # Per bank write bursts -system.physmem.perBankWrBursts::11 6467 # Per bank write bursts -system.physmem.perBankWrBursts::12 6126 # Per bank write bursts -system.physmem.perBankWrBursts::13 6747 # Per bank write bursts -system.physmem.perBankWrBursts::14 6614 # Per bank write bursts -system.physmem.perBankWrBursts::15 6682 # Per bank write bursts +system.physmem.num_reads::total 178689 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143386 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143386 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 86186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1049398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 371668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 612249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2227426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1787361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1787361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1787361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 86186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1049398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 371668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 612249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4014786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 87585 # Number of read requests accepted +system.physmem.writeReqs 96690 # Number of write requests accepted +system.physmem.readBursts 87585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96690 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5601728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue +system.physmem.bytesWritten 5458112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5605440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6188160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11390 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 914 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5700 # Per bank write bursts +system.physmem.perBankRdBursts::1 5150 # Per bank write bursts +system.physmem.perBankRdBursts::2 4887 # Per bank write bursts +system.physmem.perBankRdBursts::3 5253 # Per bank write bursts +system.physmem.perBankRdBursts::4 5094 # Per bank write bursts +system.physmem.perBankRdBursts::5 4483 # Per bank write bursts +system.physmem.perBankRdBursts::6 5146 # Per bank write bursts +system.physmem.perBankRdBursts::7 4650 # Per bank write bursts +system.physmem.perBankRdBursts::8 5914 # Per bank write bursts +system.physmem.perBankRdBursts::9 5792 # Per bank write bursts +system.physmem.perBankRdBursts::10 5352 # Per bank write bursts +system.physmem.perBankRdBursts::11 5127 # Per bank write bursts +system.physmem.perBankRdBursts::12 5714 # Per bank write bursts +system.physmem.perBankRdBursts::13 6636 # Per bank write bursts +system.physmem.perBankRdBursts::14 6391 # Per bank write bursts +system.physmem.perBankRdBursts::15 6238 # Per bank write bursts +system.physmem.perBankWrBursts::0 5924 # Per bank write bursts +system.physmem.perBankWrBursts::1 5309 # Per bank write bursts +system.physmem.perBankWrBursts::2 4960 # Per bank write bursts +system.physmem.perBankWrBursts::3 5064 # Per bank write bursts +system.physmem.perBankWrBursts::4 5666 # Per bank write bursts +system.physmem.perBankWrBursts::5 4857 # Per bank write bursts +system.physmem.perBankWrBursts::6 5361 # Per bank write bursts +system.physmem.perBankWrBursts::7 4594 # Per bank write bursts +system.physmem.perBankWrBursts::8 5275 # Per bank write bursts +system.physmem.perBankWrBursts::9 5755 # Per bank write bursts +system.physmem.perBankWrBursts::10 5195 # Per bank write bursts +system.physmem.perBankWrBursts::11 4824 # Per bank write bursts +system.physmem.perBankWrBursts::12 5173 # Per bank write bursts +system.physmem.perBankWrBursts::13 6061 # Per bank write bursts +system.physmem.perBankWrBursts::14 5642 # Per bank write bursts +system.physmem.perBankWrBursts::15 5623 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5140299284500 # Total gap between requests +system.physmem.numWrRetry 29 # Number of times write queue was full causing retry +system.physmem.totGap 5133220754000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 88604 # Read request sizes (log2) +system.physmem.readPktSize::6 87585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 101715 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96690 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 81722 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -165,455 +161,450 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 301.485168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.308895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.181387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15726 39.13% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9443 23.50% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4063 10.11% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2232 5.55% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1531 3.81% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1042 2.59% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 702 1.75% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 613 1.53% 87.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4832 12.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40184 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.412092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 185.359125 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4132 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.366626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.429404 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.022185 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 69 1.67% 1.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 9 0.22% 1.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 3347 80.94% 82.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 165 3.99% 86.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 114 2.76% 89.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 31 0.75% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 101 2.44% 92.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.27% 93.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 26 0.63% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 40 0.97% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 54 1.31% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 10 0.24% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 75 1.81% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.19% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 18 0.44% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 7 0.17% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.36% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.29% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 5 0.12% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.10% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4135 # Writes before turning the bus around for reads -system.physmem.totQLat 956383499 # Total ticks spent queuing -system.physmem.totMemAccLat 2616489749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 442695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10801.83 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 67 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 285.721608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 170.408148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 310.834116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15365 39.69% 39.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9282 23.98% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4036 10.43% 74.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2303 5.95% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1514 3.91% 83.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1118 2.89% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 653 1.69% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 582 1.50% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3855 9.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38708 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.124587 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 196.006736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3625 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3628 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3628 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.506891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.576033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 38.070070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 79 2.18% 2.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 3330 91.79% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 63 1.74% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 14 0.39% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 6 0.17% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 13 0.36% 96.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 6 0.17% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 13 0.36% 97.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.44% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.50% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.08% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 8 0.22% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.91% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.08% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.08% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 1 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.19% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3628 # Writes before turning the bus around for reads +system.physmem.totQLat 973946232 # Total ticks spent queuing +system.physmem.totMemAccLat 2615077482 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 437635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11127.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29551.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29877.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.42 # Average write queue length when enqueuing -system.physmem.readRowHits 70796 # Number of row buffer hits during reads -system.physmem.writeRowHits 78315 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.73 # Row buffer hit rate for writes -system.physmem.avgGap 27008860.31 # Average gap between requests -system.physmem.pageHitRate 78.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 147178080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 80086875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 324729600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 329469120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94792163085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2243751115500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2589991237140 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.838461 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3691094925500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128101480000 # Time in different power states +system.physmem.avgWrQLen 10.98 # Average write queue length when enqueuing +system.physmem.readRowHits 70024 # Number of row buffer hits during reads +system.physmem.writeRowHits 64077 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes +system.physmem.avgGap 27856305.81 # Average gap between requests +system.physmem.pageHitRate 77.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 138605040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 75351375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 314831400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 270442800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94326783165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2239415376750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2584559149170 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.799253 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3683386249962 # Time in different power states +system.physmem_0.memoryStateTime::REF 127820940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17513749500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17097201288 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 156612960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 365874600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 323429760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95660983305 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2237004864750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2584163561130 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.053818 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3689804823000 # Time in different power states -system.physmem_1.memoryStateTime::REF 128101480000 # Time in different power states +system.physmem_1.actEnergy 154027440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 83877750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 367863600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 282191040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95207179230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2235926942250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2582039839950 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.929569 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3682087997664 # Time in different power states +system.physmem_1.memoryStateTime::REF 127820940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18778765250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18395204336 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 906748886 # number of cpu cycles simulated +system.cpu0.numCycles 861071319 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71802590 # Number of instructions committed -system.cpu0.committedOps 146381299 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134255761 # Number of integer alu accesses +system.cpu0.committedInsts 71289400 # Number of instructions committed +system.cpu0.committedOps 145467698 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133359316 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 943296 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14239563 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134255761 # number of integer instructions +system.cpu0.num_func_calls 922812 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14140303 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133359316 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 246209877 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115427878 # number of times the integer registers were written +system.cpu0.num_int_register_reads 244470794 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114705006 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83592437 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55838323 # number of times the CC registers were written -system.cpu0.num_mem_refs 13658115 # number of memory refs -system.cpu0.num_load_insts 10127652 # Number of load instructions -system.cpu0.num_store_insts 3530463 # Number of store instructions -system.cpu0.num_idle_cycles 859556134.264708 # Number of idle cycles -system.cpu0.num_busy_cycles 47192751.735292 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052046 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947954 # Percentage of idle cycles -system.cpu0.Branches 15533640 # Number of branches fetched -system.cpu0.op_class::No_OpClass 89870 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132527069 90.54% 90.60% # Class of executed instruction -system.cpu0.op_class::IntMult 58535 0.04% 90.64% # Class of executed instruction -system.cpu0.op_class::IntDiv 49919 0.03% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::MemRead 10125945 6.92% 97.59% # Class of executed instruction -system.cpu0.op_class::MemWrite 3530463 2.41% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82965986 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55469495 # number of times the CC registers were written +system.cpu0.num_mem_refs 13497529 # number of memory refs +system.cpu0.num_load_insts 10019587 # Number of load instructions +system.cpu0.num_store_insts 3477942 # Number of store instructions +system.cpu0.num_idle_cycles 817633663.650796 # Number of idle cycles +system.cpu0.num_busy_cycles 43437655.349204 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050446 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949554 # Percentage of idle cycles +system.cpu0.Branches 15408320 # Number of branches fetched +system.cpu0.op_class::No_OpClass 89223 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 131776877 90.59% 90.65% # Class of executed instruction +system.cpu0.op_class::IntMult 58105 0.04% 90.69% # Class of executed instruction +system.cpu0.op_class::IntDiv 48148 0.03% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::MemRead 10017918 6.89% 97.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 3477942 2.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146381801 # Class of executed instruction +system.cpu0.op_class::total 145468213 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1639020 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19713831 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1639532 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.024060 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1637783 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999406 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19710876 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638295 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.031335 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.995226 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 275.897813 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 106.106411 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.253897 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.538863 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.207239 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.289579 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 344.626695 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.083132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.281816 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.673099 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.045084 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 235 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88616075 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88616075 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4923544 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2619910 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4021776 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11565230 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3397085 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1858074 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2831900 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8087059 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19915 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10654 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29231 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59800 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8320629 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4477984 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6853676 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19652289 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8340544 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4488638 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6882907 # number of overall hits -system.cpu0.dcache.overall_hits::total 19712089 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 358740 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 166586 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 774812 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1300138 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 129303 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 72150 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 124071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325524 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 150487 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 66279 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 189615 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406381 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 488043 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 238736 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 898883 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1625662 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 638530 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 305015 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1088498 # number of overall misses -system.cpu0.dcache.overall_misses::total 2032043 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2329828500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11922594046 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14252422546 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2798605810 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3955887575 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6754493385 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5128434310 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 15878481621 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21006915931 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5128434310 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 15878481621 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21006915931 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5282284 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2786496 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4796588 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12865368 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3526388 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1930224 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2955971 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8412583 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 170402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76933 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 218846 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466181 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8808672 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4716720 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7752559 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21277951 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8979074 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4793653 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7971405 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21744132 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067914 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059783 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.161534 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.101057 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036667 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037379 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041973 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038695 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.883129 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.861516 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.866431 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871724 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055405 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050615 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115947 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.076401 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071113 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063629 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136550 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093452 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13985.740098 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15387.725082 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10962.238275 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38788.715315 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31884.062956 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20749.601827 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21481.612786 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17664.681189 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12922.068629 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16813.711817 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14587.515660 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10337.830415 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 128988 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 88682212 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88682212 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4830179 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2466757 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4264396 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11561332 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3346491 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1735459 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3006073 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8088023 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19837 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10092 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29821 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 59750 # number of SoftPFReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8176670 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4202216 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7270469 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19649355 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8196507 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4212308 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7300290 # number of overall hits +system.cpu0.dcache.overall_hits::total 19709105 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 348359 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 159608 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 811619 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1319586 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 127641 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 64125 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 133967 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 325733 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145510 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 64697 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196344 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406551 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 476000 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 223733 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 945586 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1645319 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 621510 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 288430 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1141930 # number of overall misses +system.cpu0.dcache.overall_misses::total 2051870 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193925000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11673600356 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13867525356 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2608735779 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4432412697 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7041148476 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4802660779 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 16106013053 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 20908673832 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4802660779 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 16106013053 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 20908673832 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5178538 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2626365 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 5076015 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12880918 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3474132 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1799584 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3140040 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8413756 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165347 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74789 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226165 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 466301 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8652670 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4425949 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8216055 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21294674 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8818017 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4500738 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8442220 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21760975 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067270 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060771 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159893 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.102445 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036740 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035633 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042664 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038714 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.880028 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865060 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.868145 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871864 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055012 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050550 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115090 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.077264 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070482 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064085 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135264 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.094291 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13745.708235 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14383.103841 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10508.997031 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40682.039439 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 33085.854703 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21616.319120 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21466.036655 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17032.837894 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12707.975676 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16651.044548 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14104.203456 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10190.057768 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 161116 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27777 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19020 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.643698 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.470873 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1548363 # number of writebacks -system.cpu0.dcache.writebacks::total 1548363 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 50 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 354752 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 354802 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1695 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30847 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 32542 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 385599 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 387344 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1745 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 385599 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 387344 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 166536 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 420060 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 586596 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 70455 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 93224 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 163679 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 66278 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186071 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 252349 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 236991 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 513284 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 750275 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 303269 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 699355 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1002624 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1995417000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5681817065 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7677234065 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2564306918 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3209237662 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5773544580 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 908338500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2750087755 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3658426255 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4559723918 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8891054727 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13450778645 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5468062418 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11641142482 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17109204900 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30379634500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33000290500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63379925000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 574626500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 695015500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1269642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30954261000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33695306000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64649567000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059765 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087575 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045595 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036501 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031538 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019456 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.861503 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850237 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.541311 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050245 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.066208 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.035261 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063265 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087733 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.046110 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11981.895806 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13526.203554 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13087.770910 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36396.379505 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34425.015683 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35273.581706 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13704.977519 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14779.776295 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14497.486636 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19240.072062 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17321.901183 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17927.798001 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18030.403431 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16645.541223 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17064.427841 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1546722 # number of writebacks +system.cpu0.dcache.writebacks::total 1546722 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 374785 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 374834 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1569 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32139 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 33708 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1618 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 406924 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 408542 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1618 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 406924 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 408542 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159559 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 436834 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 596393 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62556 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 101828 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 164384 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64697 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 192960 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 257657 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 222115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 538662 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 760777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 286812 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 731622 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1018434 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1953809500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5644023259 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7597832759 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2418621221 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3692192265 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6110813486 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 904952750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2733042751 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3637995501 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4372430721 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9336215524 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13708646245 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5277383471 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12069258275 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17346641746 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30408890000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33050179000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63459069000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531811000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 800665000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1332476000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30940701000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33850844000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64791545000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060753 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086058 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046301 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034761 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032429 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019538 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865060 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.853182 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.552555 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050185 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065562 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.035726 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063726 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.046801 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.059821 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12920.292969 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12739.641074 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38663.297222 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36259.106189 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37174.016242 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13987.553519 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14163.778768 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.529068 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19685.436468 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17332.233430 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18019.270095 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18400.148777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16496.576477 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17032.661661 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -624,521 +615,521 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 869493 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.803035 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129984824 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 870005 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 149.406985 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149054236250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.476673 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 257.387173 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 106.939188 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286087 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.502709 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.208866 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997662 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 877463 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.822061 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128690361 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 877975 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 146.576339 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 150549344000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.387940 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 146.288168 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 89.145952 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.537867 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.285719 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.174113 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997699 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131747901 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131747901 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87329682 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39588904 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3066238 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129984824 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87329682 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39588904 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3066238 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129984824 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87329682 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39588904 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3066238 # number of overall hits -system.cpu0.icache.overall_hits::total 129984824 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 312920 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 172473 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 407665 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 893058 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 312920 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 172473 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 407665 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 893058 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 312920 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 172473 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 407665 # number of overall misses -system.cpu0.icache.overall_misses::total 893058 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2415923500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5732417941 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8148341441 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2415923500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5732417941 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8148341441 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2415923500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5732417941 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8148341441 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87642602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39761377 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3473903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130877882 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87642602 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39761377 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3473903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130877882 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87642602 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39761377 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3473903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130877882 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003570 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004338 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117351 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006824 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003570 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004338 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117351 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006824 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003570 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004338 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117351 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006824 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14007.546109 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14061.589641 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9124.089859 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14007.546109 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14061.589641 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9124.089859 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14007.546109 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14061.589641 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9124.089859 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4572 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 6 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 130472306 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 130472306 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 86685680 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38800184 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3204497 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 128690361 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86685680 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38800184 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3204497 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 128690361 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86685680 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38800184 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3204497 # number of overall hits +system.cpu0.icache.overall_hits::total 128690361 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 302042 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 162655 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 439255 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 903952 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 302042 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 162655 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 439255 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 903952 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 302042 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 162655 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 439255 # number of overall misses +system.cpu0.icache.overall_misses::total 903952 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2276697249 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6082026148 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8358723397 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2276697249 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 6082026148 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8358723397 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2276697249 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 6082026148 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8358723397 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 86987722 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38962839 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3643752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 129594313 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 86987722 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38962839 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3643752 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 129594313 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 86987722 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38962839 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3643752 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 129594313 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004175 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120550 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006975 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003472 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004175 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120550 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006975 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003472 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004175 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120550 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006975 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13997.093535 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13846.230886 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9246.866423 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9246.866423 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9246.866423 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5936 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 289 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.970954 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 6 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.539792 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23039 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23039 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23039 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23039 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23039 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23039 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 172473 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 384626 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 557099 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 172473 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 384626 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 557099 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 172473 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 384626 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 557099 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2070011500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4726513433 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6796524933 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2070011500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4726513433 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6796524933 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2070011500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4726513433 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6796524933 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004257 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004257 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004257 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.851253 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25959 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 25959 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 25959 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 25959 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 25959 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 25959 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162655 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 413296 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 575951 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 162655 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 413296 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 575951 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 162655 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 413296 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 575951 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2031893251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5207377551 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7239270802 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2031893251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5207377551 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7239270802 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2031893251 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5207377551 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7239270802 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004444 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004444 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004444 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12569.247735 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608020264 # number of cpu cycles simulated +system.cpu1.numCycles 2606018109 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35983855 # Number of instructions committed -system.cpu1.committedOps 69821911 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64889046 # Number of integer alu accesses +system.cpu1.committedInsts 35373738 # Number of instructions committed +system.cpu1.committedOps 68746890 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63819737 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 503439 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6569343 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64889046 # number of integer instructions +system.cpu1.num_func_calls 481772 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6496386 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63819737 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120388172 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55814326 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118130559 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54973369 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36581725 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27247591 # number of times the CC registers were written -system.cpu1.num_mem_refs 4980693 # number of memory refs -system.cpu1.num_load_insts 3049501 # Number of load instructions -system.cpu1.num_store_insts 1931192 # Number of store instructions -system.cpu1.num_idle_cycles 2477411639.002949 # Number of idle cycles -system.cpu1.num_busy_cycles 130608624.997051 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050080 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949920 # Percentage of idle cycles -system.cpu1.Branches 7257729 # Number of branches fetched -system.cpu1.op_class::No_OpClass 34768 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64752658 92.74% 92.79% # Class of executed instruction -system.cpu1.op_class::IntMult 32117 0.05% 92.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 23661 0.03% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::MemRead 3047883 4.37% 97.23% # Class of executed instruction -system.cpu1.op_class::MemWrite 1931192 2.77% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36098608 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26881383 # number of times the CC registers were written +system.cpu1.num_mem_refs 4684980 # number of memory refs +system.cpu1.num_load_insts 2884758 # Number of load instructions +system.cpu1.num_store_insts 1800222 # Number of store instructions +system.cpu1.num_idle_cycles 2483538175.555252 # Number of idle cycles +system.cpu1.num_busy_cycles 122479933.444748 # Number of busy cycles +system.cpu1.not_idle_fraction 0.046999 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.953001 # Percentage of idle cycles +system.cpu1.Branches 7152522 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34380 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 63978277 93.06% 93.11% # Class of executed instruction +system.cpu1.op_class::IntMult 29063 0.04% 93.16% # Class of executed instruction +system.cpu1.op_class::IntDiv 22112 0.03% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::MemRead 2883100 4.19% 97.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 1800222 2.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69822279 # Class of executed instruction +system.cpu1.op_class::total 68747154 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29145274 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29145274 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 322260 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26440523 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25789579 # Number of BTB hits +system.cpu2.branchPred.lookups 29503892 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29503892 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 342810 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26694805 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25976378 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.538082 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 584080 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63924 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153878746 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.308739 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 611666 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 68809 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155682865 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10764874 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 143615831 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29145274 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26373659 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 141609884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 675175 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 95795 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 6373 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7380 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 61565 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 20 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 458 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3473911 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 167436 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3564 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 152883285 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.850280 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.030640 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 11322292 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145393707 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29503892 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26588044 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 142785185 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 717310 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 102884 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8624 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 60469 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 854 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3643758 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 177822 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3817 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154648109 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.849994 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.031354 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97765346 63.95% 63.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 837203 0.55% 64.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23601513 15.44% 79.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 591420 0.39% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 819374 0.54% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 838216 0.55% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 577391 0.38% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 693159 0.45% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27159663 17.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98977108 64.00% 64.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 881864 0.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23689941 15.32% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 607646 0.39% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 853753 0.55% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 859687 0.56% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 584791 0.38% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 755278 0.49% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27438041 17.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 152883285 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189404 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.933305 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9834703 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93251994 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 21466938 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4884733 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 338239 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279965546 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 338239 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11923429 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 75993663 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4610925 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 24032799 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12877614 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278749384 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 221936 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5866894 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 51314 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4911660 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 333127303 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 607942521 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 373256279 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 196 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320819170 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12308133 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 159156 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160655 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 23900033 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6505190 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3599973 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 377004 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 316512 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276808275 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 423236 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274695170 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 101004 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8754938 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13676659 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 65243 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 152883285 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.796764 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.395757 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154648109 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189513 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.933910 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10277895 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 94004330 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 21519674 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4891128 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 359306 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283040141 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 359306 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12341484 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77022094 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4867618 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24062417 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12399480 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 281740718 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 206678 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5855345 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 68061 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4394741 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 336544944 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 615400877 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 377780143 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 207 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 323636169 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12908773 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 167322 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 168903 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 23920372 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6854331 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3831116 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 436605 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 369940 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 279698877 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 432383 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 277466645 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 109952 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 9178493 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 14257252 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68980 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154648109 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.794181 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.395462 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90394017 59.13% 59.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5385946 3.52% 62.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3961954 2.59% 65.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3603407 2.36% 67.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22510778 14.72% 82.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2513602 1.64% 83.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23841558 15.59% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 461559 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 210464 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91599661 59.23% 59.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5400101 3.49% 62.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3869243 2.50% 65.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3752650 2.43% 67.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22658386 14.65% 82.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2693281 1.74% 84.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23975807 15.50% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 476523 0.31% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 222457 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 152883285 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154648109 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1679391 85.86% 85.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 6 0.00% 85.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 133 0.01% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 216471 11.07% 96.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 59961 3.07% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1665704 85.56% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 217161 11.15% 96.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 64057 3.29% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 81534 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264357889 96.24% 96.27% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 55368 0.02% 96.29% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50253 0.02% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 68 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6828846 2.49% 98.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3321212 1.21% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 83075 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 266581381 96.08% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 59040 0.02% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 53621 0.02% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 87 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7156038 2.58% 98.73% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3533403 1.27% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274695170 # Type of FU issued -system.cpu2.iq.rate 1.785140 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1955962 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007120 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 704330322 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 285990572 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273107568 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 106 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 276569466 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 697735 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 277466645 # Type of FU issued +system.cpu2.iq.rate 1.782256 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1946922 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007017 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 711637991 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289314219 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275821613 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 281 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 279330355 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 137 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 727263 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1221587 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6074 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4844 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 639616 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1301667 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5946 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5330 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 686178 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755983 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21219 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 750303 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28695 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 338239 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70808815 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1780684 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277231511 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 42116 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6505190 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3599973 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 246009 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 189602 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1292389 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4844 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 181953 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 192646 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374599 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274123146 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6692505 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 521898 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 359306 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71000950 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2910946 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 280131260 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 44826 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6854348 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3831116 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 254274 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 173954 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2389293 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5330 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 193600 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 205490 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 399090 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276846611 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 7005762 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 563321 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9929733 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27833627 # Number of branches executed -system.cpu2.iew.exec_stores 3237228 # Number of stores executed -system.cpu2.iew.exec_rate 1.781423 # Inst execution rate -system.cpu2.iew.wb_sent 273932637 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273107674 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213006118 # num instructions producing a value -system.cpu2.iew.wb_consumers 349346589 # num instructions consuming a value +system.cpu2.iew.exec_refs 10447548 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28131020 # Number of branches executed +system.cpu2.iew.exec_stores 3441786 # Number of stores executed +system.cpu2.iew.exec_rate 1.778273 # Inst execution rate +system.cpu2.iew.wb_sent 276647008 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275821721 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215019240 # num instructions producing a value +system.cpu2.iew.wb_consumers 352722264 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.774824 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609727 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.771690 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609599 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9088854 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357993 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325291 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 151524726 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.769617 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.649272 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9550045 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 363403 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 345846 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153217834 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.765971 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.651639 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94238602 62.19% 62.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4221946 2.79% 64.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1274040 0.84% 65.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24556134 16.21% 82.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1017367 0.67% 82.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 681486 0.45% 83.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 477034 0.31% 83.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23101810 15.25% 98.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1956307 1.29% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95448328 62.30% 62.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4376826 2.86% 65.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1280143 0.84% 65.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24626260 16.07% 82.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 968124 0.63% 82.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 723433 0.47% 83.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 420249 0.27% 83.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23244515 15.17% 98.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2129956 1.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 151524726 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135843766 # Number of instructions committed -system.cpu2.commit.committedOps 268140656 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153217834 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137192415 # Number of instructions committed +system.cpu2.commit.committedOps 270578300 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8243960 # Number of memory references committed -system.cpu2.commit.loads 5283603 # Number of loads committed -system.cpu2.commit.membars 162116 # Number of memory barriers committed -system.cpu2.commit.branches 27422801 # Number of branches committed +system.cpu2.commit.refs 8697618 # Number of memory references committed +system.cpu2.commit.loads 5552680 # Number of loads committed +system.cpu2.commit.membars 162630 # Number of memory barriers committed +system.cpu2.commit.branches 27696347 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244944567 # Number of committed integer instructions. -system.cpu2.commit.function_calls 433353 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 47848 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 259747107 96.87% 96.89% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 53065 0.02% 96.91% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48699 0.02% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5283564 1.97% 98.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2960357 1.10% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 247309305 # Number of committed integer instructions. +system.cpu2.commit.function_calls 454335 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 48751 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 261723532 96.73% 96.75% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56607 0.02% 96.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 51834 0.02% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5552622 2.05% 98.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3144938 1.16% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 268140656 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1956307 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 270578300 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2129956 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 426769551 # The number of ROB reads -system.cpu2.rob.rob_writes 555823820 # The number of ROB writes -system.cpu2.timesIdled 116899 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 995461 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4917307163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135843766 # Number of Instructions Simulated -system.cpu2.committedOps 268140656 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.132763 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.132763 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882797 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882797 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364780652 # number of integer regfile reads -system.cpu2.int_regfile_writes 218921020 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73130 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139296056 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107100465 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89036481 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137201 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554570 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554570 # Transaction distribution +system.cpu2.rob.rob_reads 431186663 # The number of ROB reads +system.cpu2.rob.rob_writes 561693850 # The number of ROB writes +system.cpu2.timesIdled 124283 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1034756 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4900728082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137192415 # Number of Instructions Simulated +system.cpu2.committedOps 270578300 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.134777 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.134777 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.881230 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.881230 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 368834984 # number of integer regfile reads +system.cpu2.int_regfile_writes 221067360 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73020 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140711927 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108060819 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90227595 # number of misc regfile reads +system.cpu2.misc_regfile_writes 143035 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3553360 # Transaction distribution +system.iobus.trans_dist::ReadResp 3553360 # Transaction distribution system.iobus.trans_dist::WriteReq 57725 # Transaction distribution system.iobus.trans_dist::WriteResp 11005 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1681 # Transaction distribution -system.iobus.trans_dist::MessageResp 1681 # Transaction distribution +system.iobus.trans_dist::MessageReq 1679 # Transaction distribution +system.iobus.trans_dist::MessageResp 1679 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -1147,7 +1138,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1157,12 +1148,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129348 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7126912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7225528 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -1171,7 +1162,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541309 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1181,19 +1172,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570873 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2588568 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3569655 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6604187 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2698688 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4563000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5333000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1201,70 +1192,68 @@ system.iobus.reqLayer5.occupancy 758000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 141310000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 404000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 414000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 78000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10340000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10425000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 221126240 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 116029251 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 302697000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 300958000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 28304753 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 24266250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1088000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1136000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47566 # number of replacements -system.iocache.tags.tagsinuse 0.112009 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.081409 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47582 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571390009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112009 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007001 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007001 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000597695009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081409 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005088 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005088 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428589 # Number of tag accesses -system.iocache.tags.data_accesses 428589 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 901 # number of ReadReq misses -system.iocache.ReadReq_misses::total 901 # number of ReadReq misses +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 901 # number of demand (read+write) misses -system.iocache.demand_misses::total 901 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 901 # number of overall misses -system.iocache.overall_misses::total 901 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132764027 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132764027 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 6059046460 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6059046460 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132764027 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132764027 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132764027 # number of overall miss cycles -system.iocache.overall_miss_latency::total 132764027 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 901 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 901 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses +system.iocache.demand_misses::total 909 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses +system.iocache.overall_misses::total 909 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 125652013 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 125652013 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 3845868988 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 3845868988 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 125652013 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 125652013 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 125652013 # number of overall miss cycles +system.iocache.overall_miss_latency::total 125652013 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 901 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 901 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 901 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 901 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1273,325 +1262,311 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 147351.861265 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 129688.494435 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 129688.494435 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 147351.861265 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 147351.861265 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34598 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138231.037404 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 82317.401284 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 82317.401284 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138231.037404 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138231.037404 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 13512 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4497 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2030 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.693573 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.656158 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 738 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 23008 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 23008 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 738 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 738 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 738 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94361527 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 4862624466 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4862624466 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94361527 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94361527 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.819090 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.492466 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.492466 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.819090 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.819090 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127861.147696 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 211344.943759 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 211344.943759 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 745 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 745 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 21024 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 745 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 745 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 745 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 745 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86664503 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2752610998 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2752610998 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 86664503 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 86664503 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.819582 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.450000 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.450000 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.819582 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.819582 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 116328.191946 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130927.083238 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130927.083238 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104970 # number of replacements -system.l2c.tags.tagsinuse 64826.298792 # Cycle average of tags in use -system.l2c.tags.total_refs 3700737 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169148 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.878692 # Average number of references to valid blocks. +system.l2c.tags.replacements 105420 # number of replacements +system.l2c.tags.tagsinuse 64829.150073 # Cycle average of tags in use +system.l2c.tags.total_refs 3714265 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169452 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.919275 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51221.575879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131319 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1714.525389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5051.845543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 364.783966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1988.075845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.500719 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 853.175626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3622.680869 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.781579 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51423.363344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134649 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1822.192254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5065.443853 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 236.253380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1546.126379 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.729356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 913.877634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3810.029226 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.784658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.077085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030336 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000145 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013018 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.055278 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2747 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54646 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979279 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33928519 # Number of tag accesses -system.l2c.tags.data_accesses 33928519 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20269 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 306104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491683 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 12164 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6423 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 169856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 59393 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13568 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 378835 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 595825 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2292802 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.027804 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.077293 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003605 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023592 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013945 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.058136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989214 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64032 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 535 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53036 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977051 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 34034094 # Number of tag accesses +system.l2c.tags.data_accesses 34034094 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19379 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 295114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 477769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12495 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 160391 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 220397 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 66650 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 14282 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 407368 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 616656 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2308529 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1548363 # number of Writeback hits -system.l2c.Writeback_hits::total 1548363 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 100 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 101 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 272 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63359 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 39945 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 57961 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161265 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20269 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10934 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 306104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 555042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12164 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6423 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 169856 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 267695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 59393 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 378835 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 653786 # number of demand (read+write) hits -system.l2c.demand_hits::total 2454069 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20269 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10934 # number of overall hits -system.l2c.overall_hits::cpu0.inst 306104 # number of overall hits -system.l2c.overall_hits::cpu0.data 555042 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12164 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6423 # number of overall hits -system.l2c.overall_hits::cpu1.inst 169856 # number of overall hits -system.l2c.overall_hits::cpu1.data 267695 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 59393 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13568 # number of overall hits -system.l2c.overall_hits::cpu2.inst 378835 # number of overall hits -system.l2c.overall_hits::cpu2.data 653786 # number of overall hits -system.l2c.overall_hits::total 2454069 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6803 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 17544 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2617 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5064 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 36 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5767 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 10237 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48073 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 615 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 285 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 446 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1346 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 30166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 34786 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130181 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6803 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 82773 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2617 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 36 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5767 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 45023 # number of demand (read+write) misses -system.l2c.demand_misses::total 178254 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6803 # number of overall misses -system.l2c.overall_misses::cpu0.data 82773 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2617 # number of overall misses -system.l2c.overall_misses::cpu1.data 35230 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 36 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5767 # number of overall misses -system.l2c.overall_misses::cpu2.data 45023 # number of overall misses -system.l2c.overall_misses::total 178254 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 190653500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 384787000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2953999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 449712500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 795071749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1823253248 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3961367 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 5247781 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9209148 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2078566202 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2496913123 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4575479325 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 190653500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2463353202 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2953999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 449712500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3291984872 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6398732573 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 190653500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2463353202 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2953999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 449712500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3291984872 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6398732573 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 20269 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10936 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 312907 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 509227 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 12164 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6424 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 172473 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 232814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 59429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 13568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 384602 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 606062 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2340875 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_hits::writebacks 1546722 # number of Writeback hits +system.l2c.Writeback_hits::total 1546722 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 113 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 258 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58538 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36097 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 64817 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159452 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 19379 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10644 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 295114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 536307 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12495 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7386 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 160391 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256494 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 66650 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 14282 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 407368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 681473 # number of demand (read+write) hits +system.l2c.demand_hits::total 2467983 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 19379 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10644 # number of overall hits +system.l2c.overall_hits::cpu0.inst 295114 # number of overall hits +system.l2c.overall_hits::cpu0.data 536307 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12495 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7386 # number of overall hits +system.l2c.overall_hits::cpu1.inst 160391 # number of overall hits +system.l2c.overall_hits::cpu1.data 256494 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 66650 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 14282 # number of overall hits +system.l2c.overall_hits::cpu2.inst 407368 # number of overall hits +system.l2c.overall_hits::cpu2.data 681473 # number of overall hits +system.l2c.overall_hits::total 2467983 # number of overall hits +system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6915 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 16100 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2264 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3859 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 5904 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 13093 # number of ReadReq misses +system.l2c.ReadReq_misses::total 48182 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 632 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 257 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 496 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1385 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68358 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 26158 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 36472 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130988 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6915 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 84458 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2264 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 30017 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5904 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 49565 # number of demand (read+write) misses +system.l2c.demand_misses::total 179170 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6915 # number of overall misses +system.l2c.overall_misses::cpu0.data 84458 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2264 # number of overall misses +system.l2c.overall_misses::cpu1.data 30017 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5904 # number of overall misses +system.l2c.overall_misses::cpu2.data 49565 # number of overall misses +system.l2c.overall_misses::total 179170 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 185117250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 320324250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3767000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 506409000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1123352250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2138969750 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5734849 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 6109808 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11844657 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1967190465 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2891355862 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 4858546327 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 185117250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2287514715 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 3767000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 506409000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 4014708112 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6997516077 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 185117250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2287514715 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 3767000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 506409000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 4014708112 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6997516077 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 19379 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 10647 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 302029 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 493869 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 12495 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 162655 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 224256 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 66692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 14282 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 413272 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 629749 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2356711 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1548363 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1548363 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 715 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 356 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 547 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1618 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 128588 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 70111 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 92747 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 291446 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 20269 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10938 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 312907 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 637815 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 12164 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6424 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 172473 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 302925 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 59429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 13568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 384602 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 698809 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2632323 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 20269 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 312907 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 637815 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 12164 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6424 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 172473 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 302925 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 59429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 13568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 384602 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 698809 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2632323 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000366 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.021741 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.034452 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000156 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015173 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021751 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000606 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014995 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.016891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020536 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.860140 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800562 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.815356 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.831891 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.507271 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.430261 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.375063 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.446673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000366 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.021741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.129776 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000156 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.116299 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000606 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014995 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.064428 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.067717 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000366 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.021741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.129776 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000156 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.116299 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000606 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014995 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.064428 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.067717 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72851.929690 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75984.794629 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 82055.527778 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77980.319057 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 77666.479340 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 37926.762382 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 13899.533333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11766.325112 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6841.863299 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68904.269774 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71779.253809 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 35147.059287 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72851.929690 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69922.032416 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 82055.527778 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 77980.319057 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73117.848033 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 35896.712405 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72851.929690 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69922.032416 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 82055.527778 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 77980.319057 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73117.848033 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 35896.712405 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1546722 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1546722 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 745 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 585 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1643 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 126896 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 62255 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 101289 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 290440 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 19379 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 10649 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 302029 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 620765 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 12495 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7386 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 162655 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 286511 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 66692 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 14282 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 413272 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 731038 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2647153 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 19379 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 10649 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 302029 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 620765 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 12495 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7386 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 162655 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 286511 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 66692 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 14282 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 413272 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 731038 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2647153 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000470 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.022895 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.032600 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.013919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.014286 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.020791 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020445 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.848322 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.821086 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.847863 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.842970 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.538693 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.420175 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.360079 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.450998 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000470 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.022895 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.136055 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.013919 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.104767 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014286 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.067801 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.067684 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000470 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.022895 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.136055 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.013919 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.104767 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014286 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.067801 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.067684 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81765.569788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 83007.061415 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 85773.882114 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 85797.926373 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44393.544270 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 22314.587549 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12318.161290 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 8552.098917 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75204.161824 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79276.043595 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 37091.537599 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 39055.177078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 39055.177078 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1600,131 +1575,113 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96725 # number of writebacks -system.l2c.writebacks::total 96725 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2617 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 5064 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 36 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 5767 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 10236 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23721 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 285 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 446 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 731 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 30166 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 34786 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 64952 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2617 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 35230 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 36 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5767 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 45022 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 88673 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2617 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 35230 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 36 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5767 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 45022 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 88673 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 157432500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 321524500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 377524500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 667618251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1526670750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3450773 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 4577444 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 8028217 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1690819298 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2050981877 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3741801175 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 157432500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2012343798 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 377524500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2718600128 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5268471925 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 157432500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2012343798 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 377524500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2718600128 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5268471925 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27931457000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30246385500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58177842500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 534826000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 653150000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1187976000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28466283000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30899535500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59365818500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.016889 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.010133 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.800562 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.815356 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.451792 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.430261 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.375063 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.222861 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.116299 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.064427 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.033686 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.116299 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.064427 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.033686 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63492.199842 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65222.572392 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 64359.459972 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12107.975439 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10263.327354 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10982.512996 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56050.497182 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58959.980366 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57608.713742 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57120.175930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60383.815201 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59414.612396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57120.175930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60383.815201 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59414.612396 # average overall mshr miss latency +system.l2c.writebacks::writebacks 96719 # number of writebacks +system.l2c.writebacks::total 96719 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2264 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3859 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 42 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 5904 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 13093 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25162 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 257 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 496 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 753 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 26158 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 36472 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 62630 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2264 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 30017 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5904 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 49565 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 87792 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2264 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 30017 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5904 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 49565 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 87792 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 156732750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 272024750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 432457000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 959731250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1824184750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5165744 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 8859994 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14025738 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1640131535 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2435332138 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4075463673 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 156732750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1912156285 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 432457000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3395063388 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5899648423 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 156732750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1912156285 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 432457000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3395063388 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5899648423 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27747826000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30174191500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 57922017500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 492354000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 747099000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1239453000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28240180000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30921290500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59161470500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017208 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020791 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010677 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.821086 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.847863 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.458308 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420175 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.360079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.215638 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033165 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033165 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70490.995076 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73301.096005 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 72497.605516 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20100.171206 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17862.891129 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18626.478088 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62700.953246 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66772.651294 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65072.068865 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1735,66 +1692,66 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5122083 # Transaction distribution -system.membus.trans_dist::ReadResp 5122081 # Transaction distribution -system.membus.trans_dist::WriteReq 13936 # Transaction distribution -system.membus.trans_dist::WriteResp 13936 # Transaction distribution -system.membus.trans_dist::Writeback 143392 # Transaction distribution +system.membus.trans_dist::ReadReq 5119167 # Transaction distribution +system.membus.trans_dist::ReadResp 5119165 # Transaction distribution +system.membus.trans_dist::WriteReq 13931 # Transaction distribution +system.membus.trans_dist::WriteResp 13931 # Transaction distribution +system.membus.trans_dist::Writeback 143386 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1613 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1613 # Transaction distribution -system.membus.trans_dist::ReadExReq 129914 # Transaction distribution -system.membus.trans_dist::ReadExResp 129914 # Transaction distribution -system.membus.trans_dist::MessageReq 1681 # Transaction distribution -system.membus.trans_dist::MessageResp 1681 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1652 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution +system.membus.trans_dist::ReadExReq 130721 # Transaction distribution +system.membus.trans_dist::ReadExResp 130721 # Transaction distribution +system.membus.trans_dist::MessageReq 1679 # Transaction distribution +system.membus.trans_dist::MessageResp 1679 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3041102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457338 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10629668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141614 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141614 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10774644 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570873 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17560128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27220486 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6015552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33242762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 642 # Total snoops (count) -system.membus.snoop_fanout::samples 370612 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::total 10625356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10770337 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569655 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6082201 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17609408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27261264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6015616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33283596 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 789 # Total snoops (count) +system.membus.snoop_fanout::samples 371599 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370612 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 371599 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370612 # Request fanout histogram -system.membus.reqLayer0.occupancy 162893500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 371599 # Request fanout histogram +system.membus.reqLayer0.occupancy 233199000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314579500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 303775500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2176000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2272000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1055146498 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 587213160 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1088000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1136000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1708813357 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1313776839 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 29666247 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 24877750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1808,52 +1765,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7441673 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7441143 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13938 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13938 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1548363 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 23008 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1618 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1618 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291446 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291446 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7456393 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7455858 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13933 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13933 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1546722 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 21038 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1643 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1643 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 290440 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 290440 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004999 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72834 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207249 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17025096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55679680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213700038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 269360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 773664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270422742 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 67345 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4256875 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011187 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105175 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1755962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14994862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 74580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 223072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17048476 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56190016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213507600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 279632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270801176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69805 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4272022 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011152 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105014 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4209254 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47621 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4224379 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47643 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4256875 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5306709352 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4272022 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2506180983 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 318000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2510055059 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 865936683 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4923615960 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 25531897 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1938409360 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26348986 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 85751327 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96467647 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |