diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
3 files changed, 3693 insertions, 3663 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index d01497065..0f19127f8 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125918 # Number of seconds simulated -sim_ticks 5125917808500 # Number of ticks simulated -final_tick 5125917808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125948 # Number of seconds simulated +sim_ticks 5125948496500 # Number of ticks simulated +final_tick 5125948496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163224 # Simulator instruction rate (inst/s) -host_op_rate 322646 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2051147218 # Simulator tick rate (ticks/s) -host_mem_usage 753920 # Number of bytes of host memory used -host_seconds 2499.05 # Real time elapsed on the host -sim_insts 407905794 # Number of instructions simulated -sim_ops 806307064 # Number of ops (including micro ops) simulated +host_inst_rate 181287 # Simulator instruction rate (inst/s) +host_op_rate 358347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2277524092 # Simulator tick rate (ticks/s) +host_mem_usage 808864 # Number of bytes of host memory used +host_seconds 2250.67 # Real time elapsed on the host +sim_insts 408017153 # Number of instructions simulated +sim_ops 806519171 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1044736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10779456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1048640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10814912 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11857920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1044736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1044736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9592896 # Number of bytes written to this memory -system.physmem.bytes_written::total 9592896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 78 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11896448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1048640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1048640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9598912 # Number of bytes written to this memory +system.physmem.bytes_written::total 9598912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16385 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168983 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185280 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149889 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149889 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 974 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 185882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149983 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149983 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 203814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2102932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2109836 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2313326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1871449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1871449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1871449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2320829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1872612 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1872612 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1872612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2102932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 204575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2109836 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4184776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185280 # Number of read requests accepted -system.physmem.writeReqs 196609 # Number of write requests accepted -system.physmem.readBursts 185280 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196609 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11848512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 12427072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11857920 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12582976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2411 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1705 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11356 # Per bank write bursts -system.physmem.perBankRdBursts::1 10792 # Per bank write bursts -system.physmem.perBankRdBursts::2 11765 # Per bank write bursts -system.physmem.perBankRdBursts::3 11427 # Per bank write bursts -system.physmem.perBankRdBursts::4 11775 # Per bank write bursts -system.physmem.perBankRdBursts::5 11293 # Per bank write bursts -system.physmem.perBankRdBursts::6 11205 # Per bank write bursts -system.physmem.perBankRdBursts::7 11692 # Per bank write bursts -system.physmem.perBankRdBursts::8 11087 # Per bank write bursts -system.physmem.perBankRdBursts::9 11285 # Per bank write bursts -system.physmem.perBankRdBursts::10 11605 # Per bank write bursts -system.physmem.perBankRdBursts::11 12031 # Per bank write bursts -system.physmem.perBankRdBursts::12 11880 # Per bank write bursts -system.physmem.perBankRdBursts::13 12674 # Per bank write bursts -system.physmem.perBankRdBursts::14 11994 # Per bank write bursts -system.physmem.perBankRdBursts::15 11272 # Per bank write bursts -system.physmem.perBankWrBursts::0 13000 # Per bank write bursts -system.physmem.perBankWrBursts::1 12435 # Per bank write bursts -system.physmem.perBankWrBursts::2 11147 # Per bank write bursts -system.physmem.perBankWrBursts::3 11517 # Per bank write bursts -system.physmem.perBankWrBursts::4 12452 # Per bank write bursts -system.physmem.perBankWrBursts::5 12346 # Per bank write bursts -system.physmem.perBankWrBursts::6 11719 # Per bank write bursts -system.physmem.perBankWrBursts::7 11239 # Per bank write bursts -system.physmem.perBankWrBursts::8 12215 # Per bank write bursts -system.physmem.perBankWrBursts::9 12097 # Per bank write bursts -system.physmem.perBankWrBursts::10 12764 # Per bank write bursts -system.physmem.perBankWrBursts::11 12134 # Per bank write bursts -system.physmem.perBankWrBursts::12 12379 # Per bank write bursts -system.physmem.perBankWrBursts::13 12264 # Per bank write bursts -system.physmem.perBankWrBursts::14 12219 # Per bank write bursts -system.physmem.perBankWrBursts::15 12246 # Per bank write bursts +system.physmem.bw_total::total 4193440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185882 # Number of read requests accepted +system.physmem.writeReqs 196703 # Number of write requests accepted +system.physmem.readBursts 185882 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196703 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11884864 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue +system.physmem.bytesWritten 12459008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11896448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12588992 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2006 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1725 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11442 # Per bank write bursts +system.physmem.perBankRdBursts::1 11010 # Per bank write bursts +system.physmem.perBankRdBursts::2 11990 # Per bank write bursts +system.physmem.perBankRdBursts::3 11673 # Per bank write bursts +system.physmem.perBankRdBursts::4 12100 # Per bank write bursts +system.physmem.perBankRdBursts::5 11243 # Per bank write bursts +system.physmem.perBankRdBursts::6 11527 # Per bank write bursts +system.physmem.perBankRdBursts::7 11544 # Per bank write bursts +system.physmem.perBankRdBursts::8 11275 # Per bank write bursts +system.physmem.perBankRdBursts::9 11901 # Per bank write bursts +system.physmem.perBankRdBursts::10 11758 # Per bank write bursts +system.physmem.perBankRdBursts::11 11788 # Per bank write bursts +system.physmem.perBankRdBursts::12 11617 # Per bank write bursts +system.physmem.perBankRdBursts::13 12244 # Per bank write bursts +system.physmem.perBankRdBursts::14 11799 # Per bank write bursts +system.physmem.perBankRdBursts::15 10790 # Per bank write bursts +system.physmem.perBankWrBursts::0 14290 # Per bank write bursts +system.physmem.perBankWrBursts::1 13466 # Per bank write bursts +system.physmem.perBankWrBursts::2 12356 # Per bank write bursts +system.physmem.perBankWrBursts::3 11306 # Per bank write bursts +system.physmem.perBankWrBursts::4 11781 # Per bank write bursts +system.physmem.perBankWrBursts::5 11472 # Per bank write bursts +system.physmem.perBankWrBursts::6 11444 # Per bank write bursts +system.physmem.perBankWrBursts::7 11849 # Per bank write bursts +system.physmem.perBankWrBursts::8 11105 # Per bank write bursts +system.physmem.perBankWrBursts::9 11337 # Per bank write bursts +system.physmem.perBankWrBursts::10 12902 # Per bank write bursts +system.physmem.perBankWrBursts::11 12297 # Per bank write bursts +system.physmem.perBankWrBursts::12 12359 # Per bank write bursts +system.physmem.perBankWrBursts::13 12104 # Per bank write bursts +system.physmem.perBankWrBursts::14 12504 # Per bank write bursts +system.physmem.perBankWrBursts::15 12100 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5125917756500 # Total gap between requests +system.physmem.totGap 5125948445000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185280 # Read request sizes (log2) +system.physmem.readPktSize::6 185882 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196609 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196703 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,435 +156,440 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11040 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.738348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.730188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.091209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27875 37.17% 37.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17344 23.13% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7346 9.80% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4205 5.61% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3044 4.06% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1991 2.66% 82.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1466 1.96% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1106 1.47% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10608 14.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74985 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7802 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.727634 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.765031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7801 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 75254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.488559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.903299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.428888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27891 37.06% 37.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17298 22.99% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7596 10.09% 70.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4208 5.59% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3159 4.20% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2000 2.66% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1345 1.79% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1163 1.55% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10594 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75254 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7808 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.780866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.702276 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7807 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7802 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.887593 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.377135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.103132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6364 81.57% 81.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 53 0.68% 82.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.28% 82.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 275 3.52% 86.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 179 2.29% 88.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 0.68% 89.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 27 0.35% 89.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 51 0.65% 90.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 164 2.10% 92.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.22% 92.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.17% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.18% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 32 0.41% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 25 0.32% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.09% 93.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 50 0.64% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 101 1.29% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 9 0.12% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 29 0.37% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 150 1.92% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 8 0.10% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.09% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 28 0.36% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.05% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.14% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.05% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 23 0.29% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.09% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 14 0.18% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.13% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.12% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7802 # Writes before turning the bus around for reads -system.physmem.totQLat 2011030750 # Total ticks spent queuing -system.physmem.totMemAccLat 5482274500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 925665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10862.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7808 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.932377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.361157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.539970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6379 81.70% 81.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 49 0.63% 82.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 9 0.12% 82.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 259 3.32% 85.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 187 2.39% 88.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 53 0.68% 88.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 34 0.44% 89.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 61 0.78% 90.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 178 2.28% 92.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.24% 92.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 13 0.17% 92.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.18% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 27 0.35% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.24% 93.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 50 0.64% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 97 1.24% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.10% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 20 0.26% 95.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 156 2.00% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 7 0.09% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 10 0.13% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 29 0.37% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.14% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.05% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.20% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 10 0.13% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.08% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.09% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.14% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.13% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 7 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7808 # Writes before turning the bus around for reads +system.physmem.totQLat 1993300749 # Total ticks spent queuing +system.physmem.totMemAccLat 5475194499 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 928505000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10733.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29612.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29483.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.38 # Average write queue length when enqueuing -system.physmem.readRowHits 151985 # Number of row buffer hits during reads -system.physmem.writeRowHits 152335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.44 # Row buffer hit rate for writes -system.physmem.avgGap 13422533.14 # Average gap between requests -system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4919402035500 # Time in different power states -system.physmem.memoryStateTime::REF 171165540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35350129500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 274957200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 291929400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 150026250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 159286875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 712179000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 731850600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 621140400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 637100640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 334799796240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 334799796240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 129444240060 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 129652397505 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2962001074500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2961818480250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3428003413650 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3428090841510 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.759392 # Core power per rank (mW) -system.physmem.averagePower::1 668.776448 # Core power per rank (mW) -system.cpu.branchPred.lookups 86891854 # Number of BP lookups -system.cpu.branchPred.condPredicted 86891854 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 902474 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80057154 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78172464 # Number of BTB hits +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.04 # Average write queue length when enqueuing +system.physmem.readRowHits 152642 # Number of row buffer hits during reads +system.physmem.writeRowHits 152476 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.31 # Row buffer hit rate for writes +system.physmem.avgGap 13398195.03 # Average gap between requests +system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279704880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152616750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 721718400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 634806720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129444104115 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2962019880750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3428054662095 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.765327 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4927513863750 # Time in different power states +system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27267949750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 289215360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 157806000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726741600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 626667840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129734124390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2961765477000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3428101862670 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.774535 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4927089550750 # Time in different power states +system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27689450500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 86963954 # Number of BP lookups +system.cpu.branchPred.condPredicted 86963954 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 905408 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80060833 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78220075 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.645819 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1556145 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178539 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.700801 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1554669 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179026 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449528542 # number of cpu cycles simulated +system.cpu.numCycles 449722784 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27579139 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429063602 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86891854 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79728609 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417924990 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1892404 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 141641 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 49747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 210937 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 127048 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 749 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9185584 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 447344 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4767 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446980453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051866 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27725020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429300438 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86963954 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79774744 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417978242 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1899598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 143976 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 49214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 212054 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 124897 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 365 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9198894 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 449574 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4910 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 447183567 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281454432 62.97% 62.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2285018 0.51% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72162718 16.14% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1595292 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2151182 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2328836 0.52% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1532887 0.34% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1872269 0.42% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81597819 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281562684 62.96% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2296710 0.51% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72185404 16.14% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1608090 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2152491 0.48% 80.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2328628 0.52% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1534045 0.34% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1900420 0.42% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81615095 18.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446980453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193296 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954475 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23006879 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264875775 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150713064 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7438533 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 946202 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838427175 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 946202 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25861517 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223289477 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13277674 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154607234 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 28998349 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834936902 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 476513 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12412504 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 177326 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13726812 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997336716 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1813473834 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114859292 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964283425 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33053286 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468997 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473016 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39075310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17327574 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10191135 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1313699 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1076527 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829405798 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1211413 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824144334 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 238741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23374016 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36157635 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 155810 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446980453 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843804 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418028 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 447183567 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954589 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23075597 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264910108 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150816162 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7431901 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 949799 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838865197 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 949799 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25926245 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223342995 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13219671 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154710115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29034742 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 835373495 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 478818 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12412845 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 182552 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13765619 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997850152 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1814454577 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1115386152 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 142 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964539686 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33310464 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 468855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 472576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 39019315 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17353635 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10197147 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1310615 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1095058 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829813890 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1210662 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824509848 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 239912 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23585262 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36379120 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 154680 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 447183567 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418075 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262751782 58.78% 58.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13860127 3.10% 61.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10088289 2.26% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6929216 1.55% 65.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74323701 16.63% 82.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4464363 1.00% 83.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72802131 16.29% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1196176 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 564668 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262867260 58.78% 58.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13875410 3.10% 61.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10102524 2.26% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6917845 1.55% 65.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74366987 16.63% 82.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4460507 1.00% 83.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72819289 16.28% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1200322 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573423 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446980453 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 447183567 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1984017 71.87% 71.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 212 0.01% 71.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1649 0.06% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 613790 22.24% 94.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160788 5.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1986412 71.97% 71.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 252 0.01% 71.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1233 0.04% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 612541 22.19% 94.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159591 5.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 292283 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795766200 96.56% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150572 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125282 0.02% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 8 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18411850 2.23% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9398139 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 292966 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796097417 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150721 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125468 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18437939 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9405337 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824144334 # Type of FU issued -system.cpu.iq.rate 1.833353 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2760456 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2098268090 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854003641 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819590055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 270 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 824509848 # Type of FU issued +system.cpu.iq.rate 1.833374 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2760029 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2099202980 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854622338 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819935754 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826612402 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1877597 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 826976810 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1879265 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3329866 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14364 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14470 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1763076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3349902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15405 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14537 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1763571 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224552 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 71468 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 72078 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 946202 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205595274 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9411486 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830617211 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 184433 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17327584 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10191135 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 714161 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 416193 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8093117 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14470 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 516905 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 536436 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1053341 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822534076 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18016449 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1476395 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 949799 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205606066 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9444034 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831024552 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 186671 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17353635 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10197147 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 713788 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 414805 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8129418 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14537 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 518368 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 539118 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1057486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822883825 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18037381 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1492626 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27187129 # number of memory reference insts executed -system.cpu.iew.exec_branches 83286990 # Number of branches executed -system.cpu.iew.exec_stores 9170680 # Number of stores executed -system.cpu.iew.exec_rate 1.829771 # Inst execution rate -system.cpu.iew.wb_sent 822027813 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819590117 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640953314 # num instructions producing a value -system.cpu.iew.wb_consumers 1050450596 # num instructions consuming a value +system.cpu.iew.exec_refs 27216272 # number of memory reference insts executed +system.cpu.iew.exec_branches 83330623 # Number of branches executed +system.cpu.iew.exec_stores 9178891 # Number of stores executed +system.cpu.iew.exec_rate 1.829758 # Inst execution rate +system.cpu.iew.wb_sent 822374066 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819935816 # cumulative count of insts written-back +system.cpu.iew.wb_producers 641195588 # num instructions producing a value +system.cpu.iew.wb_consumers 1050795800 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610170 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823203 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610200 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24215626 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1055602 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443339838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818711 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675515 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24410170 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1055982 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 917776 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443513895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675053 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272569121 61.48% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11207092 2.53% 64.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3543073 0.80% 64.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74545535 16.81% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2433206 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1610406 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 913346 0.21% 82.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71032181 16.02% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5485878 1.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272662791 61.48% 61.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11205596 2.53% 64.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3584252 0.81% 64.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74566158 16.81% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2433850 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1609395 0.36% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 952580 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71045442 16.02% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5453831 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443339838 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407905794 # Number of instructions committed -system.cpu.commit.committedOps 806307064 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443513895 # Number of insts commited each cycle +system.cpu.commit.committedInsts 408017153 # Number of instructions committed +system.cpu.commit.committedOps 806519171 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22425775 # Number of memory references committed -system.cpu.commit.loads 13997716 # Number of loads committed -system.cpu.commit.membars 475203 # Number of memory barriers committed -system.cpu.commit.branches 82185787 # Number of branches committed +system.cpu.commit.refs 22437308 # Number of memory references committed +system.cpu.commit.loads 14003732 # Number of loads committed +system.cpu.commit.membars 475345 # Number of memory barriers committed +system.cpu.commit.branches 82208289 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735131032 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155610 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174231 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783440615 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144913 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121530 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735327062 # Number of committed integer instructions. +system.cpu.commit.function_calls 1156001 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174296 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783640915 97.16% 97.18% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 145051 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121601 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -611,167 +616,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13997716 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8428059 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14003732 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8433576 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806307064 # Class of committed instruction -system.cpu.commit.bw_lim_events 5485878 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806519171 # Class of committed instruction +system.cpu.commit.bw_lim_events 5453831 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268298437 # The number of ROB reads -system.cpu.rob.rob_writes 1664703185 # The number of ROB writes -system.cpu.timesIdled 295137 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2548089 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9802307300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407905794 # Number of Instructions Simulated -system.cpu.committedOps 806307064 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.102040 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102040 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907408 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907408 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092406866 # number of integer regfile reads -system.cpu.int_regfile_writes 656005719 # number of integer regfile writes +system.cpu.rob.rob_reads 1268911189 # The number of ROB reads +system.cpu.rob.rob_writes 1665544826 # The number of ROB writes +system.cpu.timesIdled 297395 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2539217 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9802174458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 408017153 # Number of Instructions Simulated +system.cpu.committedOps 806519171 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.102215 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102215 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907264 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907264 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092796597 # number of integer regfile reads +system.cpu.int_regfile_writes 656284247 # number of integer regfile writes system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.cc_regfile_reads 416194474 # number of cc regfile reads -system.cpu.cc_regfile_writes 322040205 # number of cc regfile writes -system.cpu.misc_regfile_reads 265569258 # number of misc regfile reads -system.cpu.misc_regfile_writes 402671 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1659070 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.990007 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19130419 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659582 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.527251 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 416355955 # number of cc regfile reads +system.cpu.cc_regfile_writes 322152728 # number of cc regfile writes +system.cpu.misc_regfile_reads 265715662 # number of misc regfile reads +system.cpu.misc_regfile_writes 402877 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1660514 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996956 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19150908 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1661026 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.529565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.990007 # Average occupied blocks per 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for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863304 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.863304 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100519 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100519 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117091 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117091 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.667088 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.667088 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38504.067548 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38504.067548 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 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(read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23476600655 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29068213412 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29068213412 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390347000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390347000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564142000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564142000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954489000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954489000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853633 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853633 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059402 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.059402 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076707 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076707 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12643.047382 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12643.047382 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38624.939375 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38624.939375 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13875.550737 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13875.550737 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18623.780891 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18623.780891 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.687433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.687433 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076687 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076687 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12628.891471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12628.891471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38737.787807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38737.787807 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.138999 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.138999 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18627.905799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18627.905799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17476.976058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17476.976058 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -779,58 +784,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73854 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.812426 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 117340 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73869 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.588488 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812426 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988277 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988277 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 73235 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.785723 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 116281 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 73250 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.587454 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785723 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986608 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986608 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 459584 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 459584 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117385 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 117385 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117385 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 117385 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117385 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 117385 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74938 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74938 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74938 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74938 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74938 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74938 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 912423463 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 912423463 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 912423463 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 912423463 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 912423463 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 912423463 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192323 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 192323 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192323 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 192323 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192323 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 192323 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389647 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389647 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389647 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389647 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389647 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389647 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12175.711428 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12175.711428 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12175.711428 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12175.711428 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12175.711428 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12175.711428 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 455451 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 455451 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116283 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 116283 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116283 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 116283 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116283 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 116283 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74295 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 74295 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74295 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 74295 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74295 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 74295 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 915742192 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 915742192 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 915742192 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 915742192 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 915742192 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 915742192 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190578 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 190578 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190578 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 190578 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 190578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389840 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389840 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389840 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389840 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389840 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389840 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12325.758019 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12325.758019 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12325.758019 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12325.758019 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12325.758019 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12325.758019 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,180 +844,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 19615 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 19615 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74938 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74938 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74938 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 74938 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74938 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 74938 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762426693 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762426693 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762426693 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762426693 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762426693 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762426693 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389647 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389647 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389647 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389647 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389647 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389647 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10174.099829 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10174.099829 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10174.099829 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20236 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20236 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74295 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74295 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74295 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 74295 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74295 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 74295 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 767004478 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 767004478 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 767004478 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 767004478 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 767004478 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 767004478 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389840 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389840 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389840 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10323.769810 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 996223 # number of replacements -system.cpu.icache.tags.tagsinuse 510.034964 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8125334 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 996735 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.151950 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.034964 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996162 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1000725 # number of replacements +system.cpu.icache.tags.tagsinuse 510.147155 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8133580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1001237 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.123531 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147645528250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.147155 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996381 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996381 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10182364 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10182364 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8125334 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8125334 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8125334 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8125334 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8125334 # number of overall hits -system.cpu.icache.overall_hits::total 8125334 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060246 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060246 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060246 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060246 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060246 # number of overall misses -system.cpu.icache.overall_misses::total 1060246 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14710988702 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14710988702 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14710988702 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14710988702 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14710988702 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14710988702 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9185580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9185580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9185580 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9185580 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9185580 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9185580 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13875.071165 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13875.071165 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13875.071165 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13875.071165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13875.071165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13875.071165 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8852 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10200177 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10200177 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8133580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8133580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8133580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8133580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8133580 # number of overall hits +system.cpu.icache.overall_hits::total 8133580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065313 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065313 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1065313 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1065313 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1065313 # number of overall misses +system.cpu.icache.overall_misses::total 1065313 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14771324125 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14771324125 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14771324125 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14771324125 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14771324125 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14771324125 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9198893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9198893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9198893 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9198893 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9198893 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9198893 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115809 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.115809 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.115809 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.115809 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.115809 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.115809 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.712823 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13865.712823 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.712823 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13865.712823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.712823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13865.712823 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6681 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 268 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.408638 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.929104 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63462 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63462 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63462 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63462 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63462 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63462 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 996784 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 996784 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 996784 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 996784 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 996784 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 996784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12075236643 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12075236643 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12075236643 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12075236643 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12075236643 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12075236643 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108516 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108516 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108516 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12114.195897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12114.195897 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12114.195897 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12114.195897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12114.195897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12114.195897 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 64029 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 64029 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 64029 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 64029 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 64029 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 64029 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001284 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1001284 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1001284 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1001284 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1001284 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1001284 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12122903243 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12122903243 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12122903243 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12122903243 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12122903243 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12122903243 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108848 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108848 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108848 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12107.357396 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12107.357396 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12107.357396 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12107.357396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12107.357396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12107.357396 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13757 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.017843 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26179 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13772 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.900886 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104067070500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017843 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376115 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376115 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 14176 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.015804 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 26673 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 14191 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.879572 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5101167924000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.015804 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375988 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375988 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 96280 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 96280 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26178 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26178 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 98532 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 98532 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26674 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26674 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26180 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26180 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26180 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26180 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14640 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14640 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14640 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14640 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14640 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14640 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168910997 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168910997 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168910997 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 168910997 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168910997 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 168910997 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40818 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 40818 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26676 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26676 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26676 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26676 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15060 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15060 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15060 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15060 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15060 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15060 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174774993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174774993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174774993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 174774993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174774993 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 174774993 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41734 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41734 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40820 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 40820 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40820 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 40820 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358665 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358665 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358648 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.358648 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358648 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.358648 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11537.636407 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11537.636407 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11537.636407 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11537.636407 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11537.636407 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11537.636407 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41736 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41736 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41736 # number of overall (read+write) accesses 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# average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11605.245219 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11605.245219 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11605.245219 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1021,177 +1026,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 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accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9603.787052 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9603.787052 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9603.787052 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 113048 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64817.930454 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3838289 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 177093 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.673861 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 113005 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.841328 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3843950 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 177067 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.709014 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50426.330308 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.730844 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.138507 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3266.844648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11101.886147 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769445 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50385.421591 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.865695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.131540 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3266.822655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11149.599847 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768821 # 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number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16326 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169384 # number of overall misses -system.cpu.l2cache.overall_misses::total 185794 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6504500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 472000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1249428250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2850151495 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4106556245 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17517303 # number of UpgradeReq miss cycles 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rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016378 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102099 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067931 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001161 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016378 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102099 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.067931 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63992.327248 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67021.734201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66081.951717 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10672.514583 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10672.514583 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57252.964800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57252.964800 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63992.327248 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59322.733703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59738.139997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63992.327248 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59322.733703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59738.139997 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16385 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169928 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 186384 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 407000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1043304250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2392591752 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3441599502 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15547443 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15547443 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7667598282 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7667598282 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5296500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 407000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1043304250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10060190034 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11109197784 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5296500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 407000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1043304250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10060190034 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11109197784 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275614000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275614000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397124500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397124500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672738500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672738500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000478 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.831154 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.831154 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.466352 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.466352 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000478 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102338 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067972 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000478 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102338 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067972 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63674.351541 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66724.071393 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65787.351416 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10634.365937 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10634.365937 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57191.006802 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57191.006802 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63674.351541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59202.662504 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59603.816765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63674.351541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59202.662504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59603.816765 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1300,63 +1305,63 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3068576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3068035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1583282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3074514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3073974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1584244 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 12 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1993478 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130100 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29738 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 161735 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8315051 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63788416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207873825 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 966272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5555008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278183521 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 59487 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4379111 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010877 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103722 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6133560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162399 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8328931 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64075456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207996475 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 988736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5638656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278699323 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 58087 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4385762 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103651 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4331481 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47630 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4338126 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47636 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4379111 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4067623882 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4385762 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4071958893 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 571500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1499268850 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1506070002 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141964932 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3144166318 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 21966489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 22600980 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 112467385 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 111516357 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225657 # Transaction distribution -system.iobus.trans_dist::ReadResp 225657 # Transaction distribution -system.iobus.trans_dist::WriteReq 57676 # Transaction distribution -system.iobus.trans_dist::WriteResp 10956 # Transaction distribution +system.iobus.trans_dist::ReadReq 225687 # Transaction distribution +system.iobus.trans_dist::ReadResp 225687 # Transaction distribution +system.iobus.trans_dist::WriteReq 57721 # Transaction distribution +system.iobus.trans_dist::WriteResp 11001 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1641 # Transaction distribution -system.iobus.trans_dist::MessageResp 1641 # Transaction distribution +system.iobus.trans_dist::MessageReq 1644 # Transaction distribution +system.iobus.trans_dist::MessageResp 1644 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -1372,15 +1377,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471406 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 570104 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -1396,19 +1401,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 241980 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276506 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1438,54 +1443,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448438152 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448361200 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460450000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52358513 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52371753 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.091509 # Cycle average of tags in use +system.iocache.tags.replacements 47581 # number of replacements +system.iocache.tags.tagsinuse 0.091546 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47597 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992976927000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091509 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005719 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005719 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992992715000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091546 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005722 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005722 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428670 # Number of tag accesses -system.iocache.tags.data_accesses 428670 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.tag_accesses 428724 # Number of tag accesses +system.iocache.tags.data_accesses 428724 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses +system.iocache.ReadReq_misses::total 916 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses -system.iocache.demand_misses::total 910 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses -system.iocache.overall_misses::total 910 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151600663 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 151600663 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12348426976 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12348426976 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 151600663 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 151600663 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 151600663 # number of overall miss cycles -system.iocache.overall_miss_latency::total 151600663 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses +system.iocache.demand_misses::total 916 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses +system.iocache.overall_misses::total 916 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149161446 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149161446 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12345702001 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12345702001 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 149161446 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 149161446 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 149161446 # number of overall miss cycles +system.iocache.overall_miss_latency::total 149161446 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1494,40 +1499,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 166594.135165 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264307.084247 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264307.084247 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 166594.135165 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 166594.135165 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70653 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162840.006550 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264248.758583 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264248.758583 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 162840.006550 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 162840.006550 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70237 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9154 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9120 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.718265 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.701425 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104259663 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918961002 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918961002 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 104259663 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 104259663 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101504946 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9916256007 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9916256007 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 101504946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 101504946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1536,79 +1541,79 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 114571.058242 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212306.528296 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212306.528296 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 114571.058242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 114571.058242 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110813.259825 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212248.630287 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212248.630287 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662598 # Transaction distribution -system.membus.trans_dist::ReadResp 662586 # Transaction distribution -system.membus.trans_dist::WriteReq 13841 # Transaction distribution -system.membus.trans_dist::WriteResp 13841 # Transaction distribution -system.membus.trans_dist::Writeback 149889 # Transaction distribution +system.membus.trans_dist::ReadReq 662646 # Transaction distribution +system.membus.trans_dist::ReadResp 662640 # Transaction distribution +system.membus.trans_dist::WriteReq 13889 # Transaction distribution +system.membus.trans_dist::WriteResp 13889 # Transaction distribution +system.membus.trans_dist::Writeback 149983 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2184 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1723 # Transaction distribution -system.membus.trans_dist::ReadExReq 133213 # Transaction distribution -system.membus.trans_dist::ReadExResp 133211 # Transaction distribution -system.membus.trans_dist::MessageReq 1641 # Transaction distribution -system.membus.trans_dist::MessageResp 1641 # Transaction distribution -system.membus.trans_dist::BadAddressError 12 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471406 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775060 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723935 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141460 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141460 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1868677 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550117 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20227873 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2187 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1743 # Transaction distribution +system.membus.trans_dist::ReadExReq 133791 # Transaction distribution +system.membus.trans_dist::ReadExResp 133789 # Transaction distribution +system.membus.trans_dist::MessageReq 1644 # Transaction distribution +system.membus.trans_dist::MessageResp 1644 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1725388 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1870142 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18480320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20272507 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26239557 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1606 # Total snoops (count) -system.membus.snoop_fanout::samples 385212 # Request fanout histogram +system.membus.pkt_size::total 26284203 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1595 # Total snoops (count) +system.membus.snoop_fanout::samples 385911 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 385212 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 385911 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 385212 # Request fanout histogram -system.membus.reqLayer0.occupancy 251510000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 385911 # Request fanout histogram +system.membus.reqLayer0.occupancy 251714500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583228000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583067000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1995467500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1996777999 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3158524545 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3163999272 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54933487 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54979247 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index b728ac0c9..92c4535bc 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.300742 # Number of seconds simulated -sim_ticks 5300741898500 # Number of ticks simulated -final_tick 5300741898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305804 # Number of seconds simulated +sim_ticks 5305803886500 # Number of ticks simulated +final_tick 5305803886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 268181 # Simulator instruction rate (inst/s) -host_op_rate 514172 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13311463323 # Simulator tick rate (ticks/s) -host_mem_usage 800056 # Number of bytes of host memory used -host_seconds 398.21 # Real time elapsed on the host -sim_insts 106792132 # Number of instructions simulated -sim_ops 204747982 # Number of ops (including micro ops) simulated +host_inst_rate 199055 # Simulator instruction rate (inst/s) +host_op_rate 381625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9885187347 # Simulator tick rate (ticks/s) +host_mem_usage 854320 # Number of bytes of host memory used +host_seconds 536.74 # Real time elapsed on the host +sim_insts 106841423 # Number of instructions simulated +sim_ops 204834575 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11447360 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11447360 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9142976 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9142976 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 178865 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 178865 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 142859 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 142859 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2159577 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2159577 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1724848 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1724848 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3884425 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3884425 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 178865 # Number of read requests accepted -system.mem_ctrls.writeReqs 142859 # Number of write requests accepted -system.mem_ctrls.readBursts 178865 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 142859 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11390720 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 56640 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9134848 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11447360 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9142976 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 885 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 106 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11434048 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11434048 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9128256 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9128256 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 178657 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 178657 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 142629 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 142629 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2155008 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2155008 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1720428 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1720428 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3875436 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3875436 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 178657 # Number of read requests accepted +system.mem_ctrls.writeReqs 142629 # Number of write requests accepted +system.mem_ctrls.readBursts 178657 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 142629 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11379712 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 54336 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9119680 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11434048 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9128256 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 849 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 11083 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10466 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10673 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10751 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11479 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 11934 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 10746 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10510 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 10984 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 10978 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 10728 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 13966 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 10998 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10695 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11146 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10843 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 9192 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 8887 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8721 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8884 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9584 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9646 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 8803 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8544 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8749 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 8837 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 8942 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 8982 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 8616 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 8535 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 8942 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8868 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 10773 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10609 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10875 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11019 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11847 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 12404 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11308 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10254 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10790 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 10382 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10431 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 13895 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 11043 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10450 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 11056 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10672 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8646 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8740 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8909 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9072 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9699 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9645 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8889 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8365 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 8684 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8653 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8512 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9107 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 8716 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8645 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9206 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 9007 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5300741764000 # Total gap between requests +system.mem_ctrls.totGap 5305803752000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 178865 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 178657 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 142859 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 177944 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 36 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 142629 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 177742 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 66 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,38 +135,38 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2042 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2762 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8528 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9126 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8582 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9159 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9214 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8343 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9016 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9104 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8438 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8502 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8352 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8474 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8065 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8107 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8180 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 7958 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 136 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 116 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 100 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 96 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 84 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 72 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 32 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 21 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 11 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2048 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2805 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8516 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9095 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8606 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9164 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9192 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8373 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9017 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9032 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8415 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8498 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8325 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8422 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8038 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8077 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8151 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 7943 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 129 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 121 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 110 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 90 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 88 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 13 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -184,74 +184,73 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60353 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 340.090865 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 200.552614 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 345.449556 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20341 33.70% 33.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14451 23.94% 57.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6322 10.48% 68.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3381 5.60% 73.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2729 4.52% 78.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1822 3.02% 81.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1379 2.28% 83.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1383 2.29% 85.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8545 14.16% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60353 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7902 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.522399 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 318.068462 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7896 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60600 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.272739 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 199.847297 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.861949 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20364 33.60% 33.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14670 24.21% 57.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6315 10.42% 68.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3448 5.69% 73.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2734 4.51% 78.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1855 3.06% 81.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1401 2.31% 83.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1433 2.36% 86.17% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8380 13.83% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60600 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7887 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.539115 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 318.374099 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7881 99.92% 99.92% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 2 0.03% 99.95% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 2 0.03% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7902 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7902 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.062769 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.701265 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 4.160598 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5817 73.61% 73.61% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.73% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 164 2.08% 75.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 13 0.16% 75.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 44 0.56% 76.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 510 6.45% 82.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 151 1.91% 84.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 32 0.40% 85.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 635 8.04% 93.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 115 1.46% 94.79% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 6 0.08% 94.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 14 0.18% 95.04% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 297 3.76% 98.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 8 0.10% 98.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 4 0.05% 98.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 6 0.08% 99.03% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 6 0.08% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 2 0.03% 99.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 4 0.05% 99.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 1 0.01% 99.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.28% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 5 0.06% 99.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 6 0.08% 99.46% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 9 0.11% 99.57% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.65% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 4 0.05% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 5 0.06% 99.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 3 0.04% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 2 0.03% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 5 0.06% 99.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 9 0.11% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7902 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1958460749 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5295585749 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 889900000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11003.82 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 7887 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7887 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.067072 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.711824 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 4.086646 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5792 73.44% 73.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 155 1.97% 75.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 18 0.23% 75.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 48 0.61% 76.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 474 6.01% 82.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 162 2.05% 84.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 48 0.61% 85.09% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 632 8.01% 93.10% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 129 1.64% 94.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 11 0.14% 94.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 12 0.15% 95.03% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 299 3.79% 98.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 7 0.09% 98.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 7 0.09% 99.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 8 0.10% 99.10% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.19% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 6 0.08% 99.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 1 0.01% 99.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 1 0.01% 99.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 11 0.14% 99.62% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 6 0.08% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 1 0.01% 99.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 8 0.10% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 7 0.09% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 7887 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1946379497 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5280279497 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 889040000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10946.52 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29753.82 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 29696.52 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 2.14 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s @@ -260,270 +259,275 @@ system.mem_ctrls.busUtil 0.03 # Da system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 27.88 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 142054 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 118304 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.81 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 82.87 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 16476053.28 # Average gap between requests -system.mem_ctrls.pageHitRate 81.18 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 5045112796500 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 177003320000 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 78625657500 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 223791120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 232477560 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 122108250 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 126847875 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 683599800 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 704636400 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 468251280 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 456652080 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 346218493920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 346218493920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 148888594485 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 149563929060 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 3049839426000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 3049247027250 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 3546444264855 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 3546550064145 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 669.047128 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 669.067087 # Core power per rank (mW) +system.mem_ctrls.avgWrQLen 25.29 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 141783 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 117919 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.74 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.74 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 16514270.00 # Average gap between requests +system.mem_ctrls.pageHitRate 81.07 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 229566960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 125259750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 694894200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 466333200 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 149180699250 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052619831250 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549865642530 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.053779 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5078135564501 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 50492285499 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 228569040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 124715250 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 692000400 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 457034400 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 149006937600 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3052772253750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549830568360 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.047168 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5078398943499 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 50232498501 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10600620667 # number of cpu cycles simulated +system.cpu0.numCycles 10611607773 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 58326751 # Number of instructions committed -system.cpu0.committedOps 112208544 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 105142610 # Number of integer alu accesses +system.cpu0.committedInsts 58312369 # Number of instructions committed +system.cpu0.committedOps 112077158 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 105052932 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 999393 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9968022 # number of instructions that are conditional controls -system.cpu0.num_int_insts 105142610 # number of integer instructions +system.cpu0.num_func_calls 985826 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9959513 # number of instructions that are conditional controls +system.cpu0.num_int_insts 105052932 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 198014063 # number of times the integer registers were read -system.cpu0.num_int_register_writes 89363011 # number of times the integer registers were written +system.cpu0.num_int_register_reads 198024346 # number of times the integer registers were read +system.cpu0.num_int_register_writes 89262745 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 60260543 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43624365 # number of times the CC registers were written -system.cpu0.num_mem_refs 12030075 # number of memory refs -system.cpu0.num_load_insts 7288332 # Number of load instructions -system.cpu0.num_store_insts 4741743 # Number of store instructions -system.cpu0.num_idle_cycles 10084773874.270475 # Number of idle cycles -system.cpu0.num_busy_cycles 515846792.729524 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048662 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951338 # Percentage of idle cycles -system.cpu0.Branches 11302630 # Number of branches fetched -system.cpu0.op_class::No_OpClass 132692 0.12% 0.12% # Class of executed instruction -system.cpu0.op_class::IntAlu 99906926 89.04% 89.15% # Class of executed instruction -system.cpu0.op_class::IntMult 87661 0.08% 89.23% # Class of executed instruction -system.cpu0.op_class::IntDiv 51849 0.05% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::MemRead 7288332 6.50% 95.77% # Class of executed instruction -system.cpu0.op_class::MemWrite 4741743 4.23% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 60301130 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43624803 # number of times the CC registers were written +system.cpu0.num_mem_refs 12143482 # number of memory refs +system.cpu0.num_load_insts 7354533 # Number of load instructions +system.cpu0.num_store_insts 4788949 # Number of store instructions +system.cpu0.num_idle_cycles 10094720432.678099 # Number of idle cycles +system.cpu0.num_busy_cycles 516887340.321903 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048710 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951290 # Percentage of idle cycles +system.cpu0.Branches 11277737 # Number of branches fetched +system.cpu0.op_class::No_OpClass 133660 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 99659673 88.92% 89.04% # Class of executed instruction +system.cpu0.op_class::IntMult 84103 0.08% 89.11% # Class of executed instruction +system.cpu0.op_class::IntDiv 57076 0.05% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::MemRead 7354533 6.56% 95.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 4788949 4.27% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 112209203 # Class of executed instruction +system.cpu0.op_class::total 112077994 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10601483797 # number of cpu cycles simulated +system.cpu1.numCycles 10608678164 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48465381 # Number of instructions committed -system.cpu1.committedOps 92539438 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88910462 # Number of integer alu accesses +system.cpu1.committedInsts 48529054 # Number of instructions committed +system.cpu1.committedOps 92757417 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 89083939 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1744945 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8275238 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88910462 # number of integer instructions +system.cpu1.num_func_calls 1759211 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8292881 # number of instructions that are conditional controls +system.cpu1.num_int_insts 89083939 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 172623141 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73500216 # number of times the integer registers were written +system.cpu1.num_int_register_reads 172769101 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73668949 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 51257305 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 33029139 # number of times the CC registers were written -system.cpu1.num_mem_refs 14403882 # number of memory refs -system.cpu1.num_load_insts 9271822 # Number of load instructions -system.cpu1.num_store_insts 5132060 # Number of store instructions -system.cpu1.num_idle_cycles 10262330670.974064 # Number of idle cycles -system.cpu1.num_busy_cycles 339153126.025936 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031991 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968009 # Percentage of idle cycles -system.cpu1.Branches 10623766 # Number of branches fetched -system.cpu1.op_class::No_OpClass 173936 0.19% 0.19% # Class of executed instruction -system.cpu1.op_class::IntAlu 77788975 84.06% 84.25% # Class of executed instruction -system.cpu1.op_class::IntMult 96916 0.10% 84.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 76680 0.08% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::MemRead 9271822 10.02% 94.45% # Class of executed instruction -system.cpu1.op_class::MemWrite 5132060 5.55% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 51289512 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 33065409 # number of times the CC registers were written +system.cpu1.num_mem_refs 14308473 # number of memory refs +system.cpu1.num_load_insts 9217545 # Number of load instructions +system.cpu1.num_store_insts 5090928 # Number of store instructions +system.cpu1.num_idle_cycles 10270312186.995054 # Number of idle cycles +system.cpu1.num_busy_cycles 338365977.004946 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031895 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968105 # Percentage of idle cycles +system.cpu1.Branches 10658677 # Number of branches fetched +system.cpu1.op_class::No_OpClass 173276 0.19% 0.19% # Class of executed instruction +system.cpu1.op_class::IntAlu 78104057 84.20% 84.39% # Class of executed instruction +system.cpu1.op_class::IntMult 100669 0.11% 84.50% # Class of executed instruction +system.cpu1.op_class::IntDiv 71662 0.08% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::MemRead 9217545 9.94% 94.51% # Class of executed instruction +system.cpu1.op_class::MemWrite 5090928 5.49% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92540389 # Class of executed instruction +system.cpu1.op_class::total 92758137 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 857926 # Transaction distribution -system.iobus.trans_dist::ReadResp 857926 # Transaction distribution -system.iobus.trans_dist::WriteReq 36569 # Transaction distribution -system.iobus.trans_dist::WriteResp 36569 # Transaction distribution -system.iobus.trans_dist::MessageReq 1919 # Transaction distribution -system.iobus.trans_dist::MessageResp 1919 # Transaction distribution +system.iobus.trans_dist::ReadReq 857916 # Transaction distribution +system.iobus.trans_dist::ReadResp 857916 # Transaction distribution +system.iobus.trans_dist::WriteReq 36558 # Transaction distribution +system.iobus.trans_dist::WriteResp 36558 # Transaction distribution +system.iobus.trans_dist::MessageReq 1920 # Transaction distribution +system.iobus.trans_dist::MessageResp 1920 # Transaction distribution system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4780 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5802 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 1048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 964 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 966 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 16892 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 296 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 238 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1704360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703174 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5240 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 316 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 400 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 348 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 10236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12178 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 200 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1792828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 86270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1792788 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3284 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6684 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3294 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 524 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 482 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1980 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1932 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 8446 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486546 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7471 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 476 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972617 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971862 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3964 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3366 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 158 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15582 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 728 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 696 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15626 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 5118 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6089 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10293 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51987 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2031288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 51000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10473 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52670 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2031220 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10161500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10107000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 145000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1080000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1059500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 94000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 55000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 20808000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 28599000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1385500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1327000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 31365000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 39157000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 23203000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 23099500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -531,19 +535,19 @@ system.iobus.reqLayer15.occupancy 9000 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 469007612 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 469010624 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8240496 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 8240920 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 1330000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2404108 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2415044 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2025089500 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 2023919000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 59993000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 76513000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -560,48 +564,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10900696 # delay histogram for all message -system.ruby.delayHist::mean 0.442840 # delay histogram for all message -system.ruby.delayHist::stdev 1.830682 # delay histogram for all message -system.ruby.delayHist | 10297724 94.47% 94.47% | 1479 0.01% 94.48% | 601064 5.51% 100.00% | 150 0.00% 100.00% | 222 0.00% 100.00% | 14 0.00% 100.00% | 41 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10900696 # delay histogram for all message +system.ruby.delayHist::samples 10911216 # delay histogram for all message +system.ruby.delayHist::mean 0.442136 # delay histogram for all message +system.ruby.delayHist::stdev 1.829254 # delay histogram for all message +system.ruby.delayHist | 10308626 94.48% 94.48% | 1272 0.01% 94.49% | 600907 5.51% 100.00% | 150 0.00% 100.00% | 203 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10911216 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152128630 +system.ruby.outstanding_req_hist::samples 152209035 system.ruby.outstanding_req_hist::mean 1.000112 system.ruby.outstanding_req_hist::gmean 1.000078 -system.ruby.outstanding_req_hist::stdev 0.010605 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152111520 99.99% 99.99% | 17110 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152128630 +system.ruby.outstanding_req_hist::stdev 0.010600 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152191931 99.99% 99.99% | 17104 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152209035 system.ruby.latency_hist::bucket_size 256 system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 152128629 -system.ruby.latency_hist::mean 3.436815 -system.ruby.latency_hist::gmean 3.107877 -system.ruby.latency_hist::stdev 5.781267 -system.ruby.latency_hist | 152119575 99.99% 99.99% | 6193 0.00% 100.00% | 2797 0.00% 100.00% | 28 0.00% 100.00% | 34 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152128629 +system.ruby.latency_hist::samples 152209034 +system.ruby.latency_hist::mean 3.436503 +system.ruby.latency_hist::gmean 3.107893 +system.ruby.latency_hist::stdev 5.762527 +system.ruby.latency_hist | 152200028 99.99% 99.99% | 6260 0.00% 100.00% | 2677 0.00% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 152209034 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 149464039 +system.ruby.hit_latency_hist::samples 149542283 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149464039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 149464039 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149542283 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 149542283 system.ruby.miss_latency_hist::bucket_size 256 system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 2664590 -system.ruby.miss_latency_hist::mean 27.938944 -system.ruby.miss_latency_hist::gmean 22.546119 -system.ruby.miss_latency_hist::stdev 36.016044 -system.ruby.miss_latency_hist | 2655536 99.66% 99.66% | 6193 0.23% 99.89% | 2797 0.10% 100.00% | 28 0.00% 100.00% | 34 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2664590 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 10684802 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 518536 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11203338 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 67461431 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 317291 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 67778722 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2666751 +system.ruby.miss_latency_hist::mean 27.914090 +system.ruby.miss_latency_hist::gmean 22.539704 +system.ruby.miss_latency_hist::stdev 35.853723 +system.ruby.miss_latency_hist | 2657745 99.66% 99.66% | 6260 0.23% 99.90% | 2677 0.10% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 2666751 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 10785659 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 531574 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11317233 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 67530179 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 328872 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 67859051 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -611,13 +615,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 13058053 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1328322 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14386375 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 58259753 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 500441 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58760194 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 15 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12972395 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1316773 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14289168 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 58254050 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 489532 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58743582 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -627,601 +631,613 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2436707 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227883 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2664590 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 10 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2439158 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 227593 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2666751 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.029331 -system.ruby.network.routers0.msg_count.Control::0 835827 -system.ruby.network.routers0.msg_count.Request_Control::2 42905 -system.ruby.network.routers0.msg_count.Response_Data::1 863889 -system.ruby.network.routers0.msg_count.Response_Control::1 496114 -system.ruby.network.routers0.msg_count.Response_Control::2 492544 -system.ruby.network.routers0.msg_count.Writeback_Data::0 292440 -system.ruby.network.routers0.msg_count.Writeback_Data::1 167 -system.ruby.network.routers0.msg_count.Writeback_Control::0 162044 -system.ruby.network.routers0.msg_bytes.Control::0 6686616 -system.ruby.network.routers0.msg_bytes.Request_Control::2 343240 -system.ruby.network.routers0.msg_bytes.Response_Data::1 62200008 -system.ruby.network.routers0.msg_bytes.Response_Control::1 3968912 -system.ruby.network.routers0.msg_bytes.Response_Control::2 3940352 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21055680 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12024 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1296352 -system.ruby.network.routers1.percent_links_utilized 0.057975 -system.ruby.network.routers1.msg_count.Control::0 1828763 -system.ruby.network.routers1.msg_count.Request_Control::2 40586 -system.ruby.network.routers1.msg_count.Response_Data::1 1853208 -system.ruby.network.routers1.msg_count.Response_Control::1 1269894 -system.ruby.network.routers1.msg_count.Response_Control::2 1269686 -system.ruby.network.routers1.msg_count.Writeback_Data::0 282914 -system.ruby.network.routers1.msg_count.Writeback_Data::1 208 -system.ruby.network.routers1.msg_count.Writeback_Control::0 948886 -system.ruby.network.routers1.msg_bytes.Control::0 14630104 -system.ruby.network.routers1.msg_bytes.Request_Control::2 324688 -system.ruby.network.routers1.msg_bytes.Response_Data::1 133430976 -system.ruby.network.routers1.msg_bytes.Response_Control::1 10159152 -system.ruby.network.routers1.msg_bytes.Response_Control::2 10157488 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20369808 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 14976 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7591088 -system.ruby.network.routers2.percent_links_utilized 0.091680 -system.ruby.network.routers2.msg_count.Control::0 2843003 -system.ruby.network.routers2.msg_count.Request_Control::2 81677 -system.ruby.network.routers2.msg_count.Response_Data::1 2894271 -system.ruby.network.routers2.msg_count.Response_Control::1 1849723 -system.ruby.network.routers2.msg_count.Response_Control::2 1762230 -system.ruby.network.routers2.msg_count.Writeback_Data::0 575354 -system.ruby.network.routers2.msg_count.Writeback_Data::1 375 -system.ruby.network.routers2.msg_count.Writeback_Control::0 1110930 -system.ruby.network.routers2.msg_bytes.Control::0 22744024 -system.ruby.network.routers2.msg_bytes.Request_Control::2 653416 -system.ruby.network.routers2.msg_bytes.Response_Data::1 208387512 -system.ruby.network.routers2.msg_bytes.Response_Control::1 14797784 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14097840 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41425488 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 27000 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8887440 -system.ruby.network.routers3.percent_links_utilized 0.006831 -system.ruby.network.routers3.msg_count.Control::0 178413 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-system.ruby.network.routers6.msg_count.Writeback_Control::0 1158480 +system.ruby.network.routers6.percent_links_utilized 0.031000 +system.ruby.network.routers6.msg_count.Control::0 2844938 +system.ruby.network.routers6.msg_count.Request_Control::2 83201 +system.ruby.network.routers6.msg_count.Response_Data::1 2946593 +system.ruby.network.routers6.msg_count.Response_Control::1 1875593 +system.ruby.network.routers6.msg_count.Response_Control::2 1764444 +system.ruby.network.routers6.msg_count.Writeback_Data::0 575124 +system.ruby.network.routers6.msg_count.Writeback_Data::1 402 +system.ruby.network.routers6.msg_count.Writeback_Control::0 1160957 system.ruby.network.routers6.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.msg_bytes.Control::0 22744024 -system.ruby.network.routers6.msg_bytes.Request_Control::2 667928 -system.ruby.network.routers6.msg_bytes.Response_Data::1 212007960 -system.ruby.network.routers6.msg_bytes.Response_Control::1 14989064 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+system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8907248 +system.ruby.network.routers6.throttle3.link_utilization 0.005283 +system.ruby.network.routers6.throttle3.msg_count.Control::0 178187 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97745 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15738 +system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47551 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1425496 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7037640 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 125904 +system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380408 system.ruby.network.routers6.throttle4.link_utilization 0.000255 -system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 814 +system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 815 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58680 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6113104 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754972 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.341149 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5536836 90.57% 90.57% | 424 0.01% 90.58% | 575424 9.41% 99.99% | 146 0.00% 100.00% | 217 0.00% 100.00% | 14 0.00% 100.00% | 41 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6113104 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6119725 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.753707 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.339234 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5543761 90.59% 90.59% | 388 0.01% 90.59% | 575170 9.40% 99.99% | 147 0.00% 100.00% | 201 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6119725 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4704101 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.045072 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.595912 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4676918 99.42% 99.42% | 479 0.01% 99.43% | 405 0.01% 99.44% | 650 0.01% 99.45% | 25495 0.54% 100.00% | 145 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4704101 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4708290 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.044976 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.595659 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4681222 99.43% 99.43% | 442 0.01% 99.43% | 339 0.01% 99.44% | 545 0.01% 99.45% | 25596 0.54% 100.00% | 141 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4708290 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 83491 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000264 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.022955 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 83480 99.99% 99.99% | 0 0.00% 99.99% | 11 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 83491 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 256 -system.ruby.LD.latency_hist::max_bucket 2559 -system.ruby.LD.latency_hist::samples 14918164 -system.ruby.LD.latency_hist::mean 4.885826 -system.ruby.LD.latency_hist::gmean 3.596048 -system.ruby.LD.latency_hist::stdev 9.349489 -system.ruby.LD.latency_hist | 14916026 99.99% 99.99% | 1637 0.01% 100.00% | 485 0.00% 100.00% | 10 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 14918164 +system.ruby.delayVCHist.vnet_2::samples 83201 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000120 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.015504 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 83196 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 83201 # delay histogram for vnet_2 +system.ruby.LD.latency_hist::bucket_size 128 +system.ruby.LD.latency_hist::max_bucket 1279 +system.ruby.LD.latency_hist::samples 14928118 +system.ruby.LD.latency_hist::mean 4.887199 +system.ruby.LD.latency_hist::gmean 3.596426 +system.ruby.LD.latency_hist::stdev 9.328249 +system.ruby.LD.latency_hist | 14912021 99.89% 99.89% | 13966 0.09% 99.99% | 828 0.01% 99.99% | 820 0.01% 100.00% | 357 0.00% 100.00% | 111 0.00% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 14928118 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13527451 +system.ruby.LD.hit_latency_hist::samples 13535758 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13527451 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13527451 -system.ruby.LD.miss_latency_hist::bucket_size 256 -system.ruby.LD.miss_latency_hist::max_bucket 2559 -system.ruby.LD.miss_latency_hist::samples 1390713 -system.ruby.LD.miss_latency_hist::mean 23.229241 -system.ruby.LD.miss_latency_hist::gmean 20.959487 -system.ruby.LD.miss_latency_hist::stdev 23.803463 -system.ruby.LD.miss_latency_hist | 1388575 99.85% 99.85% | 1637 0.12% 99.96% | 485 0.03% 100.00% | 10 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1390713 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535758 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13535758 +system.ruby.LD.miss_latency_hist::bucket_size 128 +system.ruby.LD.miss_latency_hist::max_bucket 1279 +system.ruby.LD.miss_latency_hist::samples 1392360 +system.ruby.LD.miss_latency_hist::mean 23.233506 +system.ruby.LD.miss_latency_hist::gmean 20.962083 +system.ruby.LD.miss_latency_hist::stdev 23.700852 +system.ruby.LD.miss_latency_hist | 1376263 98.84% 98.84% | 13966 1.00% 99.85% | 828 0.06% 99.91% | 820 0.06% 99.97% | 357 0.03% 99.99% | 111 0.01% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1392360 system.ruby.ST.latency_hist::bucket_size 256 system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 9498200 -system.ruby.ST.latency_hist::mean 5.193739 -system.ruby.ST.latency_hist::gmean 3.303046 -system.ruby.ST.latency_hist::stdev 17.710522 -system.ruby.ST.latency_hist | 9492386 99.94% 99.94% | 3703 0.04% 99.98% | 2069 0.02% 100.00% | 12 0.00% 100.00% | 29 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9498200 +system.ruby.ST.latency_hist::samples 9504180 +system.ruby.ST.latency_hist::mean 5.187204 +system.ruby.ST.latency_hist::gmean 3.302390 +system.ruby.ST.latency_hist::stdev 17.665644 +system.ruby.ST.latency_hist | 9498362 99.94% 99.94% | 3775 0.04% 99.98% | 1993 0.02% 100.00% | 29 0.00% 100.00% | 20 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 9504180 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9146403 +system.ruby.ST.hit_latency_hist::samples 9152723 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9146403 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9146403 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9152723 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9152723 system.ruby.ST.miss_latency_hist::bucket_size 256 system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 351797 -system.ruby.ST.miss_latency_hist::mean 62.228953 -system.ruby.ST.miss_latency_hist::gmean 40.318436 -system.ruby.ST.miss_latency_hist::stdev 71.347621 -system.ruby.ST.miss_latency_hist | 345983 98.35% 98.35% | 3703 1.05% 99.40% | 2069 0.59% 99.99% | 12 0.00% 99.99% | 29 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 351797 +system.ruby.ST.miss_latency_hist::samples 351457 +system.ruby.ST.miss_latency_hist::mean 62.146880 +system.ruby.ST.miss_latency_hist::gmean 40.269218 +system.ruby.ST.miss_latency_hist::stdev 71.205537 +system.ruby.ST.miss_latency_hist | 345639 98.34% 98.34% | 3775 1.07% 99.42% | 1993 0.57% 99.99% | 29 0.01% 99.99% | 20 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 351457 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 126538916 -system.ruby.IFETCH.latency_hist::mean 3.120095 -system.ruby.IFETCH.latency_hist::gmean 3.036786 -system.ruby.IFETCH.latency_hist::stdev 2.265582 -system.ruby.IFETCH.latency_hist | 126532168 99.99% 99.99% | 5703 0.00% 100.00% | 492 0.00% 100.00% | 323 0.00% 100.00% | 160 0.00% 100.00% | 64 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126538916 +system.ruby.IFETCH.latency_hist::samples 126602633 +system.ruby.IFETCH.latency_hist::mean 3.119985 +system.ruby.IFETCH.latency_hist::gmean 3.036795 +system.ruby.IFETCH.latency_hist::stdev 2.244898 +system.ruby.IFETCH.latency_hist | 126595894 99.99% 99.99% | 5742 0.00% 100.00% | 458 0.00% 100.00% | 336 0.00% 100.00% | 141 0.00% 100.00% | 58 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126602633 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 125721184 +system.ruby.IFETCH.hit_latency_hist::samples 125784229 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125721184 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 125721184 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125784229 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 125784229 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 817732 -system.ruby.IFETCH.miss_latency_hist::mean 21.583892 -system.ruby.IFETCH.miss_latency_hist::gmean 19.777346 -system.ruby.IFETCH.miss_latency_hist::stdev 21.240290 -system.ruby.IFETCH.miss_latency_hist | 810984 99.17% 99.17% | 5703 0.70% 99.87% | 492 0.06% 99.93% | 323 0.04% 99.97% | 160 0.02% 99.99% | 64 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 817732 +system.ruby.IFETCH.miss_latency_hist::samples 818404 +system.ruby.IFETCH.miss_latency_hist::mean 21.561079 +system.ruby.IFETCH.miss_latency_hist::gmean 19.774643 +system.ruby.IFETCH.miss_latency_hist::stdev 20.911893 +system.ruby.IFETCH.miss_latency_hist | 811665 99.18% 99.18% | 5742 0.70% 99.88% | 458 0.06% 99.93% | 336 0.04% 99.98% | 141 0.02% 99.99% | 58 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 818404 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 494265 -system.ruby.RMW_Read.latency_hist::mean 6.023605 -system.ruby.RMW_Read.latency_hist::gmean 3.954302 -system.ruby.RMW_Read.latency_hist::stdev 10.239189 -system.ruby.RMW_Read.latency_hist | 494082 99.96% 99.96% | 137 0.03% 99.99% | 14 0.00% 99.99% | 17 0.00% 100.00% | 10 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 494265 +system.ruby.RMW_Read.latency_hist::samples 494795 +system.ruby.RMW_Read.latency_hist::mean 6.019475 +system.ruby.RMW_Read.latency_hist::gmean 3.954538 +system.ruby.RMW_Read.latency_hist::stdev 10.125129 +system.ruby.RMW_Read.latency_hist | 494623 99.97% 99.97% | 131 0.03% 99.99% | 11 0.00% 99.99% | 18 0.00% 100.00% | 7 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494795 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 428815 +system.ruby.RMW_Read.hit_latency_hist::samples 429248 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428815 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 428815 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 429248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 429248 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 65450 -system.ruby.RMW_Read.miss_latency_hist::mean 25.833644 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.151736 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.422970 -system.ruby.RMW_Read.miss_latency_hist | 65267 99.72% 99.72% | 137 0.21% 99.93% | 14 0.02% 99.95% | 17 0.03% 99.98% | 10 0.02% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65450 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.latency_hist::samples 339542 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.330551 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.775845 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.064390 -system.ruby.Locked_RMW_Read.latency_hist | 339293 99.93% 99.93% | 238 0.07% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339542 +system.ruby.RMW_Read.miss_latency_hist::samples 65547 +system.ruby.RMW_Read.miss_latency_hist::mean 25.793126 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.141988 +system.ruby.RMW_Read.miss_latency_hist::stdev 17.977211 +system.ruby.RMW_Read.miss_latency_hist | 65375 99.74% 99.74% | 131 0.20% 99.94% | 11 0.02% 99.95% | 18 0.03% 99.98% | 7 0.01% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65547 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.latency_hist::samples 339654 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.341447 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.777860 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.189753 +system.ruby.Locked_RMW_Read.latency_hist | 339308 99.90% 99.90% | 89 0.03% 99.92% | 236 0.07% 99.99% | 2 0.00% 99.99% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339654 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300644 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300671 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300644 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 300644 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38898 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.343462 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.340350 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.186116 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38649 99.36% 99.36% | 238 0.61% 99.97% | 4 0.01% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 38898 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300671 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 300671 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38983 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.400739 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.361163 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.695962 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38637 99.11% 99.11% | 89 0.23% 99.34% | 236 0.61% 99.95% | 2 0.01% 99.95% | 6 0.02% 99.97% | 3 0.01% 99.97% | 2 0.01% 99.98% | 3 0.01% 99.99% | 2 0.01% 99.99% | 3 0.01% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 38983 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339542 +system.ruby.Locked_RMW_Write.latency_hist::samples 339654 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339542 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339542 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339542 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339542 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339542 -system.ruby.Directory_Controller.Fetch 178413 0.00% 0.00% -system.ruby.Directory_Controller.Data 97701 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178865 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 142859 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339654 +system.ruby.Directory_Controller.Fetch 178187 0.00% 0.00% +system.ruby.Directory_Controller.Data 97745 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 178657 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142629 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 815 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15947 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 178413 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 452 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45158 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 452 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45158 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 95761 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1578 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15947 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 178413 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 95761 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1578 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1578 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 814 +system.ruby.Directory_Controller.CleanReplacement 15738 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 178187 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 470 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 44884 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 470 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 44884 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95548 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1852 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15738 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 178187 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95548 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1852 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1852 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 815 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 814 +system.ruby.DMA_Controller.Data | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 815 system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 814 +system.ruby.DMA_Controller.READY.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 815 system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 814 +system.ruby.DMA_Controller.BUSY_RD.Data | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 815 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6037097 40.47% 40.47% | 8881067 59.53% 100.00% -system.ruby.L1Cache_Controller.Load::total 14918164 -system.ruby.L1Cache_Controller.Ifetch | 67778726 53.56% 53.56% | 58760197 46.44% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126538923 -system.ruby.L1Cache_Controller.Store | 5166241 48.41% 48.41% | 5505308 51.59% 100.00% -system.ruby.L1Cache_Controller.Store::total 10671549 -system.ruby.L1Cache_Controller.Inv | 16573 48.71% 48.71% | 17448 51.29% 100.00% -system.ruby.L1Cache_Controller.Inv::total 34021 -system.ruby.L1Cache_Controller.L1_Replacement | 807951 30.97% 30.97% | 1801234 69.03% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2609185 -system.ruby.L1Cache_Controller.Fwd_GETX | 12319 50.77% 50.77% | 11946 49.23% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 24265 -system.ruby.L1Cache_Controller.Fwd_GETS | 14009 55.59% 55.59% | 11192 44.41% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25201 +system.ruby.L1Cache_Controller.Load | 6103954 40.89% 40.89% | 8824164 59.11% 100.00% +system.ruby.L1Cache_Controller.Load::total 14928118 +system.ruby.L1Cache_Controller.Ifetch | 67859054 53.60% 53.60% | 58743585 46.40% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126602639 +system.ruby.L1Cache_Controller.Store | 5213279 48.82% 48.82% | 5465004 51.18% 100.00% +system.ruby.L1Cache_Controller.Store::total 10678283 +system.ruby.L1Cache_Controller.Inv | 16394 48.51% 48.51% | 17401 51.49% 100.00% +system.ruby.L1Cache_Controller.Inv::total 33795 +system.ruby.L1Cache_Controller.L1_Replacement | 832783 31.89% 31.89% | 1778531 68.11% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2611314 +system.ruby.L1Cache_Controller.Fwd_GETX | 12220 50.79% 50.79% | 11839 49.21% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 24059 +system.ruby.L1Cache_Controller.Fwd_GETS | 14364 56.68% 56.68% | 10979 43.32% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 25343 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 658 37.77% 37.77% | 1084 62.23% 100.00% -system.ruby.L1Cache_Controller.Data::total 1742 -system.ruby.L1Cache_Controller.Data_Exclusive | 243874 19.04% 19.04% | 1037006 80.96% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1280880 -system.ruby.L1Cache_Controller.DataS_fromL1 | 11192 44.40% 44.40% | 14013 55.60% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25205 -system.ruby.L1Cache_Controller.Data_all_Acks | 567820 42.55% 42.55% | 766775 57.45% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1334595 -system.ruby.L1Cache_Controller.Ack | 12283 55.41% 55.41% | 9885 44.59% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22168 -system.ruby.L1Cache_Controller.Ack_all | 12941 54.12% 54.12% | 10969 45.88% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 23910 -system.ruby.L1Cache_Controller.WB_Ack | 454484 26.95% 26.95% | 1231800 73.05% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1686284 -system.ruby.L1Cache_Controller.NP.Load | 272421 19.86% 19.86% | 1099369 80.14% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1371790 -system.ruby.L1Cache_Controller.NP.Ifetch | 317175 38.82% 38.82% | 499890 61.18% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 817065 -system.ruby.L1Cache_Controller.NP.Store | 219379 51.94% 51.94% | 202999 48.06% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 422378 -system.ruby.L1Cache_Controller.NP.Inv | 5530 57.31% 57.31% | 4119 42.69% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 9649 -system.ruby.L1Cache_Controller.I.Load | 8637 45.64% 45.64% | 10286 54.36% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18923 -system.ruby.L1Cache_Controller.I.Ifetch | 116 17.39% 17.39% | 551 82.61% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 667 -system.ruby.L1Cache_Controller.I.Store | 5816 50.14% 50.14% | 5783 49.86% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11599 -system.ruby.L1Cache_Controller.I.L1_Replacement | 8686 50.09% 50.09% | 8655 49.91% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17341 -system.ruby.L1Cache_Controller.S.Load | 551952 52.35% 52.35% | 502332 47.65% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1054284 -system.ruby.L1Cache_Controller.S.Ifetch | 67461431 53.66% 53.66% | 58259753 46.34% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 125721184 -system.ruby.L1Cache_Controller.S.Store | 12283 55.41% 55.41% | 9885 44.59% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22168 -system.ruby.L1Cache_Controller.S.Inv | 10821 45.28% 45.28% | 13078 54.72% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23899 -system.ruby.L1Cache_Controller.S.L1_Replacement | 344781 38.07% 38.07% | 560779 61.93% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 905560 -system.ruby.L1Cache_Controller.E.Load | 1077334 27.76% 27.76% | 2803511 72.24% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3880845 -system.ruby.L1Cache_Controller.E.Store | 80360 48.21% 48.21% | 86332 51.79% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166692 -system.ruby.L1Cache_Controller.E.Inv | 55 56.12% 56.12% | 43 43.88% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 98 -system.ruby.L1Cache_Controller.E.L1_Replacement | 162044 14.59% 14.59% | 948886 85.41% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110930 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 433 65.81% 65.81% | 225 34.19% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 658 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 907 40.65% 40.65% | 1324 59.35% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2231 -system.ruby.L1Cache_Controller.M.Load | 4126753 48.03% 48.03% | 4465569 51.97% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8592322 -system.ruby.L1Cache_Controller.M.Store | 4848403 48.25% 48.25% | 5200309 51.75% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10048712 -system.ruby.L1Cache_Controller.M.Inv | 167 44.53% 44.53% | 208 55.47% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 375 -system.ruby.L1Cache_Controller.M.L1_Replacement | 292440 50.83% 50.83% | 282914 49.17% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 575354 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11886 50.35% 50.35% | 11721 49.65% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23607 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13102 57.04% 57.04% | 9868 42.96% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 22970 +system.ruby.L1Cache_Controller.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% +system.ruby.L1Cache_Controller.Data::total 1824 +system.ruby.L1Cache_Controller.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1283110 +system.ruby.L1Cache_Controller.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 25347 +system.ruby.L1Cache_Controller.Data_all_Acks | 582883 43.69% 43.69% | 751335 56.31% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1334218 +system.ruby.L1Cache_Controller.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% +system.ruby.L1Cache_Controller.Ack::total 22252 +system.ruby.L1Cache_Controller.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 24076 +system.ruby.L1Cache_Controller.WB_Ack | 468087 27.72% 27.72% | 1220443 72.28% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1688530 +system.ruby.L1Cache_Controller.NP.Load | 281209 20.47% 20.47% | 1092251 79.53% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1373460 +system.ruby.L1Cache_Controller.NP.Ifetch | 328766 40.20% 40.20% | 488985 59.80% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 817751 +system.ruby.L1Cache_Controller.NP.Store | 223831 53.02% 53.02% | 198319 46.98% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 422150 +system.ruby.L1Cache_Controller.NP.Inv | 5086 54.54% 54.54% | 4239 45.46% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 9325 +system.ruby.L1Cache_Controller.I.Load | 8631 45.67% 45.67% | 10269 54.33% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 18900 +system.ruby.L1Cache_Controller.I.Ifetch | 106 16.23% 16.23% | 547 83.77% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 653 +system.ruby.L1Cache_Controller.I.Store | 5805 50.11% 50.11% | 5779 49.89% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11584 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8985 51.90% 51.90% | 8328 48.10% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17313 +system.ruby.L1Cache_Controller.S.Load | 530372 50.22% 50.22% | 525759 49.78% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1056131 +system.ruby.L1Cache_Controller.S.Ifetch | 67530179 53.69% 53.69% | 58254050 46.31% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 125784229 +system.ruby.L1Cache_Controller.S.Store | 12098 54.37% 54.37% | 10155 45.63% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22253 +system.ruby.L1Cache_Controller.S.Inv | 11044 46.05% 46.05% | 12940 53.95% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 23984 +system.ruby.L1Cache_Controller.S.L1_Replacement | 355711 39.28% 39.28% | 549760 60.72% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 905471 +system.ruby.L1Cache_Controller.E.Load | 1138534 29.37% 29.37% | 2737774 70.63% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3876308 +system.ruby.L1Cache_Controller.E.Store | 81127 48.65% 48.65% | 85645 51.35% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166772 +system.ruby.L1Cache_Controller.E.Inv | 48 57.83% 57.83% | 35 42.17% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 83 +system.ruby.L1Cache_Controller.E.L1_Replacement | 171015 15.36% 15.36% | 942391 84.64% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1113406 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 278 59.40% 59.40% | 190 40.60% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 468 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 1045 48.60% 48.60% | 1105 51.40% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2150 +system.ruby.L1Cache_Controller.M.Load | 4145208 48.18% 48.18% | 4458111 51.82% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8603319 +system.ruby.L1Cache_Controller.M.Store | 4890418 48.63% 48.63% | 5165106 51.37% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10055524 +system.ruby.L1Cache_Controller.M.Inv | 216 53.73% 53.73% | 186 46.27% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 402 +system.ruby.L1Cache_Controller.M.L1_Replacement | 297072 51.65% 51.65% | 278052 48.35% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 575124 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11941 50.62% 50.62% | 11649 49.38% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23590 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13319 57.43% 57.43% | 9874 42.57% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23193 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 243874 19.04% 19.04% | 1037006 80.96% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280880 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11192 44.40% 44.40% | 14013 55.60% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25205 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 343283 38.04% 38.04% | 559077 61.96% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 902360 -system.ruby.L1Cache_Controller.IM.Data | 658 37.77% 37.77% | 1084 62.23% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1742 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 224537 51.95% 51.95% | 207698 48.05% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 432235 -system.ruby.L1Cache_Controller.SM.Ack | 12283 55.41% 55.41% | 9885 44.59% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22168 -system.ruby.L1Cache_Controller.SM.Ack_all | 12941 54.12% 54.12% | 10969 45.88% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 23910 -system.ruby.L1Cache_Controller.M_I.Ifetch | 4 57.14% 57.14% | 3 42.86% 100.00% -system.ruby.L1Cache_Controller.M_I.Ifetch::total 7 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 454484 26.95% 26.95% | 1231800 73.05% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1686284 -system.ruby.L2Cache_Controller.L1_GET_INSTR 817732 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1390884 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 433978 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22168 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1686284 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 95716 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 15992 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 178413 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 113648 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23349 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2231 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1814 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7922 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25205 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1737025 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 3880 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16558 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 34140 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127715 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 801143 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 84632 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1919 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22168 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 243 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7577 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 4 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 27 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1246740 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 280078 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 95328 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8315 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1708 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1283110 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25347 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 354040 39.24% 39.24% | 548267 60.76% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 902307 +system.ruby.L1Cache_Controller.IM.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1824 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 228843 52.98% 52.98% | 203068 47.02% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431911 +system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.SM.Inv::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 22252 +system.ruby.L1Cache_Controller.SM.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 24076 +system.ruby.L1Cache_Controller.M_I.Ifetch | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 468086 27.72% 27.72% | 1220443 72.28% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1688529 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 1 +system.ruby.L2Cache_Controller.L1_GET_INSTR 818404 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1392538 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 433736 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 22253 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1688530 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95493 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 15793 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 178187 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 113483 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23599 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2150 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1627 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7690 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 25347 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1739097 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 4394 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16549 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 34274 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 127364 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 801825 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 83907 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1933 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22252 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 275 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7330 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 2 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1248836 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 280379 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 95073 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8368 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1950 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25201 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 24265 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1686284 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 25343 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 24059 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1688529 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement 145 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 100 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 228 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 113648 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1708 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 330 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 95 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 245 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 113483 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1950 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 347 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 228 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 45 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 55 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1567 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7577 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 247 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 247 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 34140 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 16558 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127715 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 125 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24087 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 46 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1712938 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22969 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2231 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25200 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 245 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 55 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 40 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1351 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 7330 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 276 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 277 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 2 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 34274 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 16549 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 127364 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 131 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24185 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 47 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1714912 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23196 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2149 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25345 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 1dbb00ab9..039ebcc95 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,148 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133759 # Number of seconds simulated -sim_ticks 5133759356500 # Number of ticks simulated -final_tick 5133759356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136081 # Number of seconds simulated +sim_ticks 5136081138000 # Number of ticks simulated +final_tick 5136081138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 270712 # Simulator instruction rate (inst/s) -host_op_rate 538208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5706161187 # Simulator tick rate (ticks/s) -host_mem_usage 956212 # Number of bytes of host memory used -host_seconds 899.69 # Real time elapsed on the host -sim_insts 243556000 # Number of instructions simulated -sim_ops 484219202 # Number of ops (including micro ops) simulated +host_inst_rate 275445 # Simulator instruction rate (inst/s) +host_op_rate 547622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5813086840 # Simulator tick rate (ticks/s) +host_mem_usage 1006240 # Number of bytes of host memory used +host_seconds 883.54 # Real time elapsed on the host +sim_insts 243366027 # Number of instructions simulated +sim_ops 483844707 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 473664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5506752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1916928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 343744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2959424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 488576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5525632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 145728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1937472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 336128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2922880 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11383040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 473664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 343744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9167488 # Number of bytes written to this memory -system.physmem.bytes_written::total 9167488 # Number of bytes written to this memory +system.physmem.bytes_read::total 11386880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 145728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 336128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 970432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9156352 # Number of bytes written to this memory +system.physmem.bytes_written::total 9156352 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 86043 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2364 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 29952 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 40 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 46241 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 86338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 30273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5252 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 45670 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177860 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143242 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143242 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177920 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143068 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143068 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 92265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1072655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 373397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 66958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 576463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2217291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 92265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 66958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785726 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785726 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 95126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1075846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 377228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 65444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 569088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2217037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 95126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 65444 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1782751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1782751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1782751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 92265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1072655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 373397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 66958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 576463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4003017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 84411 # Number of read requests accepted -system.physmem.writeReqs 105225 # Number of write requests accepted -system.physmem.readBursts 84411 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 105225 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5391616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10688 # Total number of bytes read from write queue -system.physmem.bytesWritten 6646720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5402304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6734400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1370 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 877 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5556 # Per bank write bursts -system.physmem.perBankRdBursts::1 4342 # Per bank write bursts -system.physmem.perBankRdBursts::2 4498 # Per bank write bursts -system.physmem.perBankRdBursts::3 5943 # Per bank write bursts -system.physmem.perBankRdBursts::4 5610 # Per bank write bursts -system.physmem.perBankRdBursts::5 4878 # Per bank write bursts -system.physmem.perBankRdBursts::6 4789 # Per bank write bursts -system.physmem.perBankRdBursts::7 4605 # Per bank write bursts -system.physmem.perBankRdBursts::8 5348 # Per bank write bursts -system.physmem.perBankRdBursts::9 5424 # Per bank write bursts -system.physmem.perBankRdBursts::10 4968 # Per bank write bursts -system.physmem.perBankRdBursts::11 5291 # Per bank write bursts -system.physmem.perBankRdBursts::12 5168 # Per bank write bursts -system.physmem.perBankRdBursts::13 6289 # Per bank write bursts -system.physmem.perBankRdBursts::14 5888 # Per bank write bursts -system.physmem.perBankRdBursts::15 5647 # Per bank write bursts -system.physmem.perBankWrBursts::0 6974 # Per bank write bursts -system.physmem.perBankWrBursts::1 5943 # Per bank write bursts -system.physmem.perBankWrBursts::2 5537 # Per bank write bursts -system.physmem.perBankWrBursts::3 6451 # Per bank write bursts -system.physmem.perBankWrBursts::4 6503 # Per bank write bursts -system.physmem.perBankWrBursts::5 5766 # Per bank write bursts -system.physmem.perBankWrBursts::6 6233 # Per bank write bursts -system.physmem.perBankWrBursts::7 6363 # Per bank write bursts -system.physmem.perBankWrBursts::8 6662 # Per bank write bursts -system.physmem.perBankWrBursts::9 6738 # Per bank write bursts -system.physmem.perBankWrBursts::10 7192 # Per bank write bursts -system.physmem.perBankWrBursts::11 7225 # Per bank write bursts -system.physmem.perBankWrBursts::12 6202 # Per bank write bursts -system.physmem.perBankWrBursts::13 7261 # Per bank write bursts -system.physmem.perBankWrBursts::14 6520 # Per bank write bursts -system.physmem.perBankWrBursts::15 6285 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 95126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1075846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 377228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 65444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 569088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3999787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83943 # Number of read requests accepted +system.physmem.writeReqs 110041 # Number of write requests accepted +system.physmem.readBursts 83943 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 110041 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5367872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue +system.physmem.bytesWritten 6959552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5372352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7042624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1298 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 825 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5657 # Per bank write bursts +system.physmem.perBankRdBursts::1 4325 # Per bank write bursts +system.physmem.perBankRdBursts::2 4452 # Per bank write bursts +system.physmem.perBankRdBursts::3 6002 # Per bank write bursts +system.physmem.perBankRdBursts::4 5499 # Per bank write bursts +system.physmem.perBankRdBursts::5 4854 # Per bank write bursts +system.physmem.perBankRdBursts::6 4847 # Per bank write bursts +system.physmem.perBankRdBursts::7 4597 # Per bank write bursts +system.physmem.perBankRdBursts::8 5338 # Per bank write bursts +system.physmem.perBankRdBursts::9 5444 # Per bank write bursts +system.physmem.perBankRdBursts::10 5075 # Per bank write bursts +system.physmem.perBankRdBursts::11 5197 # Per bank write bursts +system.physmem.perBankRdBursts::12 5244 # Per bank write bursts +system.physmem.perBankRdBursts::13 6205 # Per bank write bursts +system.physmem.perBankRdBursts::14 5705 # Per bank write bursts +system.physmem.perBankRdBursts::15 5432 # Per bank write bursts +system.physmem.perBankWrBursts::0 8070 # Per bank write bursts +system.physmem.perBankWrBursts::1 6584 # Per bank write bursts +system.physmem.perBankWrBursts::2 6149 # Per bank write bursts +system.physmem.perBankWrBursts::3 7200 # Per bank write bursts +system.physmem.perBankWrBursts::4 7057 # Per bank write bursts +system.physmem.perBankWrBursts::5 6223 # Per bank write bursts +system.physmem.perBankWrBursts::6 6693 # Per bank write bursts +system.physmem.perBankWrBursts::7 6492 # Per bank write bursts +system.physmem.perBankWrBursts::8 6300 # Per bank write bursts +system.physmem.perBankWrBursts::9 6374 # Per bank write bursts +system.physmem.perBankWrBursts::10 7150 # Per bank write bursts +system.physmem.perBankWrBursts::11 7064 # Per bank write bursts +system.physmem.perBankWrBursts::12 7000 # Per bank write bursts +system.physmem.perBankWrBursts::13 7706 # Per bank write bursts +system.physmem.perBankWrBursts::14 6569 # Per bank write bursts +system.physmem.perBankWrBursts::15 6112 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5132576110500 # Total gap between requests +system.physmem.totGap 5132269646500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 84411 # Read request sizes (log2) +system.physmem.readPktSize::6 83943 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 105225 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 78589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.writePktSize::6 110041 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 78296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.093112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.896548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.057147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15327 38.97% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9261 23.55% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3835 9.75% 72.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2116 5.38% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1579 4.01% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 961 2.44% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 670 1.70% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 553 1.41% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5027 12.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39329 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4061 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.744644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.795472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4058 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 39516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.960320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.025881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.744102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15369 38.89% 38.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9220 23.33% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3764 9.53% 71.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2091 5.29% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1514 3.83% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 970 2.45% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 639 1.62% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 601 1.52% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5348 13.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39516 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4123 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.342712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 185.525630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4120 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4061 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.573750 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.065998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 25.155630 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 71 1.75% 1.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 7 0.17% 1.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 3181 78.33% 80.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 170 4.19% 84.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 129 3.18% 87.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 1.18% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 114 2.81% 91.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 18 0.44% 92.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 31 0.76% 92.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 38 0.94% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 54 1.33% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 16 0.39% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 98 2.41% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 9 0.22% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 19 0.47% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.12% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.37% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.07% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 11 0.27% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.10% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.07% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4061 # Writes before turning the bus around for reads -system.physmem.totQLat 954764500 # Total ticks spent queuing -system.physmem.totMemAccLat 2534339500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 421220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11333.32 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4123 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.374727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.353037 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 26.922743 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 71 1.72% 1.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 7 0.17% 1.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 3190 77.37% 79.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 194 4.71% 83.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 131 3.18% 87.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 35 0.85% 87.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 132 3.20% 91.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 15 0.36% 91.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 23 0.56% 92.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 42 1.02% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 60 1.46% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 20 0.49% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 93 2.26% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.19% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 26 0.63% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 5 0.12% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 22 0.53% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 8 0.19% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 11 0.27% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 5 0.12% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.07% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.12% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4123 # Writes before turning the bus around for reads +system.physmem.totQLat 931934250 # Total ticks spent queuing +system.physmem.totMemAccLat 2504553000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 419365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11111.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30083.32 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29861.25 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.29 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.74 # Average write queue length when enqueuing -system.physmem.readRowHits 67051 # Number of row buffer hits during reads -system.physmem.writeRowHits 81719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.69 # Row buffer hit rate for writes -system.physmem.avgGap 27065410.10 # Average gap between requests -system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4938610465000 # Time in different power states -system.physmem.memoryStateTime::REF 171427360000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23717365000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 143949960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 153377280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 78544125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 83688000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 313723800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 343379400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 322509600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 350470800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 335311916160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 335311916160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 122830725285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 123321765465 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2972506855500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2972076118500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3431508224430 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3431640715605 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.420699 # Core power per rank (mW) -system.physmem.averagePower::1 668.446507 # Core power per rank (mW) +system.physmem.avgWrQLen 12.18 # Average write queue length when enqueuing +system.physmem.readRowHits 66618 # Number of row buffer hits during reads +system.physmem.writeRowHits 86482 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes +system.physmem.avgGap 26457180.21 # Average gap between requests +system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 145862640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79389750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 313817400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 352952640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94379716215 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2235135422250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2580580030335 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.988936 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3685687946000 # Time in different power states +system.physmem_0.memoryStateTime::REF 127900240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17077044750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 152878320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 83263125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 340392000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 351702000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95036922225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2235169487250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2581307514360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.001289 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3684742447500 # Time in different power states +system.physmem_1.memoryStateTime::REF 127900240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18039817250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 816782821 # number of cpu cycles simulated +system.cpu0.numCycles 818737889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71499658 # Number of instructions committed -system.cpu0.committedOps 145804776 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 133691400 # Number of integer alu accesses +system.cpu0.committedInsts 71815441 # Number of instructions committed +system.cpu0.committedOps 146372002 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134241940 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 937441 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14175274 # number of instructions that are conditional controls -system.cpu0.num_int_insts 133691400 # number of integer instructions +system.cpu0.num_func_calls 946109 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14229680 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134241940 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 245252400 # number of times the integer registers were read -system.cpu0.num_int_register_writes 114908320 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246318200 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115340862 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83238542 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55564556 # number of times the CC registers were written -system.cpu0.num_mem_refs 13632532 # number of memory refs -system.cpu0.num_load_insts 10074437 # Number of load instructions -system.cpu0.num_store_insts 3558095 # Number of store instructions -system.cpu0.num_idle_cycles 775198881.273652 # Number of idle cycles -system.cpu0.num_busy_cycles 41583939.726348 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050912 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949088 # Percentage of idle cycles -system.cpu0.Branches 15460140 # Number of branches fetched -system.cpu0.op_class::No_OpClass 93742 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 131973601 90.51% 90.58% # Class of executed instruction -system.cpu0.op_class::IntMult 57512 0.04% 90.62% # Class of executed instruction -system.cpu0.op_class::IntDiv 47972 0.03% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::MemRead 10074437 6.91% 97.56% # Class of executed instruction -system.cpu0.op_class::MemWrite 3558095 2.44% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83590760 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55777582 # number of times the CC registers were written +system.cpu0.num_mem_refs 13734986 # number of memory refs +system.cpu0.num_load_insts 10122778 # Number of load instructions +system.cpu0.num_store_insts 3612208 # Number of store instructions +system.cpu0.num_idle_cycles 777021055.677311 # Number of idle cycles +system.cpu0.num_busy_cycles 41716833.322689 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050953 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949047 # Percentage of idle cycles +system.cpu0.Branches 15525387 # Number of branches fetched +system.cpu0.op_class::No_OpClass 95218 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 132436366 90.48% 90.54% # Class of executed instruction +system.cpu0.op_class::IntMult 58371 0.04% 90.58% # Class of executed instruction +system.cpu0.op_class::IntDiv 47638 0.03% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::MemRead 10122778 6.92% 97.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 3612208 2.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 145805359 # Class of executed instruction +system.cpu0.op_class::total 146372579 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1638252 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999461 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19656533 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1638764 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.994731 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1637223 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19645241 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1637735 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.995372 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 126.389920 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 280.383418 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 105.226123 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.246855 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.547624 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.205520 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 126.457209 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 281.700690 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 103.841562 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.246987 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.550197 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.202816 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88454507 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88454507 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4870617 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2557813 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4089779 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11518209 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3418412 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1747628 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2910585 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8076625 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 20088 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10280 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29520 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59888 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8289029 # number of demand (read+write) hits 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of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21670057148 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4598998555 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 17071058593 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21670057148 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5229872 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2719383 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4886123 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12835378 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3554117 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1808659 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3039276 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8402052 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 172426 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73113 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 220962 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466501 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8783989 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4528042 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7925399 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21237430 # number of demand (read+write) accesses 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62891 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 190739 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406304 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 503090 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 223405 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 908570 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1635065 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 655764 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 286296 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1099309 # number of overall misses +system.cpu0.dcache.overall_misses::total 2041369 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2292566250 # number of ReadReq miss cycles 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-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4757652042 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6680332042 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1922680000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4757652042 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6680332042 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004070 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110598 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004223 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004070 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110598 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004223 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004070 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110598 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004223 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11988.427340 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12218.814555 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12151.603808 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11988.427340 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12218.814555 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12151.603808 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11988.427340 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12218.814555 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12151.603808 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22336 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22336 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22336 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22336 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22336 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22336 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 159327 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 372409 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 531736 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 159327 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 372409 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 531736 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 159327 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 372409 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 531736 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1905663500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4555263703 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6460927203 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1905663500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4555263703 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6460927203 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1905663500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4555263703 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6460927203 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004073 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004073 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004073 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.629641 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604022160 # number of cpu cycles simulated +system.cpu1.numCycles 2604019962 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35714054 # Number of instructions committed -system.cpu1.committedOps 69387825 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64459883 # Number of integer alu accesses +system.cpu1.committedInsts 35730684 # Number of instructions committed +system.cpu1.committedOps 69408718 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64481893 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 492416 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6558216 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64459883 # number of integer instructions +system.cpu1.num_func_calls 491880 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6558534 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64481893 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119340959 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55539831 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119402180 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55560948 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36447320 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27215061 # number of times the CC registers were written -system.cpu1.num_mem_refs 4790084 # number of memory refs -system.cpu1.num_load_insts 2979771 # Number of load instructions -system.cpu1.num_store_insts 1810313 # Number of store instructions -system.cpu1.num_idle_cycles 2477161896.436619 # Number of idle cycles -system.cpu1.num_busy_cycles 126860263.563381 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048717 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951283 # Percentage of idle cycles -system.cpu1.Branches 7226981 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35150 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64505894 92.96% 93.01% # Class of executed instruction -system.cpu1.op_class::IntMult 31723 0.05% 93.06% # Class of executed instruction -system.cpu1.op_class::IntDiv 25263 0.04% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::MemRead 2979771 4.29% 97.39% # Class of executed instruction -system.cpu1.op_class::MemWrite 1810313 2.61% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36459460 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27231683 # number of times the CC registers were written +system.cpu1.num_mem_refs 4801643 # number of memory refs +system.cpu1.num_load_insts 2988079 # Number of load instructions +system.cpu1.num_store_insts 1813564 # Number of store instructions +system.cpu1.num_idle_cycles 2476018804.880995 # Number of idle cycles +system.cpu1.num_busy_cycles 128001157.119005 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049155 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950845 # Percentage of idle cycles +system.cpu1.Branches 7226738 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34859 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64514544 92.95% 93.00% # Class of executed instruction +system.cpu1.op_class::IntMult 31705 0.05% 93.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 26275 0.04% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::MemRead 2988079 4.31% 97.39% # Class of executed instruction +system.cpu1.op_class::MemWrite 1813564 2.61% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69388114 # Class of executed instruction +system.cpu1.op_class::total 69409026 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29235559 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29235559 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 325219 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26520697 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25831839 # Number of BTB hits +system.cpu2.branchPred.lookups 29092929 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29092929 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 315476 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26409431 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25746575 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.402564 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 591824 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 65511 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154416401 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.490078 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 584007 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63229 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153281353 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10884284 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 144162908 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29235559 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26423663 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 142028644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 680270 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 102603 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9165 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 58663 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 3537 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 505 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3520608 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 170393 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3486 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 153432274 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.849912 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.030749 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10494646 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143459530 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29092929 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26330582 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 141345595 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 659748 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 97189 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 4757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7888 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 55541 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 2125 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3459376 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 164097 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3515 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152337401 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.854593 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.033085 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98146892 63.97% 63.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 849455 0.55% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23639563 15.41% 79.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 596355 0.39% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 820460 0.53% 80.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 843182 0.55% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 578600 0.38% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 712944 0.46% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27244823 17.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 97296263 63.87% 63.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 832536 0.55% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23575408 15.48% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 586344 0.38% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 814239 0.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 832677 0.55% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 567105 0.37% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 704147 0.46% 82.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27128682 17.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 153432274 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189329 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.933598 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10016257 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93700057 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23552939 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5059225 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 340786 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 280915475 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 340786 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12183481 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76207577 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4633489 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26208589 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13095410 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 279683437 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 223314 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5946104 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 66230 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4950669 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 334110880 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 610223912 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 374707495 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321802825 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12308055 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 159496 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160992 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24728287 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6624186 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3707561 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 399799 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 335575 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 277732310 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 423659 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 275640781 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 103956 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8785176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13632215 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64646 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 153432274 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.796498 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.396081 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 152337401 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189801 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.935923 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9688238 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 93124886 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23395204 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5013369 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 330525 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279674043 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 330525 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11836052 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76001562 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4488572 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 26027497 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12868079 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278471354 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 223428 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5927671 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 64367 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4764004 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 332707542 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 607302278 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 372965322 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 116 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320669422 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12038120 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 154906 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 156494 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24500450 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6532282 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3632430 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 395237 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325236 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276569941 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 416887 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274532538 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 100855 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8584816 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13350787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62925 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152337401 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.802135 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.398465 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90704132 59.12% 59.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5447937 3.55% 62.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3973753 2.59% 65.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3694975 2.41% 67.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22399331 14.60% 82.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2621812 1.71% 83.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23895005 15.57% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 478633 0.31% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 216696 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 89943207 59.04% 59.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5345468 3.51% 62.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3937636 2.58% 65.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3657575 2.40% 67.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22350485 14.67% 82.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2587133 1.70% 83.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23826816 15.64% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 472076 0.31% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 217005 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 153432274 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152337401 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1775129 86.29% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 6 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 95 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 220574 10.72% 97.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 61430 2.99% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1755222 86.36% 86.36% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 86.36% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 168 0.01% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 216539 10.65% 97.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 60595 2.98% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 78003 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 265083835 96.17% 96.20% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56667 0.02% 96.22% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50646 0.02% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6950861 2.52% 98.76% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3420769 1.24% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 75570 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264135020 96.21% 96.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 55664 0.02% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49906 0.02% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6866354 2.50% 98.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3350024 1.22% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 275640781 # Type of FU issued -system.cpu2.iq.rate 1.785049 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2057234 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007463 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 706874938 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 286945707 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 274032875 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 88 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 277619970 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 42 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 720639 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274532538 # Type of FU issued +system.cpu2.iq.rate 1.791037 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2032524 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007404 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 703535734 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285575754 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272952384 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 276489433 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 59 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 719306 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1236107 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6357 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5250 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 663784 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1204229 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6084 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4820 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 645551 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755898 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23011 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 756143 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21686 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 340786 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 71022096 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1766284 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 278155969 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 42225 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6624208 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3707561 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 245817 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 196681 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1270617 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5250 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 184655 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 193373 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 378028 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 275054919 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6809103 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 532643 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 330525 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70849508 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1741832 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276986828 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 38338 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6532282 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3632430 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 240586 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 193301 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1249611 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4820 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 179927 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 186201 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 366128 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273965652 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6730604 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 516589 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10142277 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27929616 # Number of branches executed -system.cpu2.iew.exec_stores 3333174 # Number of stores executed -system.cpu2.iew.exec_rate 1.781255 # Inst execution rate -system.cpu2.iew.wb_sent 274858802 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 274032897 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213637344 # num instructions producing a value -system.cpu2.iew.wb_consumers 350353641 # num instructions consuming a value +system.cpu2.iew.exec_refs 9996676 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27816636 # Number of branches executed +system.cpu2.iew.exec_stores 3266072 # Number of stores executed +system.cpu2.iew.exec_rate 1.787338 # Inst execution rate +system.cpu2.iew.wb_sent 273775485 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272952416 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212880444 # num instructions producing a value +system.cpu2.iew.wb_consumers 349125324 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.774636 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609776 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.780728 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609754 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9127323 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 359013 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 328005 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152066658 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.769136 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.649747 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8921992 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 353962 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 318190 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 151004847 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.775201 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.653055 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94590362 62.20% 62.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4261266 2.80% 65.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1284145 0.84% 65.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24598382 16.18% 82.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1032712 0.68% 82.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 681511 0.45% 83.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 477761 0.31% 83.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23127222 15.21% 98.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2013297 1.32% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 93801921 62.12% 62.12% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4186228 2.77% 64.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1259762 0.83% 65.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24518557 16.24% 81.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1012800 0.67% 82.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 677237 0.45% 83.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 473264 0.31% 83.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23075029 15.28% 98.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2000049 1.32% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152066658 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136342288 # Number of instructions committed -system.cpu2.commit.committedOps 269026601 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 151004847 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135819902 # Number of instructions committed +system.cpu2.commit.committedOps 268063987 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8431878 # Number of memory references committed -system.cpu2.commit.loads 5388101 # Number of loads committed -system.cpu2.commit.membars 162694 # Number of memory barriers committed -system.cpu2.commit.branches 27513301 # Number of branches committed +system.cpu2.commit.refs 8314932 # Number of memory references committed +system.cpu2.commit.loads 5328053 # Number of loads committed +system.cpu2.commit.membars 161474 # Number of memory barriers committed +system.cpu2.commit.branches 27411077 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245807321 # Number of committed integer instructions. -system.cpu2.commit.function_calls 438928 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 45809 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 260445608 96.81% 96.83% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 54412 0.02% 96.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48894 0.02% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5388101 2.00% 98.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3043777 1.13% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244897516 # Number of committed integer instructions. +system.cpu2.commit.function_calls 434912 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44620 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 259602696 96.84% 96.86% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 53542 0.02% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48197 0.02% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5328053 1.99% 98.89% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2986879 1.11% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 269026601 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2013297 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 268063987 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2000049 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 428179753 # The number of ROB reads -system.cpu2.rob.rob_writes 557679634 # The number of ROB writes -system.cpu2.timesIdled 117886 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 984127 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4904701568 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136342288 # Number of Instructions Simulated -system.cpu2.committedOps 269026601 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.132564 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.132564 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882952 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882952 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 366241285 # number of integer regfile reads -system.cpu2.int_regfile_writes 219634896 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads +system.cpu2.rob.rob_reads 425964171 # The number of ROB reads +system.cpu2.rob.rob_writes 555310468 # The number of ROB writes +system.cpu2.timesIdled 112460 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 943952 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4909839532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135819902 # Number of Instructions Simulated +system.cpu2.committedOps 268063987 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.128563 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.128563 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.886082 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.886082 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364708409 # number of integer regfile reads +system.cpu2.int_regfile_writes 218787106 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72944 # number of floating regfile reads system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139741848 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107405291 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89464185 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137179 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554524 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554524 # Transaction distribution +system.cpu2.cc_regfile_reads 139159619 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107004309 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89032423 # number of misc regfile reads +system.cpu2.misc_regfile_writes 133306 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554527 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554527 # Transaction distribution system.iobus.trans_dist::WriteReq 57693 # Transaction distribution system.iobus.trans_dist::WriteResp 10973 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution @@ -1148,11 +1156,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 7129192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227766 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227772 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -1172,24 +1180,24 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 3570795 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605211 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2723904 # Layer occupancy (ticks) +system.iobus.pkt_size::total 6605235 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2673040 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5226000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4313000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1197,64 +1205,64 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 355000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 345000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10403000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10349000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 252354975 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 277910069 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303598000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 302790000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31582004 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 34215251 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1142000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1117000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47566 # number of replacements -system.iocache.tags.tagsinuse 0.080066 # Cycle average of tags in use +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.087266 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47582 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.080066 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005004 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005004 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000571413009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.087266 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005454 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005454 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428589 # Number of tag accesses -system.iocache.tags.data_accesses 428589 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 901 # number of ReadReq misses -system.iocache.ReadReq_misses::total 901 # number of ReadReq misses +system.iocache.tags.tag_accesses 428616 # Number of tag accesses +system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 901 # number of demand (read+write) misses -system.iocache.demand_misses::total 901 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 901 # number of overall misses -system.iocache.overall_misses::total 901 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129757279 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129757279 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 6940731692 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6940731692 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 129757279 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 129757279 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 129757279 # number of overall miss cycles -system.iocache.overall_miss_latency::total 129757279 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 901 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 901 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses +system.iocache.demand_misses::total 904 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses +system.iocache.overall_misses::total 904 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131125053 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131125053 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7701347765 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 7701347765 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 131125053 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 131125053 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 131125053 # number of overall miss cycles +system.iocache.overall_miss_latency::total 131125053 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 901 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 901 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 901 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 901 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1263,311 +1271,311 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144014.738069 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 144014.738069 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 148560.181764 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 148560.181764 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 144014.738069 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 144014.738069 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 144014.738069 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 144014.738069 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 39427 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145049.837389 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 164840.491545 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 164840.491545 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145049.837389 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145049.837389 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 44239 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5130 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5740 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.685575 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.707143 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 749 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 26264 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 26264 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 749 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 749 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 749 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90783279 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90783279 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 5574995700 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 5574995700 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 90783279 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 90783279 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 90783279 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 90783279 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.831299 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.831299 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.562158 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.562158 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.831299 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.831299 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.831299 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.831299 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 121205.979973 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212267.579196 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212267.579196 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 121205.979973 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 121205.979973 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 737 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28920 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 28920 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 737 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 737 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 737 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92773553 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6197505767 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6197505767 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 92773553 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 92773553 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.815265 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.619007 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.619007 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.815265 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.815265 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 125879.990502 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 214298.263036 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214298.263036 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104681 # number of replacements -system.l2c.tags.tagsinuse 64826.811839 # Cycle average of tags in use -system.l2c.tags.total_refs 3703362 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168901 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.926229 # Average number of references to valid blocks. +system.l2c.tags.replacements 104557 # number of replacements +system.l2c.tags.tagsinuse 64826.146133 # Cycle average of tags in use +system.l2c.tags.total_refs 3692284 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168716 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.884611 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51337.140952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1734.424462 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4936.447431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 379.153025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1982.017983 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.155297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 876.173345 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3570.165084 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.783343 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51357.956330 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134652 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1732.560753 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4954.090850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 380.669805 # Average occupied blocks per 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55177.106921 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59121.672710 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57409.961621 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56676.241754 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61155.346743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59803.133457 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56676.241754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61155.346743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59803.133457 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1693,66 +1707,62 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5119623 # Transaction distribution -system.membus.trans_dist::ReadResp 5119621 # Transaction distribution -system.membus.trans_dist::WriteReq 13885 # Transaction distribution -system.membus.trans_dist::WriteResp 13885 # Transaction distribution -system.membus.trans_dist::Writeback 143242 # Transaction distribution +system.membus.trans_dist::ReadReq 5119668 # Transaction distribution +system.membus.trans_dist::ReadResp 5119668 # Transaction distribution +system.membus.trans_dist::WriteReq 13886 # Transaction distribution +system.membus.trans_dist::WriteResp 13886 # Transaction distribution +system.membus.trans_dist::Writeback 143068 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1670 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1670 # Transaction distribution -system.membus.trans_dist::ReadExReq 130030 # Transaction distribution -system.membus.trans_dist::ReadExResp 130030 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1653 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1653 # Transaction distribution +system.membus.trans_dist::ReadExReq 130108 # Transaction distribution +system.membus.trans_dist::ReadExResp 130108 # Transaction distribution system.membus.trans_dist::MessageReq 1666 # Transaction distribution system.membus.trans_dist::MessageResp 1666 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039944 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455611 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10624751 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141603 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141603 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10769686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3040070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10624915 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141621 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141621 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10769868 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570795 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079885 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17550016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27200696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6014848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6014848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33222208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 744 # Total snoops (count) -system.membus.snoop_fanout::samples 370602 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6080137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17551104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27202036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6015808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33224508 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 602 # Total snoops (count) +system.membus.snoop_fanout::samples 370472 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370602 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 370472 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370602 # Request fanout histogram -system.membus.reqLayer0.occupancy 163555999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 370472 # Request fanout histogram +system.membus.reqLayer0.occupancy 162446500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314970500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 314906500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2284000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2234000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1078528499 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1120775500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1142000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1117000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1669525375 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1662967675 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 33021996 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 35567749 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1766,52 +1776,51 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7445520 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7444981 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13887 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13887 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1547770 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 26264 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1672 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291256 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291256 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740744 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14998032 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 215574 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17027929 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55702976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213603640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 275304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 788512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270370432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 71210 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4262409 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011172 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105107 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7434879 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7434349 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1546924 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 28920 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291412 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1730144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14995223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73480 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207718 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17006565 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55364032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213483380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 273608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 760144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 269881164 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 70776 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4251023 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011203 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105249 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4214788 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47621 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4203399 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4262409 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5252515580 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4251023 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5194614325 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 954000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2476922699 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2395792281 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4880781676 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4837647628 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 25221399 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 25185912 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 92014088 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 87831597 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |