diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
3 files changed, 3774 insertions, 3732 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index ebffe6201..6393b5a08 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.122213 # Number of seconds simulated -sim_ticks 5122212682000 # Number of ticks simulated -final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.130109 # Number of seconds simulated +sim_ticks 5130108675000 # Number of ticks simulated +final_tick 5130108675000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178126 # Simulator instruction rate (inst/s) -host_op_rate 352092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2236626113 # Simulator tick rate (ticks/s) -host_mem_usage 810964 # Number of bytes of host memory used -host_seconds 2290.15 # Real time elapsed on the host -sim_insts 407934867 # Number of instructions simulated -sim_ops 806343968 # Number of ops (including micro ops) simulated +host_inst_rate 175723 # Simulator instruction rate (inst/s) +host_op_rate 347336 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2210269457 # Simulator tick rate (ticks/s) +host_mem_usage 810456 # Number of bytes of host memory used +host_seconds 2321.03 # Real time elapsed on the host +sim_insts 407858109 # Number of instructions simulated +sim_ops 806179275 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10801152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1044544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10779584 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11881280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9569088 # Number of bytes written to this memory -system.physmem.bytes_written::total 9569088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168768 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11857088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1044544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1044544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9583168 # Number of bytes written to this memory +system.physmem.bytes_written::total 9583168 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 67 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168431 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185645 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149517 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149517 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2108689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2319560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1868155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1868155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1868155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2108689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4187715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185645 # Number of read requests accepted -system.physmem.writeReqs 196237 # Number of write requests accepted -system.physmem.readBursts 185645 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196237 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11872960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 10880320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11881280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12559168 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26214 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1708 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11253 # Per bank write bursts -system.physmem.perBankRdBursts::1 10547 # Per bank write bursts -system.physmem.perBankRdBursts::2 11972 # Per bank write bursts -system.physmem.perBankRdBursts::3 11655 # Per bank write bursts -system.physmem.perBankRdBursts::4 11971 # Per bank write bursts -system.physmem.perBankRdBursts::5 11254 # Per bank write bursts -system.physmem.perBankRdBursts::6 11364 # Per bank write bursts -system.physmem.perBankRdBursts::7 11315 # Per bank write bursts -system.physmem.perBankRdBursts::8 11445 # Per bank write bursts -system.physmem.perBankRdBursts::9 11672 # Per bank write bursts -system.physmem.perBankRdBursts::10 11062 # Per bank write bursts -system.physmem.perBankRdBursts::11 11423 # Per bank write bursts -system.physmem.perBankRdBursts::12 12308 # Per bank write bursts -system.physmem.perBankRdBursts::13 12737 # Per bank write bursts -system.physmem.perBankRdBursts::14 11748 # Per bank write bursts -system.physmem.perBankRdBursts::15 11789 # Per bank write bursts -system.physmem.perBankWrBursts::0 11864 # Per bank write bursts -system.physmem.perBankWrBursts::1 10686 # Per bank write bursts -system.physmem.perBankWrBursts::2 10651 # Per bank write bursts -system.physmem.perBankWrBursts::3 9860 # Per bank write bursts -system.physmem.perBankWrBursts::4 10294 # Per bank write bursts -system.physmem.perBankWrBursts::5 10368 # Per bank write bursts -system.physmem.perBankWrBursts::6 9733 # Per bank write bursts -system.physmem.perBankWrBursts::7 9712 # Per bank write bursts -system.physmem.perBankWrBursts::8 9632 # Per bank write bursts -system.physmem.perBankWrBursts::9 10471 # Per bank write bursts -system.physmem.perBankWrBursts::10 10725 # Per bank write bursts -system.physmem.perBankWrBursts::11 10392 # Per bank write bursts -system.physmem.perBankWrBursts::12 11457 # Per bank write bursts -system.physmem.perBankWrBursts::13 11384 # Per bank write bursts -system.physmem.perBankWrBursts::14 11667 # Per bank write bursts -system.physmem.perBankWrBursts::15 11109 # Per bank write bursts +system.physmem.num_reads::total 185267 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149737 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149737 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 203611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2101239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2311274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203611 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203611 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1868024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1868024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1868024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2101239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4179299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185267 # Number of read requests accepted +system.physmem.writeReqs 149737 # Number of write requests accepted +system.physmem.readBursts 185267 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149737 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11846656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue +system.physmem.bytesWritten 9581440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11857088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9583168 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48775 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11590 # Per bank write bursts +system.physmem.perBankRdBursts::1 11256 # Per bank write bursts +system.physmem.perBankRdBursts::2 12288 # Per bank write bursts +system.physmem.perBankRdBursts::3 11911 # Per bank write bursts +system.physmem.perBankRdBursts::4 11840 # Per bank write bursts +system.physmem.perBankRdBursts::5 11665 # Per bank write bursts +system.physmem.perBankRdBursts::6 10867 # Per bank write bursts +system.physmem.perBankRdBursts::7 10808 # Per bank write bursts +system.physmem.perBankRdBursts::8 11222 # Per bank write bursts +system.physmem.perBankRdBursts::9 11056 # Per bank write bursts +system.physmem.perBankRdBursts::10 11302 # Per bank write bursts +system.physmem.perBankRdBursts::11 11775 # Per bank write bursts +system.physmem.perBankRdBursts::12 11547 # Per bank write bursts +system.physmem.perBankRdBursts::13 12196 # Per bank write bursts +system.physmem.perBankRdBursts::14 11932 # Per bank write bursts +system.physmem.perBankRdBursts::15 11849 # Per bank write bursts +system.physmem.perBankWrBursts::0 10246 # Per bank write bursts +system.physmem.perBankWrBursts::1 9545 # Per bank write bursts +system.physmem.perBankWrBursts::2 9025 # Per bank write bursts +system.physmem.perBankWrBursts::3 8913 # Per bank write bursts +system.physmem.perBankWrBursts::4 9024 # Per bank write bursts +system.physmem.perBankWrBursts::5 9097 # Per bank write bursts +system.physmem.perBankWrBursts::6 8779 # Per bank write bursts +system.physmem.perBankWrBursts::7 8697 # Per bank write bursts +system.physmem.perBankWrBursts::8 8886 # Per bank write bursts +system.physmem.perBankWrBursts::9 9043 # Per bank write bursts +system.physmem.perBankWrBursts::10 9545 # Per bank write bursts +system.physmem.perBankWrBursts::11 9380 # Per bank write bursts +system.physmem.perBankWrBursts::12 9802 # Per bank write bursts +system.physmem.perBankWrBursts::13 9849 # Per bank write bursts +system.physmem.perBankWrBursts::14 10052 # Per bank write bursts +system.physmem.perBankWrBursts::15 9827 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 85 # Number of times write queue was full causing retry -system.physmem.totGap 5122212630000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 5130108625500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185645 # Read request sizes (log2) +system.physmem.readPktSize::6 185267 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196237 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 171240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149737 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,302 +156,301 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 73901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.887796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.352303 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.737558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28243 38.22% 38.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17330 23.45% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7468 10.11% 71.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4217 5.71% 77.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3016 4.08% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1973 2.67% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1390 1.88% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1267 1.71% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8997 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 73901 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6788 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.329258 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 584.024068 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6787 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 72239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.626919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.108811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.147383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27668 38.30% 38.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17613 24.38% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7498 10.38% 73.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4242 5.87% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2823 3.91% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1928 2.67% 85.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1515 2.10% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1131 1.57% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7821 10.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 72239 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7351 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.179159 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 561.374907 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7350 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6788 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6788 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.044932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.591825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 43.260290 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6382 94.02% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 87 1.28% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 9 0.13% 95.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 9 0.13% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 22 0.32% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 15 0.22% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 29 0.43% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 26 0.38% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 35 0.52% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 9 0.13% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 41 0.60% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 54 0.80% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.10% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.09% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.01% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.06% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.03% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.04% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.07% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 19 0.28% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 6 0.09% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6788 # Writes before turning the bus around for reads -system.physmem.totQLat 2015945224 # Total ticks spent queuing -system.physmem.totMemAccLat 5494351474 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 927575000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10866.75 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7351 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.365937 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.603384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.112022 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6287 85.53% 85.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 96 1.31% 86.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 185 2.52% 89.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 82 1.12% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 111 1.51% 91.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 202 2.75% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.42% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.19% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.19% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.14% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.12% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 246 3.35% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 7 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.19% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7351 # Writes before turning the bus around for reads +system.physmem.totQLat 1992019456 # Total ticks spent queuing +system.physmem.totMemAccLat 5462719456 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 925520000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10761.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29616.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29511.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.03 # Average write queue length when enqueuing -system.physmem.readRowHits 152167 # Number of row buffer hits during reads -system.physmem.writeRowHits 129451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes -system.physmem.avgGap 13413076.89 # Average gap between requests -system.physmem.pageHitRate 79.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 269256960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 146916000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 712374000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 538928640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129214187775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2959979121750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3425418506805 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.738637 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4924130039468 # Time in different power states -system.physmem_0.memoryStateTime::REF 171041780000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing +system.physmem.readRowHits 151846 # Number of row buffer hits during reads +system.physmem.writeRowHits 110728 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.95 # Row buffer hit rate for writes +system.physmem.avgGap 15313574.24 # Average gap between requests +system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 269393040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 146990250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 719355000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 475152480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335073401520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129448929735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2964510370500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3430643592525 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.727957 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4931666056220 # Time in different power states +system.physmem_0.memoryStateTime::REF 171305420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27040752032 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27131976280 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 289434600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 157925625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 734635200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 562703760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334557721680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129751534755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2959507764750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3425561720370 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.766596 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4923333713433 # Time in different power states -system.physmem_1.memoryStateTime::REF 171041780000 # Time in different power states +system.physmem_1.actEnergy 276733800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 150995625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 724448400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 494968320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335073401520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129698055360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2964291831000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3430710434025 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.740988 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4931307220986 # Time in different power states +system.physmem_1.memoryStateTime::REF 171305420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27832687817 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27495924014 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86818912 # Number of BP lookups -system.cpu.branchPred.condPredicted 86818912 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 895085 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80098723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78142837 # Number of BTB hits +system.cpu.branchPred.lookups 86802866 # Number of BP lookups +system.cpu.branchPred.condPredicted 86802866 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 898884 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79915985 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78142205 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.558156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1551403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180089 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.780444 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1557172 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181109 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449999443 # number of cpu cycles simulated +system.cpu.numCycles 449354840 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27536923 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428761982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86818912 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79694240 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418469892 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1877186 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 142405 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 58257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 203994 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 110 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 541 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9116293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 453128 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4723 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447350715 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.891249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.050769 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27419696 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 428691862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86802866 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79699377 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417944649 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1884104 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 141232 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 57475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 210217 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 60 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 747 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9135683 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 451645 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5364 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 446716128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.893620 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051973 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 282061925 63.05% 63.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2147503 0.48% 63.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72168287 16.13% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1568006 0.35% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2127596 0.48% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2318806 0.52% 81.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1512611 0.34% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1884650 0.42% 81.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81561331 18.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281460190 63.01% 63.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2138894 0.48% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72152839 16.15% 79.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1576063 0.35% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2129707 0.48% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2325949 0.52% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1505469 0.34% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1859854 0.42% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81567163 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447350715 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192931 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952806 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22908567 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 265367852 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150702709 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7432994 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 938593 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837990299 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 938593 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25758226 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223276953 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12890661 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154592541 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29893741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834466404 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 451836 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12178537 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 145180 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14794285 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 996780528 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1812316725 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114082490 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 470 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964296204 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32484322 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 461178 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 464876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 38644871 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17242919 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10123129 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1280249 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1072002 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828945592 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1192163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823760090 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 244912 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23793782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 35793426 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 146866 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447350715 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.841419 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.417821 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 446716128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193172 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954016 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22817532 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264818622 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150719822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7418100 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 942052 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837890793 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 942052 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25656597 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 222831809 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12884327 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154608390 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29792953 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834381209 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 449377 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12218260 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 146025 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14738284 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 996692347 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1812155414 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1113986633 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 357 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964101925 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32590420 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 461964 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 466029 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38550499 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17267645 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10120270 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1295034 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1078818 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828854264 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1188467 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823634023 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 239226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23863451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 35922872 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 148640 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 446716128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418621 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263279849 58.85% 58.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13891965 3.11% 61.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9851915 2.20% 64.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7048956 1.58% 65.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74303394 16.61% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4391366 0.98% 83.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72807233 16.28% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1204673 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571364 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262749029 58.82% 58.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13824325 3.09% 61.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9784338 2.19% 64.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7058515 1.58% 65.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74344613 16.64% 82.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4389971 0.98% 83.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72797188 16.30% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1191150 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 576999 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447350715 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 446716128 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1986394 72.18% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 608344 22.10% 94.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 157420 5.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1965794 71.96% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 607707 22.24% 94.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 158405 5.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 285236 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795541833 96.57% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150365 0.02% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 127447 0.02% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 286388 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795396124 96.57% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150331 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 127202 0.02% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 108 0.00% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 98 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued @@ -475,98 +474,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18320687 2.22% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9334414 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18333764 2.23% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9340116 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823760090 # Type of FU issued -system.cpu.iq.rate 1.830580 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2752158 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003341 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2097867450 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 853943468 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819213197 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 630 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 182 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826226763 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1860072 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823634023 # Type of FU issued +system.cpu.iq.rate 1.832926 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2731906 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003317 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2096954851 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 853918294 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819080568 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 454 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 494 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826079323 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1864091 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3252614 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 3276332 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15288 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14318 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1702580 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1695886 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2208153 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72229 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207587 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 71306 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 938593 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 204923881 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10223668 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830137755 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 158534 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17242919 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10123129 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 698460 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 397050 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8973453 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 942052 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 204779875 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9950427 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830042731 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 154301 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17267645 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10120270 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 698404 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 395340 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8703386 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14318 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 514177 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 531213 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1045390 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822137992 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17928402 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1491599 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 517416 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 531852 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1049268 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822011733 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17933627 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1492341 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27038601 # number of memory reference insts executed -system.cpu.iew.exec_branches 83256358 # Number of branches executed -system.cpu.iew.exec_stores 9110199 # Number of stores executed -system.cpu.iew.exec_rate 1.826976 # Inst execution rate -system.cpu.iew.wb_sent 821634339 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819213379 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640695638 # num instructions producing a value -system.cpu.iew.wb_consumers 1049922326 # num instructions consuming a value +system.cpu.iew.exec_refs 27049256 # number of memory reference insts executed +system.cpu.iew.exec_branches 83240327 # Number of branches executed +system.cpu.iew.exec_stores 9115629 # Number of stores executed +system.cpu.iew.exec_rate 1.829315 # Inst execution rate +system.cpu.iew.wb_sent 821506514 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819080726 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640638640 # num instructions producing a value +system.cpu.iew.wb_consumers 1049832937 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.820476 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610231 # average fanout of values written-back +system.cpu.iew.wb_rate 1.822793 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610229 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23667492 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1045297 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 906773 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443789392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.816952 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.674122 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23734474 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1039827 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 910229 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443141458 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.819237 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.674506 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272960111 61.51% 61.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11180384 2.52% 64.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3592831 0.81% 64.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74586039 16.81% 81.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2426818 0.55% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1631046 0.37% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 941888 0.21% 82.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71056225 16.01% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5414050 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272292366 61.45% 61.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11181272 2.52% 63.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3605802 0.81% 64.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74611152 16.84% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2465682 0.56% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1626284 0.37% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 958421 0.22% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70995563 16.02% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5404916 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443789392 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407934867 # Number of instructions committed -system.cpu.commit.committedOps 806343968 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443141458 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407858109 # Number of instructions committed +system.cpu.commit.committedOps 806179275 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22410853 # Number of memory references committed -system.cpu.commit.loads 13990304 # Number of loads committed -system.cpu.commit.membars 471837 # Number of memory barriers committed -system.cpu.commit.branches 82192569 # Number of branches committed +system.cpu.commit.refs 22415696 # Number of memory references committed +system.cpu.commit.loads 13991312 # Number of loads committed +system.cpu.commit.membars 468143 # Number of memory barriers committed +system.cpu.commit.branches 82176077 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735158454 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155650 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171552 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783497766 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144918 0.02% 97.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121442 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735014201 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155537 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171593 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783328307 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144946 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121298 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -593,231 +592,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13987725 1.73% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8420549 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13988731 1.74% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8424384 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806343968 # Class of committed instruction -system.cpu.commit.bw_lim_events 5414050 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1268308634 # The number of ROB reads -system.cpu.rob.rob_writes 1663603607 # The number of ROB writes -system.cpu.timesIdled 289860 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2648728 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9794423343 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407934867 # Number of Instructions Simulated -system.cpu.committedOps 806343968 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.103116 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.103116 # CPI: Total CPI of All Threads -system.cpu.ipc 0.906523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.906523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091825743 # number of integer regfile reads -system.cpu.int_regfile_writes 655727641 # number of integer regfile writes -system.cpu.fp_regfile_reads 182 # number of floating regfile reads -system.cpu.cc_regfile_reads 416065488 # number of cc regfile reads -system.cpu.cc_regfile_writes 321934300 # number of cc regfile writes -system.cpu.misc_regfile_reads 265346710 # number of misc regfile reads -system.cpu.misc_regfile_writes 399949 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1659310 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993990 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19061899 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659822 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.484303 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993990 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 806179275 # Class of committed instruction +system.cpu.commit.bw_lim_events 5404916 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1267572015 # The number of ROB reads +system.cpu.rob.rob_writes 1663421472 # The number of ROB writes +system.cpu.timesIdled 288126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2638712 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9810859930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407858109 # Number of Instructions Simulated +system.cpu.committedOps 806179275 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.101743 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101743 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907653 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907653 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091670765 # number of integer regfile reads +system.cpu.int_regfile_writes 655627629 # number of integer regfile writes +system.cpu.fp_regfile_reads 158 # number of floating regfile reads +system.cpu.cc_regfile_reads 416000684 # number of cc regfile reads +system.cpu.cc_regfile_writes 321879904 # number of cc regfile writes +system.cpu.misc_regfile_reads 265310647 # number of misc regfile reads +system.cpu.misc_regfile_writes 400047 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1661478 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997539 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19061070 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1661990 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.468824 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997539 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88087332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88087332 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10917280 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10917280 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077307 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077307 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64579 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64579 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 18994587 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18994587 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19059166 # number of overall hits -system.cpu.dcache.overall_hits::total 19059166 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1807757 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1807757 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 333541 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 333541 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406408 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406408 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2141298 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2141298 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2547706 # number of overall misses -system.cpu.dcache.overall_misses::total 2547706 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27202744445 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27202744445 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13955718277 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13955718277 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41158462722 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41158462722 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41158462722 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41158462722 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12725037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12725037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8410848 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8410848 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 470987 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 470987 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21135885 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21135885 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21606872 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21606872 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142063 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.142063 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039656 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862886 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.862886 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101311 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101311 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15047.788196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15047.788196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41841.087833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41841.087833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19221.267998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19221.267998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16155.106877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16155.106877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 414660 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88124232 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88124232 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10914055 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10914055 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8079827 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8079827 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 64080 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 64080 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18993882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18993882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19057962 # number of overall hits +system.cpu.dcache.overall_hits::total 19057962 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1815960 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1815960 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334906 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334906 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406730 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406730 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2150866 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2150866 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2557596 # number of overall misses +system.cpu.dcache.overall_misses::total 2557596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27033028000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27033028000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13819339247 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13819339247 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40852367247 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40852367247 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40852367247 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40852367247 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12730015 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12730015 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8414733 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8414733 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 470810 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 470810 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21144748 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21144748 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21615558 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21615558 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142652 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039800 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039800 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863894 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.863894 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101721 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101721 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118322 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118322 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14886.356528 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14886.356528 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41263.337316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41263.337316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18993.450660 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18993.450660 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15972.955559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15972.955559 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 469124 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43514 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 51580 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.529347 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.095076 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560749 # number of writebacks -system.cpu.dcache.writebacks::total 1560749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 839489 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 839489 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 42702 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 42702 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 882191 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 882191 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 882191 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 882191 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968268 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968268 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290839 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290839 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402958 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402958 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1259107 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12344104823 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5960784250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5960784250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25178573591 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25178573591 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31139357841 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31139357841 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97454292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97454292000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593348000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593348000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100047640000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 100047640000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076092 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034579 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034579 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059572 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059572 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076923 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13255.078933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13255.078933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42443.086460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42443.086460 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14792.569573 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14792.569573 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency +system.cpu.dcache.writebacks::writebacks 1562865 # number of writebacks +system.cpu.dcache.writebacks::total 1562865 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 845003 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 845003 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44547 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44547 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 889550 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 889550 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 889550 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 889550 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970957 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 970957 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290359 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290359 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403239 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403239 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1261316 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1261316 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1664555 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1664555 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13875 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13875 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 616771 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 616771 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13333994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13333994500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12420799750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12420799750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6058828500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6058828500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25754794250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25754794250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31813622750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31813622750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793670000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793670000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2615433000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2615433000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100409103000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100409103000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.856479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.856479 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059652 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059652 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077007 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13732.837294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13732.837294 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42777.388509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42777.388509 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15025.403049 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15025.403049 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20418.986400 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20418.986400 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19112.389047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19112.389047 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.533133 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.533133 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188499.675676 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188499.675676 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162798.028766 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162798.028766 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 104942 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 77779 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.349233 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5097981011500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.263782 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.828986 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.828986 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 446439 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 446439 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 104946 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 104946 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 104946 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 104946 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 104946 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 104946 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 78849 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 78849 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 78849 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 78849 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 78849 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 78849 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 941548961 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 941548961 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 941548961 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 941548961 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 941548961 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 941548961 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 183795 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 183795 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 183795 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 183795 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 183795 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 183795 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11941.165532 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11941.165532 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11941.165532 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11941.165532 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11941.165532 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 72618 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.793557 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 113213 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 72633 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.558699 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5097094340500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.793557 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.924597 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.924597 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 447394 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 447394 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113219 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 113219 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113219 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 113219 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113219 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 113219 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 73652 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 73652 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 73652 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 73652 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 73652 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 73652 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 910717000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 910717000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 910717000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 910717000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 910717000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 910717000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 186871 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 186871 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 186871 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 186871 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 186871 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 186871 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394133 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394133 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394133 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394133 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394133 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394133 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12365.136045 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12365.136045 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12365.136045 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12365.136045 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12365.136045 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12365.136045 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,180 +825,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22745 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22745 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 78849 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 78849 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 78849 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 78849 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 78849 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 78849 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 823159683 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 823159683 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 823159683 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 823159683 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 823159683 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 823159683 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10439.697181 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10439.697181 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10439.697181 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 18815 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 18815 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 73652 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 73652 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 73652 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 73652 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 73652 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 73652 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 837065000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 837065000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 837065000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 837065000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 837065000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 837065000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394133 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394133 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394133 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394133 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11365.136045 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11365.136045 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11365.136045 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 996925 # number of replacements -system.cpu.icache.tags.tagsinuse 509.357790 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8050243 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 997437 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.070929 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148006664250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.357790 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994839 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994839 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 991040 # number of replacements +system.cpu.icache.tags.tagsinuse 509.607437 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8073267 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 991552 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.142051 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147914027500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.607437 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995327 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10113779 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10113779 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8050243 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8050243 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8050243 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8050243 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8050243 # number of overall hits -system.cpu.icache.overall_hits::total 8050243 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066046 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066046 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066046 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066046 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066046 # number of overall misses -system.cpu.icache.overall_misses::total 1066046 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14875004411 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14875004411 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14875004411 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14875004411 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14875004411 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14875004411 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9116289 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9116289 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9116289 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9116289 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9116289 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9116289 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116939 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116939 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.116939 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.116939 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.116939 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.116939 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13953.435791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13953.435791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13953.435791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13953.435791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13953.435791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7127 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10127588 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10127588 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8073267 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8073267 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8073267 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8073267 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8073267 # number of overall hits +system.cpu.icache.overall_hits::total 8073267 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1062411 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1062411 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1062411 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1062411 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1062411 # number of overall misses +system.cpu.icache.overall_misses::total 1062411 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14792091486 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14792091486 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14792091486 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14792091486 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14792091486 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14792091486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9135678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9135678 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9135678 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9135678 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9135678 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9135678 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116293 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116293 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116293 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116293 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116293 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116293 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.134725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13923.134725 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.134725 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13923.134725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.134725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13923.134725 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7978 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 382 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.900293 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.884817 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68556 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68556 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68556 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68556 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68556 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68556 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 997490 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 997490 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 997490 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 997490 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 997490 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 997490 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12688553873 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12688553873 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12688553873 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12688553873 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12688553873 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12688553873 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109418 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109418 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109418 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109418 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12720.482284 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12720.482284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12720.482284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12720.482284 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70501 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70501 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70501 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70501 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70501 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70501 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13114232487 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13114232487 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13114232487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13114232487 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13114232487 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13114232487 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108575 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108575 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108575 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108575 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13221.191930 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13221.191930 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13221.191930 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13221.191930 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13221.191930 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13221.191930 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13512 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.614352 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26763 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13525 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.978780 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5101180103500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.614352 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.413397 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.413397 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 15565 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.022675 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 26231 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 15578 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.683849 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102115273500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.022675 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376417 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376417 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 96721 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 96721 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26775 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26775 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 101828 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 101828 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26240 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26240 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26777 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26777 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26777 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26777 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14389 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14389 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14389 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14389 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14389 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14389 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 168738994 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 168738994 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 168738994 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 168738994 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 168738994 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 168738994 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41164 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41164 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26242 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26242 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26242 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26242 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16448 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 16448 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16448 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 16448 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16448 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 16448 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193358500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193358500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193358500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 193358500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193358500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 193358500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 42688 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 42688 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41166 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41166 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41166 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41166 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349553 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349553 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349536 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.349536 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349536 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.349536 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11726.943776 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11726.943776 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11726.943776 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11726.943776 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11726.943776 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 42690 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 42690 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 42690 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 42690 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.385307 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.385307 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.385289 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.385289 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.385289 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.385289 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11755.745379 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11755.745379 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11755.745379 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11755.745379 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11755.745379 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11755.745379 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1008,177 +1007,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3066 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3066 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14389 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14389 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14389 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14389 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14389 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14389 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147144512 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147144512 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147144512 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147144512 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147144512 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147144512 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.349553 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.349553 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.349536 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.349536 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.349536 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10226.180555 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10226.180555 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10226.180555 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3018 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3018 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16448 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16448 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16448 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 16448 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16448 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 16448 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 176910500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 176910500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 176910500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 176910500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 176910500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 176910500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.385307 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.385307 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.385289 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.385289 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.385289 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.385289 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10755.745379 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10755.745379 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10755.745379 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10755.745379 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112729 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64831.922119 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3833002 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176853 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.673378 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112892 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.691770 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4938747 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176773 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.938356 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50534.450143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.577905 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.126849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.817202 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11175.950019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771095 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000222 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047391 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 694 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7383 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35081373 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35081373 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12140 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 981027 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1334830 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2396575 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1586560 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1586560 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 50529.309735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 20.322898 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.136173 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3138.561208 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11131.361756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.771016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000310 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047891 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.169851 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989070 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63881 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54573 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974747 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43864381 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43864381 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1584698 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1584698 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 310 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 310 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154702 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154702 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 68578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 981027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1489532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2551277 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 68578 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12140 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 981027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1489532 # number of overall hits -system.cpu.l2cache.overall_hits::total 2551277 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16363 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35684 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52120 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1439 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1439 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134046 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134046 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169730 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186166 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169730 # number of overall misses -system.cpu.l2cache.overall_misses::total 186166 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6097000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 666500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1366410532 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3072121000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4445295032 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22717321 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22717321 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10374564266 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10374564266 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6097000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 666500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1366410532 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13446685266 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14819859298 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6097000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 666500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1366410532 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13446685266 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14819859298 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68644 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12147 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 997390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1370514 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2448695 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1586560 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1586560 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1749 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1749 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68644 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 997390 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1659262 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2737443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68644 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 997390 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1659262 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2737443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016406 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026037 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021285 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.822756 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.822756 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464232 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.464232 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000576 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016406 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102292 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.068007 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000576 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016406 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102292 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.068007 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92378.787879 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 95214.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83506.113304 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86092.394350 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 85289.620721 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15786.880473 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15786.880473 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77395.552765 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77395.552765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79605.617019 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92378.787879 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 95214.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83506.113304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79223.974937 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79605.617019 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 154215 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154215 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 975190 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 975190 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 67279 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 13917 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1337816 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1419012 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 67279 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 13917 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 975190 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1492031 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2548417 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 67279 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 13917 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 975190 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1492031 # number of overall hits +system.cpu.l2cache.overall_hits::total 2548417 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1787 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1787 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133737 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133737 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16323 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16323 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 67 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35675 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 35747 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 67 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16323 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169412 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185807 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 67 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16323 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169412 # number of overall misses +system.cpu.l2cache.overall_misses::total 185807 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23917000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23917000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10298204500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10298204500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1359330500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1359330500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 6177500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 415000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3065419500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3072012000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6177500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 415000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1359330500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13363624000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14729547000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6177500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 415000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1359330500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13363624000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14729547000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 1584698 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1584698 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2097 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2097 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287952 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287952 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 991513 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 991513 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 67346 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 13922 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1373491 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1454759 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 13922 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 991513 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1661443 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2734224 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 13922 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 991513 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1661443 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2734224 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.852170 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.852170 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.464442 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.464442 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016463 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016463 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000995 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000359 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.025974 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024572 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000995 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000359 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016463 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101967 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.067956 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000995 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000359 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016463 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101967 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.067956 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13383.883604 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13383.883604 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77003.405939 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77003.405939 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83277.001777 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83277.001777 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 92201.492537 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85926.264891 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85937.617143 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92201.492537 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83277.001777 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78882.393219 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79273.369679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92201.492537 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83277.001777 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78882.393219 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79273.369679 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1187,176 +1192,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102850 # number of writebacks -system.cpu.l2cache.writebacks::total 102850 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 103070 # number of writebacks +system.cpu.l2cache.writebacks::total 103070 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16361 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35683 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52117 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134046 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 134046 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169729 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 186163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2626180250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3793540968 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 26446420 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 26446420 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8698623734 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8698623734 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5264500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 578000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1161518218 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11324803984 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12492164702 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5264500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 578000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1161518218 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11324803984 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12492164702 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88988446000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88988446000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411352000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411352000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91399798000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91399798000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026036 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021284 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.822756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.822756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464232 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464232 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068006 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016404 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102292 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068006 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70993.106656 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73597.518426 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72788.935817 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18378.332175 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18378.332175 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64892.825851 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64892.825851 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79765.151515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 90 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 90 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1787 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1787 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133737 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133737 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16321 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16321 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 67 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35671 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35743 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 67 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16321 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185801 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 67 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16321 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169408 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185801 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 602896 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 602896 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13875 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13875 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 616771 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 616771 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37875000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37875000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8960834500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8960834500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1195971500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1195971500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 5507500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 365000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2711142000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2717014500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5507500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1195971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11671976500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12873820500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5507500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1195971500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11671976500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12873820500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257461500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257461500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2455867500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2455867500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92713329000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92713329000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.852170 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.852170 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464442 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464442 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025971 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024570 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067954 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000995 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000359 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067954 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21194.739787 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21194.739787 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67003.405939 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67003.405939 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73278.077324 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73278.077324 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76004.092961 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76015.289707 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73278.077324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68898.614587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69288.219654 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73278.077324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68898.614587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69288.219654 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.519035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.519035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176999.459459 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176999.459459 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.506314 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.506314 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1586560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 170238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8316168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63832960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207882816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 63315 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3059319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1734439 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1113474 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 991910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1465068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2973341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6222105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 35861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 172954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9404261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63456832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208155201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1084160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5514304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278210497 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 220375 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6313792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.033219 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179209 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6104051 96.68% 96.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 209741 3.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6313792 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4643672976 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 564000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1500637871 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1489388443 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3138590336 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3104272690 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 21588991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 24683477 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 118331389 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 110523908 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 223899 # Transaction distribution -system.iobus.trans_dist::ReadResp 223899 # Transaction distribution -system.iobus.trans_dist::WriteReq 57753 # Transaction distribution -system.iobus.trans_dist::WriteResp 11033 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.trans_dist::ReadReq 222096 # Transaction distribution +system.iobus.trans_dist::ReadResp 222096 # Transaction distribution +system.iobus.trans_dist::WriteReq 57708 # Transaction distribution +system.iobus.trans_dist::WriteResp 57708 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1366,21 +1382,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 468050 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 566590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 562892 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1390,19 +1406,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 240311 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3274683 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3272836 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3914184 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1414,7 +1430,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1432,177 +1448,179 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 257302678 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 242657095 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 457017000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50364257 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47572 # number of replacements -system.iocache.tags.tagsinuse 0.078977 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.103760 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4993305876000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.078977 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004936 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.004936 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4993210499000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103760 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006485 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006485 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428643 # Number of tag accesses -system.iocache.tags.data_accesses 428643 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses -system.iocache.demand_misses::total 907 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses -system.iocache.overall_misses::total 907 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142095944 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 142095944 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8602345477 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8602345477 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 142095944 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 142095944 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 142095944 # number of overall miss cycles -system.iocache.overall_miss_latency::total 142095944 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses +system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses +system.iocache.demand_misses::total 909 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses +system.iocache.overall_misses::total 909 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141558677 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141558677 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5512975418 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5512975418 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141558677 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141558677 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141558677 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141558677 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 156665.869901 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 184125.545313 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 184125.545313 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 156665.869901 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156665.869901 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 156665.869901 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 29724 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155730.117712 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118000.330009 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118000.330009 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 155730.117712 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 155730.117712 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 155730.117712 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4480 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.634821 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94520448 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6172895487 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6172895487 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94520448 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94520448 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94520448 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96108677 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3176975418 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3176975418 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 96108677 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96108677 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 96108677 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 104212.180816 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 132125.331485 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132125.331485 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 104212.180816 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 104212.180816 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105730.117712 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68000.330009 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68000.330009 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105730.117712 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105730.117712 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 657725 # Transaction distribution -system.membus.trans_dist::ReadResp 657721 # Transaction distribution -system.membus.trans_dist::WriteReq 13919 # Transaction distribution -system.membus.trans_dist::WriteResp 13919 # Transaction distribution -system.membus.trans_dist::Writeback 149517 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2208 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1727 # Transaction distribution -system.membus.trans_dist::ReadExReq 133760 # Transaction distribution -system.membus.trans_dist::ReadExResp 133758 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 4 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477841 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1715089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141457 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141457 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1859832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240311 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538377 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20214016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1635 # Total snoops (count) -system.membus.snoop_fanout::samples 1005577 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram +system.membus.trans_dist::ReadReq 602896 # Transaction distribution +system.membus.trans_dist::ReadResp 655847 # Transaction distribution +system.membus.trans_dist::WriteReq 13875 # Transaction distribution +system.membus.trans_dist::WriteResp 13875 # Transaction distribution +system.membus.trans_dist::Writeback 149737 # Transaction distribution +system.membus.trans_dist::CleanEvict 10183 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2524 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2074 # Transaction distribution +system.membus.trans_dist::ReadExReq 133454 # Transaction distribution +system.membus.trans_dist::ReadExResp 133450 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52973 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.trans_dist::BadAddressError 22 # Transaction distribution +system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 487788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 44 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1866481 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538381 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18425216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20202049 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23223657 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1607 # Total snoops (count) +system.membus.snoop_fanout::samples 1014551 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001618 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040197 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1012909 99.84% 99.84% # Request fanout histogram +system.membus.snoop_fanout::2 1642 0.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1005577 # Request fanout histogram -system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1014551 # Request fanout histogram +system.membus.reqLayer0.occupancy 354940000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388594500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1203162900 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1018302522 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2211768878 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2206598693 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 51465743 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 86075861 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 4c2a41024..7d82f190a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305853 # Number of seconds simulated -sim_ticks 5305853045500 # Number of ticks simulated -final_tick 5305853045500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305855 # Number of seconds simulated +sim_ticks 5305855051000 # Number of ticks simulated +final_tick 5305855051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178751 # Simulator instruction rate (inst/s) -host_op_rate 342595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8842177355 # Simulator tick rate (ticks/s) -host_mem_usage 856496 # Number of bytes of host memory used -host_seconds 600.06 # Real time elapsed on the host -sim_insts 107261902 # Number of instructions simulated -sim_ops 205578300 # Number of ops (including micro ops) simulated +host_inst_rate 186796 # Simulator instruction rate (inst/s) +host_op_rate 357991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9246678170 # Simulator tick rate (ticks/s) +host_mem_usage 1105624 # Number of bytes of host memory used +host_seconds 573.81 # Real time elapsed on the host +sim_insts 107186053 # Number of instructions simulated +sim_ops 205419480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11415232 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11415232 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9161984 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9161984 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 178363 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 178363 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 143156 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 143156 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2151441 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2151441 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1726769 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1726769 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3878211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3878211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 178363 # Number of read requests accepted -system.mem_ctrls.writeReqs 143156 # Number of write requests accepted -system.mem_ctrls.readBursts 178363 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 143156 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11360576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54656 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9153536 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11415232 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9161984 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 854 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11371136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11371136 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9131456 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9131456 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 177674 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 177674 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 142679 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 142679 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2143130 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2143130 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1721015 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1721015 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3864145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3864145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 177674 # Number of read requests accepted +system.mem_ctrls.writeReqs 142679 # Number of write requests accepted +system.mem_ctrls.readBursts 177674 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 142679 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11313280 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 57856 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9121152 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11371136 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9131456 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 904 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 135 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 10856 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10881 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10729 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11226 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11595 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 12060 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 11357 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10544 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 10640 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 10408 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 10338 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14247 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 10851 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10291 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10803 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10683 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 8741 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 8453 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8515 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9195 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9530 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9557 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 9142 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8665 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8844 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 8855 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 8455 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9314 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 8873 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 8616 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9161 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 9108 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 10805 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10794 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11389 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11550 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 12175 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 10978 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10407 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10706 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 10369 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10514 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 13718 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10819 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10294 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10714 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8779 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8773 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8745 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9209 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9395 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9648 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8754 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8594 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 8776 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8713 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8651 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9041 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 8739 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8605 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9111 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8985 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5305852911000 # Total gap between requests +system.mem_ctrls.totGap 5305854916500 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 178363 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 177674 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 143156 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 177440 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 69 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 142679 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 176703 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 67 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2057 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2808 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8578 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9141 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8600 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9229 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9219 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8361 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9057 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9077 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8449 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8526 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8348 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8471 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8060 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8092 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8178 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 7986 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 125 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 101 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 94 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 84 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 73 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 27 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 19 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2059 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2790 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8563 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9122 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8572 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9212 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9034 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9060 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8413 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8500 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8357 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8453 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8029 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8097 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8147 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 7952 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 85 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 89 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 75 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 18 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,213 +184,211 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60721 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 337.841076 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 199.411090 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 344.057801 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20489 33.74% 33.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14673 24.16% 57.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6364 10.48% 68.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3396 5.59% 73.98% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2745 4.52% 78.50% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1826 3.01% 81.51% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1362 2.24% 83.75% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1430 2.36% 86.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8436 13.89% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60721 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7928 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.388118 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 317.537098 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7922 99.92% 99.92% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::1024-2047 2 0.03% 99.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::2048-3071 2 0.03% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60336 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.676213 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 200.551275 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.723517 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20068 33.26% 33.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14736 24.42% 57.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6373 10.56% 68.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3491 5.79% 74.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2657 4.40% 78.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1861 3.08% 81.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1364 2.26% 83.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1338 2.22% 86.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8448 14.00% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60336 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7897 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.382170 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.489285 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7891 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7928 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7928 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.040363 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.696882 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 3.983964 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5814 73.34% 73.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 181 2.28% 75.79% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 14 0.18% 75.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 36 0.45% 76.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 489 6.17% 82.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 149 1.88% 84.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 53 0.67% 85.14% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 653 8.24% 93.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 113 1.43% 94.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 3 0.04% 94.84% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.01% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 312 3.94% 98.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 4 0.05% 98.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 10 0.13% 99.12% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 5 0.06% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 9 0.11% 99.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 9 0.11% 99.41% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 2 0.03% 99.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 4 0.05% 99.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 5 0.06% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.65% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 6 0.08% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 2 0.03% 99.75% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 1 0.01% 99.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 1 0.01% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::49 2 0.03% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7928 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1963261998 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5291555748 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 887545000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11060.07 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 7897 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7897 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.047106 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.696875 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 4.065797 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5800 73.45% 73.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 169 2.14% 75.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 37 0.47% 76.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 500 6.33% 82.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 145 1.84% 84.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 43 0.54% 85.13% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 653 8.27% 93.40% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 111 1.41% 94.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 12 0.15% 94.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 19 0.24% 95.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 304 3.85% 99.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.14% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 3 0.04% 99.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 6 0.08% 99.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.35% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.40% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.46% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.62% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.72% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 9 0.11% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::52 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 7897 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1934453242 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5248890742 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 883850000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10943.33 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29810.07 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 2.14 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 29693.33 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 2.13 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2.14 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 141459 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 118352 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.69 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 82.74 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 16502455.25 # Average gap between requests -system.mem_ctrls.pageHitRate 81.05 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 231139440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 126117750 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 696134400 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 465251040 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 149731396200 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3052164794250 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3549966942360 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 669.066980 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5077378950000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 177173880000 # Time in different power states +system.mem_ctrls.avgWrQLen 24.42 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 140774 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 118177 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.64 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.91 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 16562526.08 # Average gap between requests +system.mem_ctrls.pageHitRate 81.10 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 229839120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 125408250 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 694816200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 465892560 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 149179147425 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052653894750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549901616145 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.053686 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5078195767000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 51294057500 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 50484766750 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 227911320 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 124356375 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 688428000 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 461544480 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 149042883510 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3052768752750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3549865985715 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 669.047952 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5078391595500 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 177173880000 # Time in different power states +system.mem_ctrls_1.actEnergy 226301040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 123477750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 683982000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 457624080 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 148537848690 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3053216437500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549798288900 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.034212 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5079136661250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 177174140000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 50287445500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 49544125250 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10611706091 # number of cpu cycles simulated +system.cpu0.numCycles 10611710102 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 59111887 # Number of instructions committed -system.cpu0.committedOps 113456709 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 106426265 # Number of integer alu accesses +system.cpu0.committedInsts 59039296 # Number of instructions committed +system.cpu0.committedOps 113305650 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 106292214 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu0.num_func_calls 1016173 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10055603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 106426265 # number of integer instructions +system.cpu0.num_func_calls 1017385 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 10037497 # number of instructions that are conditional controls +system.cpu0.num_int_insts 106292214 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 200823032 # number of times the integer registers were read -system.cpu0.num_int_register_writes 90335124 # number of times the integer registers were written +system.cpu0.num_int_register_reads 200616677 # number of times the integer registers were read +system.cpu0.num_int_register_writes 90211380 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 61044422 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44109295 # number of times the CC registers were written -system.cpu0.num_mem_refs 12452626 # number of memory refs -system.cpu0.num_load_insts 7522002 # Number of load instructions -system.cpu0.num_store_insts 4930624 # Number of store instructions -system.cpu0.num_idle_cycles 10088968020.334099 # Number of idle cycles -system.cpu0.num_busy_cycles 522738070.665901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049261 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950739 # Percentage of idle cycles -system.cpu0.Branches 11433567 # Number of branches fetched -system.cpu0.op_class::No_OpClass 130284 0.11% 0.11% # Class of executed instruction -system.cpu0.op_class::IntAlu 100735872 88.79% 88.90% # Class of executed instruction -system.cpu0.op_class::IntMult 86129 0.08% 88.98% # Class of executed instruction -system.cpu0.op_class::IntDiv 56904 0.05% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatCvt 16 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.03% # Class of executed instruction -system.cpu0.op_class::MemRead 7517799 6.63% 95.65% # Class of executed instruction -system.cpu0.op_class::MemWrite 4930624 4.35% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 60966470 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44030878 # number of times the CC registers were written +system.cpu0.num_mem_refs 12456031 # number of memory refs +system.cpu0.num_load_insts 7518228 # Number of load instructions +system.cpu0.num_store_insts 4937803 # Number of store instructions +system.cpu0.num_idle_cycles 10088651138.334099 # Number of idle cycles +system.cpu0.num_busy_cycles 523058963.665901 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049291 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950709 # Percentage of idle cycles +system.cpu0.Branches 11416966 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131109 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 100580264 88.77% 88.88% # Class of executed instruction +system.cpu0.op_class::IntMult 86269 0.08% 88.96% # Class of executed instruction +system.cpu0.op_class::IntDiv 57079 0.05% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.01% # Class of executed instruction +system.cpu0.op_class::MemRead 7514027 6.63% 95.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 4937803 4.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 113457628 # Class of executed instruction +system.cpu0.op_class::total 113306567 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10608768454 # number of cpu cycles simulated +system.cpu1.numCycles 10608777066 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48150015 # Number of instructions committed -system.cpu1.committedOps 92121591 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88447957 # Number of integer alu accesses +system.cpu1.committedInsts 48146757 # Number of instructions committed +system.cpu1.committedOps 92113830 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88441893 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu1.num_func_calls 1752470 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8220366 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88447957 # number of integer instructions +system.cpu1.num_func_calls 1752446 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8219760 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88441893 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 171418672 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73201138 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171408328 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73196137 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 50927853 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 32747912 # number of times the CC registers were written -system.cpu1.num_mem_refs 14125902 # number of memory refs -system.cpu1.num_load_insts 9133895 # Number of load instructions -system.cpu1.num_store_insts 4992007 # Number of store instructions -system.cpu1.num_idle_cycles 10273983246.713898 # Number of idle cycles -system.cpu1.num_busy_cycles 334785207.286102 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031557 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968443 # Percentage of idle cycles -system.cpu1.Branches 10582274 # Number of branches fetched -system.cpu1.op_class::No_OpClass 169782 0.18% 0.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 77660290 84.30% 84.49% # Class of executed instruction -system.cpu1.op_class::IntMult 98483 0.11% 84.59% # Class of executed instruction -system.cpu1.op_class::IntDiv 71910 0.08% 84.67% # Class of executed instruction +system.cpu1.num_cc_register_reads 50924734 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 32745964 # number of times the CC registers were written +system.cpu1.num_mem_refs 14124901 # number of memory refs +system.cpu1.num_load_insts 9133293 # Number of load instructions +system.cpu1.num_store_insts 4991608 # Number of store instructions +system.cpu1.num_idle_cycles 10274072284.207695 # Number of idle cycles +system.cpu1.num_busy_cycles 334704781.792306 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031550 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968450 # Percentage of idle cycles +system.cpu1.Branches 10581617 # Number of branches fetched +system.cpu1.op_class::No_OpClass 169787 0.18% 0.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 77653530 84.30% 84.49% # Class of executed instruction +system.cpu1.op_class::IntMult 98479 0.11% 84.59% # Class of executed instruction +system.cpu1.op_class::IntDiv 71918 0.08% 84.67% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::FloatCvt 16 0.00% 84.67% # Class of executed instruction @@ -417,17 +415,17 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.67% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.67% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.67% # Class of executed instruction -system.cpu1.op_class::MemRead 9129754 9.91% 94.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 4992007 5.42% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 9129153 9.91% 94.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 4991608 5.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92122242 # Class of executed instruction +system.cpu1.op_class::total 92114491 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 857753 # Transaction distribution -system.iobus.trans_dist::ReadResp 857753 # Transaction distribution -system.iobus.trans_dist::WriteReq 36065 # Transaction distribution -system.iobus.trans_dist::WriteResp 36065 # Transaction distribution +system.iobus.trans_dist::ReadReq 842290 # Transaction distribution +system.iobus.trans_dist::ReadResp 842290 # Transaction distribution +system.iobus.trans_dist::WriteReq 35657 # Transaction distribution +system.iobus.trans_dist::WriteResp 35657 # Transaction distribution system.iobus.trans_dist::MessageReq 1791 # Transaction distribution system.iobus.trans_dist::MessageResp 1791 # Transaction distribution system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) @@ -440,15 +438,15 @@ system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 66 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 964 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14814 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 742772 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 729402 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1702492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1671974 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5284 # Packet count per connected master and slave (bytes) @@ -456,9 +454,9 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 396 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 28 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 384 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 30418 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12448 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) @@ -466,8 +464,8 @@ system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.p system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85378 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1791218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 84154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1759476 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) @@ -478,15 +476,15 @@ system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 33 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1928 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7407 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1485538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1458798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 316 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1970762 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1935448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3394 # Cumulative packet size per connected master and slave (bytes) @@ -494,9 +492,9 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 198 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 14 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15471 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15165 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15515 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15209 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) @@ -504,53 +502,53 @@ system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51075 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2028533 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 50000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 50463 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 1992607 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10224000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9032500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 154500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 940000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 97500 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 56000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 52500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 20660000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 20247500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1276000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1157500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 31144500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 30508000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 23664000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 20468500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 468374820 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 369412820 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 7594080 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7528580 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 1329500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 1593000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2404400 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2422900 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2023552000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1846190500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 60655000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 57610000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -567,48 +565,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10895286 # delay histogram for all message -system.ruby.delayHist::mean 0.442462 # delay histogram for all message -system.ruby.delayHist::stdev 1.830078 # delay histogram for all message -system.ruby.delayHist | 10293202 94.47% 94.47% | 1309 0.01% 94.49% | 600320 5.51% 100.00% | 166 0.00% 100.00% | 230 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10895286 # delay histogram for all message +system.ruby.delayHist::samples 10891010 # delay histogram for all message +system.ruby.delayHist::mean 0.442869 # delay histogram for all message +system.ruby.delayHist::stdev 1.830823 # delay histogram for all message +system.ruby.delayHist | 10288616 94.47% 94.47% | 1282 0.01% 94.48% | 600649 5.52% 100.00% | 161 0.00% 100.00% | 257 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10891010 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152835089 +system.ruby.outstanding_req_hist::samples 152756591 system.ruby.outstanding_req_hist::mean 1.000166 system.ruby.outstanding_req_hist::gmean 1.000115 -system.ruby.outstanding_req_hist::stdev 0.012900 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152809653 99.98% 99.98% | 25436 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152835089 -system.ruby.latency_hist::bucket_size 256 -system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 152835088 -system.ruby.latency_hist::mean 3.434218 -system.ruby.latency_hist::gmean 3.107238 -system.ruby.latency_hist::stdev 5.763390 -system.ruby.latency_hist | 152826003 99.99% 99.99% | 6324 0.00% 100.00% | 2683 0.00% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152835088 +system.ruby.outstanding_req_hist::stdev 0.012901 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152731162 99.98% 99.98% | 25429 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152756591 +system.ruby.latency_hist::bucket_size 128 +system.ruby.latency_hist::max_bucket 1279 +system.ruby.latency_hist::samples 152756590 +system.ruby.latency_hist::mean 3.433707 +system.ruby.latency_hist::gmean 3.107293 +system.ruby.latency_hist::stdev 5.733578 +system.ruby.latency_hist | 152719525 99.98% 99.98% | 28048 0.02% 99.99% | 2695 0.00% 100.00% | 3637 0.00% 100.00% | 2109 0.00% 100.00% | 523 0.00% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.latency_hist::total 152756590 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 150173511 +system.ruby.hit_latency_hist::samples 150094333 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150173511 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 150173511 -system.ruby.miss_latency_hist::bucket_size 256 -system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 2661577 -system.ruby.miss_latency_hist::mean 27.933971 -system.ruby.miss_latency_hist::gmean 22.542647 -system.ruby.miss_latency_hist::stdev 36.007178 -system.ruby.miss_latency_hist | 2652492 99.66% 99.66% | 6324 0.24% 99.90% | 2683 0.10% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2661577 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11100819 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 532265 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11633084 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 68582952 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 323144 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 68906096 # Number of cache demand accesses +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150094333 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 150094333 +system.ruby.miss_latency_hist::bucket_size 128 +system.ruby.miss_latency_hist::max_bucket 1279 +system.ruby.miss_latency_hist::samples 2662257 +system.ruby.miss_latency_hist::mean 27.885506 +system.ruby.miss_latency_hist::gmean 22.530762 +system.ruby.miss_latency_hist::stdev 35.745831 +system.ruby.miss_latency_hist | 2625192 98.61% 98.61% | 28048 1.05% 99.66% | 2695 0.10% 99.76% | 3637 0.14% 99.90% | 2109 0.08% 99.98% | 523 0.02% 100.00% | 9 0.00% 100.00% | 20 0.00% 100.00% | 17 0.00% 100.00% | 7 0.00% 100.00% +system.ruby.miss_latency_hist::total 2662257 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11119260 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 532503 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11651763 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 68488995 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 323914 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 68812909 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -618,13 +616,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 15 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12795046 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313851 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108897 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 57694694 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 492317 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58187011 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 16 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12794938 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313574 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108512 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 57691140 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 492266 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58183406 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -635,71 +633,71 @@ system.ruby.l1_cntrl1.prefetcher.partial_hits 0 system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2434372 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227205 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2661577 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2435460 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 226797 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2662257 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.029987 -system.ruby.network.routers0.msg_count.Control::0 855409 -system.ruby.network.routers0.msg_count.Request_Control::2 42371 -system.ruby.network.routers0.msg_count.Response_Data::1 883866 -system.ruby.network.routers0.msg_count.Response_Control::1 509923 -system.ruby.network.routers0.msg_count.Response_Control::2 507294 -system.ruby.network.routers0.msg_count.Writeback_Data::0 298509 -system.ruby.network.routers0.msg_count.Writeback_Data::1 176 -system.ruby.network.routers0.msg_count.Writeback_Control::0 170526 -system.ruby.network.routers0.msg_bytes.Control::0 6843272 -system.ruby.network.routers0.msg_bytes.Request_Control::2 338968 -system.ruby.network.routers0.msg_bytes.Response_Data::1 63638352 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4079384 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4058352 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21492648 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12672 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1364208 -system.ruby.network.routers1.percent_links_utilized 0.057152 -system.ruby.network.routers1.msg_count.Control::0 1806168 -system.ruby.network.routers1.msg_count.Request_Control::2 40332 -system.ruby.network.routers1.msg_count.Response_Data::1 1830141 -system.ruby.network.routers1.msg_count.Response_Control::1 1256659 -system.ruby.network.routers1.msg_count.Response_Control::2 1255808 -system.ruby.network.routers1.msg_count.Writeback_Data::0 276119 -system.ruby.network.routers1.msg_count.Writeback_Data::1 194 -system.ruby.network.routers1.msg_count.Writeback_Control::0 942229 -system.ruby.network.routers1.msg_bytes.Control::0 14449344 -system.ruby.network.routers1.msg_bytes.Request_Control::2 322656 -system.ruby.network.routers1.msg_bytes.Response_Data::1 131770152 -system.ruby.network.routers1.msg_bytes.Response_Control::1 10053272 -system.ruby.network.routers1.msg_bytes.Response_Control::2 10046464 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880568 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13968 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7537832 -system.ruby.network.routers2.percent_links_utilized 0.091505 -system.ruby.network.routers2.msg_count.Control::0 2839493 -system.ruby.network.routers2.msg_count.Request_Control::2 81198 -system.ruby.network.routers2.msg_count.Response_Data::1 2891200 -system.ruby.network.routers2.msg_count.Response_Control::1 1848800 -system.ruby.network.routers2.msg_count.Response_Control::2 1763102 -system.ruby.network.routers2.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers2.msg_count.Writeback_Data::1 370 -system.ruby.network.routers2.msg_count.Writeback_Control::0 1112755 -system.ruby.network.routers2.msg_bytes.Control::0 22715944 -system.ruby.network.routers2.msg_bytes.Request_Control::2 649584 -system.ruby.network.routers2.msg_bytes.Response_Data::1 208166400 -system.ruby.network.routers2.msg_bytes.Response_Control::1 14790400 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8902040 -system.ruby.network.routers3.percent_links_utilized 0.006812 -system.ruby.network.routers3.msg_count.Control::0 177916 -system.ruby.network.routers3.msg_count.Response_Data::1 276580 -system.ruby.network.routers3.msg_count.Response_Control::1 130228 +system.ruby.network.routers0.percent_links_utilized 0.030013 +system.ruby.network.routers0.msg_count.Control::0 856417 +system.ruby.network.routers0.msg_count.Request_Control::2 42660 +system.ruby.network.routers0.msg_count.Response_Data::1 884950 +system.ruby.network.routers0.msg_count.Response_Control::1 510141 +system.ruby.network.routers0.msg_count.Response_Control::2 507455 +system.ruby.network.routers0.msg_count.Writeback_Data::0 298492 +system.ruby.network.routers0.msg_count.Writeback_Data::1 178 +system.ruby.network.routers0.msg_count.Writeback_Control::0 170402 +system.ruby.network.routers0.msg_bytes.Control::0 6851336 +system.ruby.network.routers0.msg_bytes.Request_Control::2 341280 +system.ruby.network.routers0.msg_bytes.Response_Data::1 63716400 +system.ruby.network.routers0.msg_bytes.Response_Control::1 4081128 +system.ruby.network.routers0.msg_bytes.Response_Control::2 4059640 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21491424 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12816 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1363216 +system.ruby.network.routers1.percent_links_utilized 0.057139 +system.ruby.network.routers1.msg_count.Control::0 1805840 +system.ruby.network.routers1.msg_count.Request_Control::2 40537 +system.ruby.network.routers1.msg_count.Response_Data::1 1830038 +system.ruby.network.routers1.msg_count.Response_Control::1 1255303 +system.ruby.network.routers1.msg_count.Response_Control::2 1254313 +system.ruby.network.routers1.msg_count.Writeback_Data::0 276120 +system.ruby.network.routers1.msg_count.Writeback_Data::1 190 +system.ruby.network.routers1.msg_count.Writeback_Control::0 940436 +system.ruby.network.routers1.msg_bytes.Control::0 14446720 +system.ruby.network.routers1.msg_bytes.Request_Control::2 324296 +system.ruby.network.routers1.msg_bytes.Response_Data::1 131762736 +system.ruby.network.routers1.msg_bytes.Response_Control::1 10042424 +system.ruby.network.routers1.msg_bytes.Response_Control::2 10034504 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 19880640 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 13680 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7523488 +system.ruby.network.routers2.percent_links_utilized 0.091475 +system.ruby.network.routers2.msg_count.Control::0 2839469 +system.ruby.network.routers2.msg_count.Request_Control::2 81710 +system.ruby.network.routers2.msg_count.Response_Data::1 2890401 +system.ruby.network.routers2.msg_count.Response_Control::1 1846120 +system.ruby.network.routers2.msg_count.Response_Control::2 1761768 +system.ruby.network.routers2.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers2.msg_count.Writeback_Data::1 368 +system.ruby.network.routers2.msg_count.Writeback_Control::0 1110838 +system.ruby.network.routers2.msg_bytes.Control::0 22715752 +system.ruby.network.routers2.msg_bytes.Request_Control::2 653680 +system.ruby.network.routers2.msg_bytes.Response_Data::1 208108872 +system.ruby.network.routers2.msg_bytes.Response_Control::1 14768960 +system.ruby.network.routers2.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers2.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers3.percent_links_utilized 0.006783 +system.ruby.network.routers3.msg_count.Control::0 177212 +system.ruby.network.routers3.msg_count.Response_Data::1 275392 +system.ruby.network.routers3.msg_count.Response_Control::1 129266 system.ruby.network.routers3.msg_count.Writeback_Control::0 47545 system.ruby.network.routers3.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.msg_bytes.Control::0 1423328 -system.ruby.network.routers3.msg_bytes.Response_Data::1 19913760 -system.ruby.network.routers3.msg_bytes.Response_Control::1 1041824 +system.ruby.network.routers3.msg_bytes.Control::0 1417696 +system.ruby.network.routers3.msg_bytes.Response_Data::1 19828224 +system.ruby.network.routers3.msg_bytes.Response_Control::1 1034128 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.percent_links_utilized 0.000239 @@ -710,120 +708,120 @@ system.ruby.network.routers4.msg_bytes.Response_Data::1 58248 system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers5.percent_links_utilized 0 -system.ruby.network.routers6.percent_links_utilized 0.030950 -system.ruby.network.routers6.msg_count.Control::0 2839493 -system.ruby.network.routers6.msg_count.Request_Control::2 82703 -system.ruby.network.routers6.msg_count.Response_Data::1 2941298 -system.ruby.network.routers6.msg_count.Response_Control::1 1872805 -system.ruby.network.routers6.msg_count.Response_Control::2 1763102 -system.ruby.network.routers6.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers6.msg_count.Writeback_Data::1 370 -system.ruby.network.routers6.msg_count.Writeback_Control::0 1160300 +system.ruby.network.routers6.percent_links_utilized 0.030942 +system.ruby.network.routers6.msg_count.Control::0 2839469 +system.ruby.network.routers6.msg_count.Request_Control::2 83197 +system.ruby.network.routers6.msg_count.Response_Data::1 2940795 +system.ruby.network.routers6.msg_count.Response_Control::1 1870415 +system.ruby.network.routers6.msg_count.Response_Control::2 1761768 +system.ruby.network.routers6.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.msg_count.Writeback_Data::1 368 +system.ruby.network.routers6.msg_count.Writeback_Control::0 1158383 system.ruby.network.routers6.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.msg_bytes.Control::0 22715944 -system.ruby.network.routers6.msg_bytes.Request_Control::2 661624 -system.ruby.network.routers6.msg_bytes.Response_Data::1 211773456 -system.ruby.network.routers6.msg_bytes.Response_Control::1 14982440 -system.ruby.network.routers6.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers6.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers6.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers6.msg_bytes.Writeback_Control::0 9282400 +system.ruby.network.routers6.msg_bytes.Control::0 22715752 +system.ruby.network.routers6.msg_bytes.Request_Control::2 665576 +system.ruby.network.routers6.msg_bytes.Response_Data::1 211737240 +system.ruby.network.routers6.msg_bytes.Response_Control::1 14963320 +system.ruby.network.routers6.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers6.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers6.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers6.msg_bytes.Writeback_Control::0 9267064 system.ruby.network.routers6.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.msg_count.Control 8518479 -system.ruby.network.msg_count.Request_Control 246604 -system.ruby.network.msg_count.Response_Data 8823894 -system.ruby.network.msg_count.Response_Control 10907721 -system.ruby.network.msg_count.Writeback_Data 1724994 -system.ruby.network.msg_count.Writeback_Control 3621108 -system.ruby.network.msg_byte.Control 68147832 -system.ruby.network.msg_byte.Request_Control 1972832 -system.ruby.network.msg_byte.Response_Data 635320368 -system.ruby.network.msg_byte.Response_Control 87261768 -system.ruby.network.msg_byte.Writeback_Data 124199568 -system.ruby.network.msg_byte.Writeback_Control 28968864 -system.ruby.network.routers0.throttle0.link_utilization 0.038287 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42371 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 843260 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 494161 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 338968 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 60714720 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3953288 -system.ruby.network.routers0.throttle1.link_utilization 0.021686 -system.ruby.network.routers0.throttle1.msg_count.Control::0 855409 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40606 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 15762 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 507294 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 298509 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 176 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 170526 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 6843272 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2923632 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 126096 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4058352 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 21492648 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 12672 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1364208 -system.ruby.network.routers1.throttle0.link_utilization 0.082198 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 40332 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1796167 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 1239377 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 322656 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 129324024 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 9915016 -system.ruby.network.routers1.throttle1.link_utilization 0.032106 -system.ruby.network.routers1.throttle1.msg_count.Control::0 1806168 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 33974 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 17282 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1255808 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 276119 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 194 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 942229 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 14449344 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 2446128 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 138256 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 10046464 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 19880568 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 13968 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7537832 -system.ruby.network.routers2.throttle0.link_utilization 0.059676 -system.ruby.network.routers2.throttle0.msg_count.Control::0 2661577 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 203207 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 123979 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1763102 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 370 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 1112755 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21292616 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 14630904 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 991832 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8902040 -system.ruby.network.routers2.throttle1.link_utilization 0.123335 -system.ruby.network.routers2.throttle1.msg_count.Control::0 177916 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 81198 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2687993 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1724821 -system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1423328 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 649584 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 193535496 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13798568 -system.ruby.network.routers3.throttle0.link_utilization 0.005284 -system.ruby.network.routers3.throttle0.msg_count.Control::0 177916 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 97855 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 15288 +system.ruby.network.msg_count.Control 8518407 +system.ruby.network.msg_count.Request_Control 248104 +system.ruby.network.msg_count.Response_Data 8822385 +system.ruby.network.msg_count.Response_Control 10896549 +system.ruby.network.msg_count.Writeback_Data 1724940 +system.ruby.network.msg_count.Writeback_Control 3615357 +system.ruby.network.msg_byte.Control 68147256 +system.ruby.network.msg_byte.Request_Control 1984832 +system.ruby.network.msg_byte.Response_Data 635211720 +system.ruby.network.msg_byte.Response_Control 87172392 +system.ruby.network.msg_byte.Writeback_Data 124195680 +system.ruby.network.msg_byte.Writeback_Control 28922856 +system.ruby.network.routers0.throttle0.link_utilization 0.038328 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42660 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 844192 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 494162 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 341280 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 60781824 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3953296 +system.ruby.network.routers0.throttle1.link_utilization 0.021698 +system.ruby.network.routers0.throttle1.msg_count.Control::0 856417 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40758 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 15979 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 507455 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 298492 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 178 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 170402 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 6851336 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2934576 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 127832 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4059640 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 21491424 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 12816 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1363216 +system.ruby.network.routers1.throttle0.link_utilization 0.082169 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 40537 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1795610 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 1238038 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 324296 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 129283920 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 9904304 +system.ruby.network.routers1.throttle1.link_utilization 0.032108 +system.ruby.network.routers1.throttle1.msg_count.Control::0 1805840 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 34428 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 17265 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1254313 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 276120 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 190 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 940436 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 14446720 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 2478816 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 138120 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 10034504 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 19880640 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 13680 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7523488 +system.ruby.network.routers2.throttle0.link_utilization 0.059642 +system.ruby.network.routers2.throttle0.msg_count.Control::0 2662257 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 202813 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 123155 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1761768 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 368 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 1110838 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21298056 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 14602536 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 985240 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers2.throttle1.link_utilization 0.123308 +system.ruby.network.routers2.throttle1.msg_count.Control::0 177212 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 81710 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2687588 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1722965 +system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1417696 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 653680 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 193506336 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13783720 +system.ruby.network.routers3.throttle0.link_utilization 0.005259 +system.ruby.network.routers3.throttle0.msg_count.Control::0 177212 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 97371 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 15060 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47545 -system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1423328 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 7045560 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1417696 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 7010712 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 120480 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380360 -system.ruby.network.routers3.throttle1.link_utilization 0.008341 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 178725 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 114940 +system.ruby.network.routers3.throttle1.link_utilization 0.008307 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 178021 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 114206 system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12868200 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 919520 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12817512 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 913648 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle0.link_utilization 0.000255 system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 809 @@ -835,43 +833,43 @@ system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 475 system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.038287 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42371 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 843260 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 494161 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 338968 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 60714720 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3953288 -system.ruby.network.routers6.throttle1.link_utilization 0.082198 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40332 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1796167 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1239377 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 322656 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129324024 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9915016 -system.ruby.network.routers6.throttle2.link_utilization 0.059676 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2661577 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203207 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123979 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1763102 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574628 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 370 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1112755 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21292616 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14630904 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 991832 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14104816 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41373216 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26640 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8902040 -system.ruby.network.routers6.throttle3.link_utilization 0.005284 -system.ruby.network.routers6.throttle3.msg_count.Control::0 177916 -system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97855 -system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15288 +system.ruby.network.routers6.throttle0.link_utilization 0.038328 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42660 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 844192 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 494162 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 341280 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 60781824 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3953296 +system.ruby.network.routers6.throttle1.link_utilization 0.082169 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40537 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1795610 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1238038 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 324296 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129283920 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9904304 +system.ruby.network.routers6.throttle2.link_utilization 0.059642 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2662257 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 202813 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123155 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1761768 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574612 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 368 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110838 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21298056 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14602536 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 985240 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14094144 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41372064 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26496 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8886704 +system.ruby.network.routers6.throttle3.link_utilization 0.005259 +system.ruby.network.routers6.throttle3.msg_count.Control::0 177212 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97371 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15060 system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47545 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1423328 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7045560 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1417696 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7010712 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 120480 system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers6.throttle4.link_utilization 0.000255 system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 809 @@ -881,176 +879,176 @@ system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 3738 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6112062 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754100 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.339998 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5536581 90.58% 90.58% | 390 0.01% 90.59% | 574653 9.40% 99.99% | 162 0.00% 100.00% | 217 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6112062 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6109475 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.754420 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.340404 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5533989 90.58% 90.58% | 406 0.01% 90.59% | 574630 9.41% 99.99% | 158 0.00% 100.00% | 247 0.00% 100.00% | 11 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6109475 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4700521 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.045023 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.596216 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4673467 99.42% 99.42% | 451 0.01% 99.43% | 352 0.01% 99.44% | 567 0.01% 99.45% | 25509 0.54% 100.00% | 158 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 10 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4700521 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4698338 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.045583 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.599791 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4670953 99.42% 99.42% | 477 0.01% 99.43% | 336 0.01% 99.43% | 540 0.01% 99.45% | 25880 0.55% 100.00% | 139 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4698338 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 82703 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000121 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.015550 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 82698 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 82703 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 83197 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000192 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.019611 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 83189 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 83197 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15017729 -system.ruby.LD.latency_hist::mean 4.875603 -system.ruby.LD.latency_hist::gmean 3.591894 -system.ruby.LD.latency_hist::stdev 9.357158 -system.ruby.LD.latency_hist | 15001612 99.89% 99.89% | 13925 0.09% 99.99% | 816 0.01% 99.99% | 883 0.01% 100.00% | 364 0.00% 100.00% | 107 0.00% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.latency_hist::total 15017729 +system.ruby.LD.latency_hist::samples 15027912 +system.ruby.LD.latency_hist::mean 4.869020 +system.ruby.LD.latency_hist::gmean 3.591147 +system.ruby.LD.latency_hist::stdev 9.231737 +system.ruby.LD.latency_hist | 15011958 99.89% 99.89% | 13851 0.09% 99.99% | 851 0.01% 99.99% | 792 0.01% 100.00% | 329 0.00% 100.00% | 121 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 15027912 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13626729 +system.ruby.LD.hit_latency_hist::samples 13637263 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13626729 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13626729 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637263 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13637263 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1391000 -system.ruby.LD.miss_latency_hist::mean 23.249676 -system.ruby.LD.miss_latency_hist::gmean 20.961439 -system.ruby.LD.miss_latency_hist::stdev 23.942041 -system.ruby.LD.miss_latency_hist | 1374883 98.84% 98.84% | 13925 1.00% 99.84% | 816 0.06% 99.90% | 883 0.06% 99.96% | 364 0.03% 99.99% | 107 0.01% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1391000 -system.ruby.ST.latency_hist::bucket_size 256 -system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 9551572 -system.ruby.ST.latency_hist::mean 5.175450 -system.ruby.ST.latency_hist::gmean 3.300315 -system.ruby.ST.latency_hist::stdev 17.651145 -system.ruby.ST.latency_hist | 9545751 99.94% 99.94% | 3768 0.04% 99.98% | 2002 0.02% 100.00% | 25 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9551572 +system.ruby.LD.miss_latency_hist::samples 1390649 +system.ruby.LD.miss_latency_hist::mean 23.197386 +system.ruby.LD.miss_latency_hist::gmean 20.952196 +system.ruby.LD.miss_latency_hist::stdev 23.468925 +system.ruby.LD.miss_latency_hist | 1374695 98.85% 98.85% | 13851 1.00% 99.85% | 851 0.06% 99.91% | 792 0.06% 99.97% | 329 0.02% 99.99% | 121 0.01% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1390649 +system.ruby.ST.latency_hist::bucket_size 128 +system.ruby.ST.latency_hist::max_bucket 1279 +system.ruby.ST.latency_hist::samples 9558783 +system.ruby.ST.latency_hist::mean 5.170026 +system.ruby.ST.latency_hist::gmean 3.300098 +system.ruby.ST.latency_hist::stdev 17.579302 +system.ruby.ST.latency_hist | 9544781 99.85% 99.85% | 8164 0.09% 99.94% | 1330 0.01% 99.95% | 2504 0.03% 99.98% | 1628 0.02% 100.00% | 340 0.00% 100.00% | 7 0.00% 100.00% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist::total 9558783 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9200825 +system.ruby.ST.hit_latency_hist::samples 9207752 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9200825 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9200825 -system.ruby.ST.miss_latency_hist::bucket_size 256 -system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 350747 -system.ruby.ST.miss_latency_hist::mean 62.242032 -system.ruby.ST.miss_latency_hist::gmean 40.314149 -system.ruby.ST.miss_latency_hist::stdev 71.440751 -system.ruby.ST.miss_latency_hist | 344926 98.34% 98.34% | 3768 1.07% 99.41% | 2002 0.57% 99.99% | 25 0.01% 99.99% | 25 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 350747 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9207752 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9207752 +system.ruby.ST.miss_latency_hist::bucket_size 128 +system.ruby.ST.miss_latency_hist::max_bucket 1279 +system.ruby.ST.miss_latency_hist::samples 351031 +system.ruby.ST.miss_latency_hist::mean 62.091086 +system.ruby.ST.miss_latency_hist::gmean 40.236579 +system.ruby.ST.miss_latency_hist::stdev 71.074662 +system.ruby.ST.miss_latency_hist | 337029 96.01% 96.01% | 8164 2.33% 98.34% | 1330 0.38% 98.72% | 2504 0.71% 99.43% | 1628 0.46% 99.89% | 340 0.10% 99.99% | 7 0.00% 99.99% | 12 0.00% 100.00% | 11 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 351031 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 127093107 -system.ruby.IFETCH.latency_hist::mean 3.119052 -system.ruby.IFETCH.latency_hist::gmean 3.036517 -system.ruby.IFETCH.latency_hist::stdev 2.234317 -system.ruby.IFETCH.latency_hist | 127086452 99.99% 99.99% | 5646 0.00% 100.00% | 489 0.00% 100.00% | 322 0.00% 100.00% | 142 0.00% 100.00% | 52 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 127093107 +system.ruby.IFETCH.latency_hist::samples 126996315 +system.ruby.IFETCH.latency_hist::mean 3.119134 +system.ruby.IFETCH.latency_hist::gmean 3.036572 +system.ruby.IFETCH.latency_hist::stdev 2.233716 +system.ruby.IFETCH.latency_hist | 126989642 99.99% 99.99% | 5673 0.00% 100.00% | 484 0.00% 100.00% | 317 0.00% 100.00% | 137 0.00% 100.00% | 55 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126996315 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 126277646 +system.ruby.IFETCH.hit_latency_hist::samples 126180135 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126277646 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 126277646 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180135 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 126180135 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 815461 -system.ruby.IFETCH.miss_latency_hist::mean 21.554760 -system.ruby.IFETCH.miss_latency_hist::gmean 19.772157 -system.ruby.IFETCH.miss_latency_hist::stdev 20.880175 -system.ruby.IFETCH.miss_latency_hist | 808806 99.18% 99.18% | 5646 0.69% 99.88% | 489 0.06% 99.94% | 322 0.04% 99.98% | 142 0.02% 99.99% | 52 0.01% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 815461 +system.ruby.IFETCH.miss_latency_hist::samples 816180 +system.ruby.IFETCH.miss_latency_hist::mean 21.537108 +system.ruby.IFETCH.miss_latency_hist::gmean 19.766480 +system.ruby.IFETCH.miss_latency_hist::stdev 20.855244 +system.ruby.IFETCH.miss_latency_hist | 809507 99.18% 99.18% | 5673 0.70% 99.88% | 484 0.06% 99.94% | 317 0.04% 99.98% | 137 0.02% 99.99% | 55 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 816180 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 493320 -system.ruby.RMW_Read.latency_hist::mean 6.020587 -system.ruby.RMW_Read.latency_hist::gmean 3.953175 -system.ruby.RMW_Read.latency_hist::stdev 10.251324 -system.ruby.RMW_Read.latency_hist | 493147 99.96% 99.96% | 127 0.03% 99.99% | 17 0.00% 99.99% | 15 0.00% 100.00% | 9 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 493320 +system.ruby.RMW_Read.latency_hist::samples 494272 +system.ruby.RMW_Read.latency_hist::mean 6.020764 +system.ruby.RMW_Read.latency_hist::gmean 3.952362 +system.ruby.RMW_Read.latency_hist::stdev 10.313773 +system.ruby.RMW_Read.latency_hist | 494092 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 11 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494272 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 428060 +system.ruby.RMW_Read.hit_latency_hist::samples 428940 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428060 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 428060 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428940 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 65260 -system.ruby.RMW_Read.miss_latency_hist::mean 25.833527 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.149766 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.493474 -system.ruby.RMW_Read.miss_latency_hist | 65087 99.73% 99.73% | 127 0.19% 99.93% | 17 0.03% 99.96% | 15 0.02% 99.98% | 9 0.01% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65260 +system.ruby.RMW_Read.miss_latency_hist::samples 65332 +system.ruby.RMW_Read.miss_latency_hist::mean 25.853716 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.153784 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.748956 +system.ruby.RMW_Read.miss_latency_hist | 65152 99.72% 99.72% | 129 0.20% 99.92% | 18 0.03% 99.95% | 18 0.03% 99.98% | 11 0.02% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65332 system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.latency_hist::samples 339680 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.345204 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780937 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.076413 -system.ruby.Locked_RMW_Read.latency_hist | 339429 99.93% 99.93% | 234 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339680 +system.ruby.Locked_RMW_Read.latency_hist::samples 339654 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.351331 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780101 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.370233 +system.ruby.Locked_RMW_Read.latency_hist | 339398 99.92% 99.92% | 231 0.07% 99.99% | 12 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339654 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300571 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300589 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300571 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 300571 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300589 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 300589 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39109 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.369199 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.378025 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.121215 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38858 99.36% 99.36% | 234 0.60% 99.96% | 11 0.03% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 39109 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39065 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.443850 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.382210 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.468459 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38809 99.34% 99.34% | 231 0.59% 99.94% | 12 0.03% 99.97% | 6 0.02% 99.98% | 4 0.01% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 39065 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339680 +system.ruby.Locked_RMW_Write.latency_hist::samples 339654 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339680 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339680 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339680 -system.ruby.Directory_Controller.Fetch 177916 0.00% 0.00% -system.ruby.Directory_Controller.Data 97855 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178363 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 143156 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339654 +system.ruby.Directory_Controller.Fetch 177212 0.00% 0.00% +system.ruby.Directory_Controller.Data 97371 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 177674 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142679 0.00% 0.00% system.ruby.Directory_Controller.DMA_READ 809 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15288 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 177916 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 447 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45301 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 447 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45301 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 96058 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1435 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15288 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 177916 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 96058 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1435 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1435 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 15060 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 177212 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 462 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45308 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 462 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45308 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95596 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 347 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1428 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15060 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 177212 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95596 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 347 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 347 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1428 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1428 0.00% 0.00% system.ruby.DMA_Controller.ReadRequest | 809 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.ReadRequest::total 809 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% @@ -1067,169 +1065,169 @@ system.ruby.DMA_Controller.BUSY_RD.Data | 809 100.00% 100.00% | system.ruby.DMA_Controller.BUSY_RD.Data::total 809 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6268725 41.74% 41.74% | 8749004 58.26% 100.00% -system.ruby.L1Cache_Controller.Load::total 15017729 -system.ruby.L1Cache_Controller.Ifetch | 68906101 54.22% 54.22% | 58187012 45.78% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 127093113 -system.ruby.L1Cache_Controller.Store | 5364359 50.02% 50.02% | 5359893 49.98% 100.00% -system.ruby.L1Cache_Controller.Store::total 10724252 -system.ruby.L1Cache_Controller.Inv | 15938 47.70% 47.70% | 17476 52.30% 100.00% -system.ruby.L1Cache_Controller.Inv::total 33414 -system.ruby.L1Cache_Controller.L1_Replacement | 827888 31.76% 31.76% | 1778547 68.24% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2606435 -system.ruby.L1Cache_Controller.Fwd_GETX | 12260 51.09% 51.09% | 11738 48.91% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 23998 -system.ruby.L1Cache_Controller.Fwd_GETS | 14169 56.03% 56.03% | 11118 43.97% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25287 +system.ruby.L1Cache_Controller.Load | 6279317 41.78% 41.78% | 8748595 58.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 15027912 +system.ruby.L1Cache_Controller.Ifetch | 68812914 54.18% 54.18% | 58183407 45.82% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126996321 +system.ruby.L1Cache_Controller.Store | 5372446 50.06% 50.06% | 5359917 49.94% 100.00% +system.ruby.L1Cache_Controller.Store::total 10732363 +system.ruby.L1Cache_Controller.Inv | 16157 48.07% 48.07% | 17455 51.93% 100.00% +system.ruby.L1Cache_Controller.Inv::total 33612 +system.ruby.L1Cache_Controller.L1_Replacement | 828605 31.79% 31.79% | 1777971 68.21% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2606576 +system.ruby.L1Cache_Controller.Fwd_GETX | 12248 51.07% 51.07% | 11736 48.93% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23984 +system.ruby.L1Cache_Controller.Fwd_GETS | 14251 55.67% 55.67% | 11346 44.33% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 25597 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% -system.ruby.L1Cache_Controller.Data::total 1855 -system.ruby.L1Cache_Controller.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1282695 -system.ruby.L1Cache_Controller.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25291 -system.ruby.L1Cache_Controller.Data_all_Acks | 578454 43.51% 43.51% | 751132 56.49% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1329586 -system.ruby.L1Cache_Controller.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22150 -system.ruby.L1Cache_Controller.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 24005 -system.ruby.L1Cache_Controller.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1687383 -system.ruby.L1Cache_Controller.NP.Load | 280457 20.44% 20.44% | 1091772 79.56% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1372229 -system.ruby.L1Cache_Controller.NP.Ifetch | 323032 39.65% 39.65% | 491723 60.35% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 814755 -system.ruby.L1Cache_Controller.NP.Store | 225423 53.48% 53.48% | 196076 46.52% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 421499 -system.ruby.L1Cache_Controller.NP.Inv | 4849 53.95% 53.95% | 4139 46.05% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 8988 -system.ruby.L1Cache_Controller.I.Load | 8492 45.24% 45.24% | 10279 54.76% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18771 -system.ruby.L1Cache_Controller.I.Ifetch | 112 15.86% 15.86% | 594 84.14% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 706 -system.ruby.L1Cache_Controller.I.Store | 5744 50.09% 50.09% | 5723 49.91% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11467 -system.ruby.L1Cache_Controller.I.L1_Replacement | 9001 51.76% 51.76% | 8389 48.24% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17390 -system.ruby.L1Cache_Controller.S.Load | 552961 51.86% 51.86% | 513218 48.14% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1066179 -system.ruby.L1Cache_Controller.S.Ifetch | 68582952 54.31% 54.31% | 57694694 45.69% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 126277646 -system.ruby.L1Cache_Controller.S.Store | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22150 -system.ruby.L1Cache_Controller.S.Inv | 10866 45.32% 45.32% | 13108 54.68% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23974 -system.ruby.L1Cache_Controller.S.L1_Replacement | 349852 38.80% 38.80% | 551810 61.20% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 901662 -system.ruby.L1Cache_Controller.E.Load | 1151502 29.73% 29.73% | 2721068 70.27% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3872570 -system.ruby.L1Cache_Controller.E.Store | 80746 48.37% 48.37% | 86187 51.63% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166933 -system.ruby.L1Cache_Controller.E.Inv | 47 57.32% 57.32% | 35 42.68% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 82 -system.ruby.L1Cache_Controller.E.L1_Replacement | 170526 15.32% 15.32% | 942229 84.68% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1112755 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 332 72.81% 72.81% | 124 27.19% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 456 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 992 45.23% 45.23% | 1201 54.77% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2193 -system.ruby.L1Cache_Controller.M.Load | 4275313 49.21% 49.21% | 4412667 50.79% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8687980 -system.ruby.L1Cache_Controller.M.Store | 5040297 49.89% 49.89% | 5061906 50.11% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10102203 -system.ruby.L1Cache_Controller.M.Inv | 176 47.57% 47.57% | 194 52.43% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 370 -system.ruby.L1Cache_Controller.M.L1_Replacement | 298509 51.95% 51.95% | 276119 48.05% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 574628 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11928 50.67% 50.67% | 11614 49.33% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23542 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13177 57.06% 57.06% | 9917 42.94% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23094 +system.ruby.L1Cache_Controller.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% +system.ruby.L1Cache_Controller.Data::total 1840 +system.ruby.L1Cache_Controller.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 25601 +system.ruby.L1Cache_Controller.Data_all_Acks | 579316 43.50% 43.50% | 752306 56.50% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1331622 +system.ruby.L1Cache_Controller.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.Ack::total 22455 +system.ruby.L1Cache_Controller.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 24295 +system.ruby.L1Cache_Controller.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1685450 +system.ruby.L1Cache_Controller.NP.Load | 280382 20.44% 20.44% | 1091184 79.56% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1371566 +system.ruby.L1Cache_Controller.NP.Ifetch | 323814 39.71% 39.71% | 491732 60.29% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815546 +system.ruby.L1Cache_Controller.NP.Store | 225433 53.48% 53.48% | 196079 46.52% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 421512 +system.ruby.L1Cache_Controller.NP.Inv | 4849 54.09% 54.09% | 4115 45.91% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8964 +system.ruby.L1Cache_Controller.I.Load | 8724 45.72% 45.72% | 10359 54.28% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 19083 +system.ruby.L1Cache_Controller.I.Ifetch | 100 15.77% 15.77% | 534 84.23% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 634 +system.ruby.L1Cache_Controller.I.Store | 5739 50.07% 50.07% | 5722 49.93% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11461 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8993 51.78% 51.78% | 8375 48.22% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17368 +system.ruby.L1Cache_Controller.S.Load | 555624 51.88% 51.88% | 515377 48.12% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1071001 +system.ruby.L1Cache_Controller.S.Ifetch | 68488995 54.28% 54.28% | 57691140 45.72% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 126180135 +system.ruby.L1Cache_Controller.S.Store | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22455 +system.ruby.L1Cache_Controller.S.Inv | 11078 45.79% 45.79% | 13115 54.21% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 24193 +system.ruby.L1Cache_Controller.S.L1_Replacement | 350718 38.81% 38.81% | 553040 61.19% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 903758 +system.ruby.L1Cache_Controller.E.Load | 1152084 29.74% 29.74% | 2722150 70.26% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3874234 +system.ruby.L1Cache_Controller.E.Store | 80726 48.37% 48.37% | 86165 51.63% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166891 +system.ruby.L1Cache_Controller.E.Inv | 52 59.77% 59.77% | 35 40.23% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 87 +system.ruby.L1Cache_Controller.E.L1_Replacement | 170402 15.34% 15.34% | 940436 84.66% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110838 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 330 72.53% 72.53% | 125 27.47% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 455 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 996 45.17% 45.17% | 1209 54.83% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2205 +system.ruby.L1Cache_Controller.M.Load | 4282503 49.27% 49.27% | 4409525 50.73% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8692028 +system.ruby.L1Cache_Controller.M.Store | 5048323 49.93% 49.93% | 5061721 50.07% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10110044 +system.ruby.L1Cache_Controller.M.Inv | 178 48.37% 48.37% | 190 51.63% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 368 +system.ruby.L1Cache_Controller.M.L1_Replacement | 298492 51.95% 51.95% | 276120 48.05% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 574612 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11918 50.65% 50.65% | 11611 49.35% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23529 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13255 56.66% 56.66% | 10137 43.34% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23392 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1282695 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25291 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348115 38.75% 38.75% | 550360 61.25% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898475 -system.ruby.L1Cache_Controller.IM.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1855 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230339 53.43% 53.43% | 200772 46.57% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431111 -system.ruby.L1Cache_Controller.SM.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22150 -system.ruby.L1Cache_Controller.SM.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 24005 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252712 19.73% 19.73% | 1028027 80.27% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280739 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25601 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348962 38.75% 38.75% | 551527 61.25% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900489 +system.ruby.L1Cache_Controller.IM.Data | 818 44.46% 44.46% | 1022 55.54% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1840 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230354 53.43% 53.43% | 200779 46.57% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431133 +system.ruby.L1Cache_Controller.SM.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 22455 +system.ruby.L1Cache_Controller.SM.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 24295 system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1687383 -system.ruby.L2Cache_Controller.L1_GET_INSTR 815461 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1391156 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 432966 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22150 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1687383 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 95998 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 15348 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 177916 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 113143 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23468 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2193 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1505 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7534 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25291 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1737811 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 3594 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16427 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 34220 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127269 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799004 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 83018 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1958 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22150 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 257 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7192 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 468894 27.82% 27.82% | 1216556 72.18% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685450 +system.ruby.L2Cache_Controller.L1_GET_INSTR 816180 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1390821 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 432975 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 22455 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95536 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 15120 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 177212 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 112431 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23764 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2205 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1487 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7462 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 25601 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1736167 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 3550 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16316 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 33914 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 126982 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799834 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 84313 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1944 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22455 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 252 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7120 0.00% 0.00% system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1248475 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 279741 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 95619 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8056 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1564 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1246825 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 280063 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 95163 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7896 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1542 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25287 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 23998 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1687383 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 122 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 100 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 25597 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23984 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1685450 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 121 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 104 0.00% 0.00% system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 113143 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1564 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 310 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 42 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 112431 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1542 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 308 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.MEM_Inv 230 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 40 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1245 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7192 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 260 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 260 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 44 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1232 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 7120 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 255 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 255 0.00% 0.00% system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 34220 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 16427 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127269 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 115 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24108 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 41 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1713703 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23085 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2191 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 15 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 13 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25276 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 33914 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 16316 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 126982 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 122 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24399 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711768 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23385 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2205 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 11 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 11 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25590 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 81562c0f3..99542453a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133731 # Number of seconds simulated -sim_ticks 5133731116500 # Number of ticks simulated -final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.134211 # Number of seconds simulated +sim_ticks 5134211428000 # Number of ticks simulated +final_tick 5134211428000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 268887 # Simulator instruction rate (inst/s) -host_op_rate 534560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5655392824 # Simulator tick rate (ticks/s) -host_mem_usage 1025452 # Number of bytes of host memory used -host_seconds 907.76 # Real time elapsed on the host -sim_insts 244084329 # Number of instructions simulated -sim_ops 485251122 # Number of ops (including micro ops) simulated +host_inst_rate 263536 # Simulator instruction rate (inst/s) +host_op_rate 523907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5540037627 # Simulator tick rate (ticks/s) +host_mem_usage 1021876 # Number of bytes of host memory used +host_seconds 926.75 # Real time elapsed on the host +sim_insts 244230745 # Number of instructions simulated +sim_ops 485529516 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 445760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5319424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 180800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1995776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 334336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3134080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5140544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1859072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 422208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3469952 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11441152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 445760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 180800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 334336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 960896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9198080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9198080 # Number of bytes written to this memory +system.physmem.bytes_read::total 11466176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 422208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 9230336 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 83116 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2825 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 31184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 48970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 29048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 39 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 54218 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178768 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143720 # Number of write requests responded to by this memory +system.physmem.num_reads::total 179159 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144224 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 86830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1036171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 388757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 65125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 610488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2228623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 86830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35218 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 65125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187173 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1791695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1791695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1791695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 76650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1001233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 362095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 82234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 675849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2233289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 76650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 82234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1797810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1797810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1797810 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 86830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1036171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 388757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 65125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 610488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4020318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 88682 # Number of read requests accepted -system.physmem.writeReqs 112966 # Number of write requests accepted -system.physmem.readBursts 88682 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 112966 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5672000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3648 # Total number of bytes read from write queue -system.physmem.bytesWritten 6262656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5675648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7229824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 57 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 15112 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1053 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5542 # Per bank write bursts -system.physmem.perBankRdBursts::1 5155 # Per bank write bursts -system.physmem.perBankRdBursts::2 5253 # Per bank write bursts -system.physmem.perBankRdBursts::3 5290 # Per bank write bursts -system.physmem.perBankRdBursts::4 5356 # Per bank write bursts -system.physmem.perBankRdBursts::5 4920 # Per bank write bursts -system.physmem.perBankRdBursts::6 5387 # Per bank write bursts -system.physmem.perBankRdBursts::7 5003 # Per bank write bursts -system.physmem.perBankRdBursts::8 5335 # Per bank write bursts -system.physmem.perBankRdBursts::9 5304 # Per bank write bursts -system.physmem.perBankRdBursts::10 5486 # Per bank write bursts -system.physmem.perBankRdBursts::11 5354 # Per bank write bursts -system.physmem.perBankRdBursts::12 5802 # Per bank write bursts -system.physmem.perBankRdBursts::13 6837 # Per bank write bursts -system.physmem.perBankRdBursts::14 6164 # Per bank write bursts -system.physmem.perBankRdBursts::15 6437 # Per bank write bursts -system.physmem.perBankWrBursts::0 6158 # Per bank write bursts -system.physmem.perBankWrBursts::1 6179 # Per bank write bursts -system.physmem.perBankWrBursts::2 6254 # Per bank write bursts -system.physmem.perBankWrBursts::3 6080 # Per bank write bursts -system.physmem.perBankWrBursts::4 5432 # Per bank write bursts -system.physmem.perBankWrBursts::5 5660 # Per bank write bursts -system.physmem.perBankWrBursts::6 6180 # Per bank write bursts -system.physmem.perBankWrBursts::7 5898 # Per bank write bursts -system.physmem.perBankWrBursts::8 5226 # Per bank write bursts -system.physmem.perBankWrBursts::9 5788 # Per bank write bursts -system.physmem.perBankWrBursts::10 6663 # Per bank write bursts -system.physmem.perBankWrBursts::11 6618 # Per bank write bursts -system.physmem.perBankWrBursts::12 6477 # Per bank write bursts -system.physmem.perBankWrBursts::13 6666 # Per bank write bursts -system.physmem.perBankWrBursts::14 5929 # Per bank write bursts -system.physmem.perBankWrBursts::15 6646 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 76650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1001233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 362095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 82234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 675849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4031099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92684 # Number of read requests accepted +system.physmem.writeReqs 79104 # Number of write requests accepted +system.physmem.readBursts 92684 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 79104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5924224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 5060672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5931776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5062656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 20933 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6439 # Per bank write bursts +system.physmem.perBankRdBursts::1 5501 # Per bank write bursts +system.physmem.perBankRdBursts::2 5319 # Per bank write bursts +system.physmem.perBankRdBursts::3 5591 # Per bank write bursts +system.physmem.perBankRdBursts::4 5862 # Per bank write bursts +system.physmem.perBankRdBursts::5 5383 # Per bank write bursts +system.physmem.perBankRdBursts::6 5425 # Per bank write bursts +system.physmem.perBankRdBursts::7 4840 # Per bank write bursts +system.physmem.perBankRdBursts::8 6025 # Per bank write bursts +system.physmem.perBankRdBursts::9 5959 # Per bank write bursts +system.physmem.perBankRdBursts::10 5660 # Per bank write bursts +system.physmem.perBankRdBursts::11 5754 # Per bank write bursts +system.physmem.perBankRdBursts::12 5715 # Per bank write bursts +system.physmem.perBankRdBursts::13 6523 # Per bank write bursts +system.physmem.perBankRdBursts::14 5966 # Per bank write bursts +system.physmem.perBankRdBursts::15 6604 # Per bank write bursts +system.physmem.perBankWrBursts::0 5842 # Per bank write bursts +system.physmem.perBankWrBursts::1 5111 # Per bank write bursts +system.physmem.perBankWrBursts::2 4865 # Per bank write bursts +system.physmem.perBankWrBursts::3 5025 # Per bank write bursts +system.physmem.perBankWrBursts::4 5489 # Per bank write bursts +system.physmem.perBankWrBursts::5 4924 # Per bank write bursts +system.physmem.perBankWrBursts::6 4816 # Per bank write bursts +system.physmem.perBankWrBursts::7 4154 # Per bank write bursts +system.physmem.perBankWrBursts::8 4431 # Per bank write bursts +system.physmem.perBankWrBursts::9 4666 # Per bank write bursts +system.physmem.perBankWrBursts::10 4446 # Per bank write bursts +system.physmem.perBankWrBursts::11 4728 # Per bank write bursts +system.physmem.perBankWrBursts::12 4725 # Per bank write bursts +system.physmem.perBankWrBursts::13 5504 # Per bank write bursts +system.physmem.perBankWrBursts::14 4686 # Per bank write bursts +system.physmem.perBankWrBursts::15 5661 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 5132592336000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 5133211221000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 88682 # Read request sizes (log2) +system.physmem.readPktSize::6 92684 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 112966 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 81919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.writePktSize::6 79104 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 86281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -165,986 +165,984 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40590 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.012121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.528709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.654231 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15917 39.21% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9832 24.22% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4000 9.85% 73.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2295 5.65% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1624 4.00% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1126 2.77% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 717 1.77% 87.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 617 1.52% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4462 10.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40590 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.420983 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 192.521538 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3781 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3784 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.859937 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.216089 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 44.163335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 82 2.17% 2.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 3425 90.51% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 68 1.80% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 12 0.32% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 7 0.18% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 15 0.40% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 10 0.26% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 22 0.58% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 22 0.58% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.45% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 6 0.16% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.58% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 36 0.95% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.18% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.08% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 1 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 1 0.03% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.13% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 4 0.11% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.13% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3784 # Writes before turning the bus around for reads -system.physmem.totQLat 1019929900 # Total ticks spent queuing -system.physmem.totMemAccLat 2681648650 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 443125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11508.38 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.949081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.456020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 296.352111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16538 40.64% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10119 24.87% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4173 10.26% 75.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2507 6.16% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1551 3.81% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1073 2.64% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 750 1.84% 90.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 656 1.61% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3325 8.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40692 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.462136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 184.101810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4117 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.192476 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.355155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.050068 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 67 1.63% 1.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.15% 1.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.10% 1.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3537 85.85% 87.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 61 1.48% 89.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 102 2.48% 91.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 51 1.24% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.92% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 95 2.31% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 16 0.39% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.15% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.22% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.05% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 98 2.38% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.05% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.12% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.15% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4120 # Writes before turning the bus around for reads +system.physmem.totQLat 1055441928 # Total ticks spent queuing +system.physmem.totMemAccLat 2791054428 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 462830000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11402.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30258.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30152.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.85 # Average write queue length when enqueuing -system.physmem.readRowHits 70792 # Number of row buffer hits during reads -system.physmem.writeRowHits 75088 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.73 # Row buffer hit rate for writes -system.physmem.avgGap 25453227.09 # Average gap between requests -system.physmem.pageHitRate 78.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 147351960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 80169375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 326866800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 309938400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94629197520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2236697889750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2582234091885 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.903813 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3683333970938 # Time in different power states -system.physmem_0.memoryStateTime::REF 127833680000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.29 # Average write queue length when enqueuing +system.physmem.readRowHits 74063 # Number of row buffer hits during reads +system.physmem.writeRowHits 56883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes +system.physmem.avgGap 29881081.46 # Average gap between requests +system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 149294880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 81184125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 345992400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 260664480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94809930840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2241062736000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2586727052805 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.763806 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3682666821734 # Time in different power states +system.physmem_0.memoryStateTime::REF 127820680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17533181312 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17822753766 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 159410160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86781750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 364408200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 323974080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95188577850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2235010334250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2581176164370 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.974824 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3682508953468 # Time in different power states -system.physmem_1.memoryStateTime::REF 127833680000 # Time in different power states +system.physmem_1.actEnergy 158336640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 86183625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 376006800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 251728560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95265143955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2233496235000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2579650884660 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.996985 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3682005807728 # Time in different power states +system.physmem_1.memoryStateTime::REF 127820680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18355082532 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18463901522 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 819384850 # number of cpu cycles simulated +system.cpu0.numCycles 814812843 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70809878 # Number of instructions committed -system.cpu0.committedOps 144569383 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 132504639 # Number of integer alu accesses +system.cpu0.committedInsts 70855773 # Number of instructions committed +system.cpu0.committedOps 144639705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 132581707 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 914830 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14060186 # number of instructions that are conditional controls -system.cpu0.num_int_insts 132504639 # number of integer instructions +system.cpu0.num_func_calls 911803 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14069363 # number of instructions that are conditional controls +system.cpu0.num_int_insts 132581707 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 242769596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113987635 # number of times the integer registers were written +system.cpu0.num_int_register_reads 242934374 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114063964 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82531896 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55153606 # number of times the CC registers were written -system.cpu0.num_mem_refs 13358556 # number of memory refs -system.cpu0.num_load_insts 9930193 # Number of load instructions -system.cpu0.num_store_insts 3428363 # Number of store instructions -system.cpu0.num_idle_cycles 778171794.138464 # Number of idle cycles -system.cpu0.num_busy_cycles 41213055.861536 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050298 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949702 # Percentage of idle cycles -system.cpu0.Branches 15315720 # Number of branches fetched -system.cpu0.op_class::No_OpClass 88912 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 131019698 90.63% 90.69% # Class of executed instruction -system.cpu0.op_class::IntMult 57722 0.04% 90.73% # Class of executed instruction -system.cpu0.op_class::IntDiv 46561 0.03% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.76% # Class of executed instruction -system.cpu0.op_class::MemRead 9928558 6.87% 97.63% # Class of executed instruction -system.cpu0.op_class::MemWrite 3428363 2.37% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82574901 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55200628 # number of times the CC registers were written +system.cpu0.num_mem_refs 13389972 # number of memory refs +system.cpu0.num_load_insts 9966183 # Number of load instructions +system.cpu0.num_store_insts 3423789 # Number of store instructions +system.cpu0.num_idle_cycles 774643417.179050 # Number of idle cycles +system.cpu0.num_busy_cycles 40169425.820950 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049299 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950701 # Percentage of idle cycles +system.cpu0.Branches 15322983 # Number of branches fetched +system.cpu0.op_class::No_OpClass 87668 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 131058913 90.61% 90.67% # Class of executed instruction +system.cpu0.op_class::IntMult 57724 0.04% 90.71% # Class of executed instruction +system.cpu0.op_class::IntDiv 47555 0.03% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.74% # Class of executed instruction +system.cpu0.op_class::MemRead 9964546 6.89% 97.63% # Class of executed instruction +system.cpu0.op_class::MemWrite 3423789 2.37% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 144569814 # Class of executed instruction +system.cpu0.op_class::total 144640195 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1636339 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999246 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19643358 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1636851 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.000700 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1639692 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999446 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19677629 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1640204 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.997062 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 232.510577 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.541861 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.946808 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.454122 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499105 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.046771 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 231.527826 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.098734 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 24.372886 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.452203 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500193 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.047603 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88441515 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88441515 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4745925 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2412981 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4334563 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11493469 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3299103 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1688891 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3099986 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8087980 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19676 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9874 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30514 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 60064 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8045028 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4101872 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7434549 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19581449 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8064704 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4111746 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7465063 # number of overall hits -system.cpu0.dcache.overall_hits::total 19641513 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 345343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 160729 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 822143 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1328215 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 125592 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 64251 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 135437 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325280 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145872 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63796 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196481 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406149 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 470935 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 224980 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 957580 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1653495 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 616807 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 288776 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1154061 # number of overall misses -system.cpu0.dcache.overall_misses::total 2059644 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2230470250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12318599402 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14549069652 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2662717793 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4381161307 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7043879100 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4893188043 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 16699760709 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21592948752 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4893188043 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 16699760709 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21592948752 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5091268 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2573710 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5156706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12821684 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3424695 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1753142 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3235423 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8413260 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165548 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73670 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226995 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466213 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8515963 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4326852 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8392129 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21234944 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8681511 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4400522 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8619124 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21701157 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067830 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.062450 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159432 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.103591 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036672 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036649 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041861 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038663 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.881146 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865970 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.865574 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871166 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055300 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.051996 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.077867 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071048 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065623 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133895 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094909 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13877.211020 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14983.524037 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10953.851336 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41442.433472 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32348.333963 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21654.817696 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21749.435697 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17439.546261 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13058.974325 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16944.580031 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14470.431553 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10483.825725 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 172709 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 88605943 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88605943 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4782117 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2413671 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4330956 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11526744 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3296356 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1699008 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3093469 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8088833 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19899 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9911 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30439 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 60249 # number of SoftPFReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8078473 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4112679 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7424425 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19615577 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8098372 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4122590 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7454864 # number of overall hits +system.cpu0.dcache.overall_hits::total 19675826 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 346307 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 159141 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 827752 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1333200 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 123952 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 63357 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 139093 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 326402 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 144703 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63873 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 197428 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406004 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 470259 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 222498 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 966845 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1659602 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 614962 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 286371 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1164273 # number of overall misses +system.cpu0.dcache.overall_misses::total 2065606 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2189850500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12100176000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14290026500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2530090000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4783086364 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7313176364 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4719940500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 16883262364 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 21603202864 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4719940500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 16883262364 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 21603202864 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5128424 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2572812 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 5158708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12859944 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3420308 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1762365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3232562 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8415235 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 164602 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73784 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 227867 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 466253 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8548732 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4335177 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8391270 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21275179 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8713334 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4408961 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8619137 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21741432 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067527 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.061855 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.160457 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.103671 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036240 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035950 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043029 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038787 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.879108 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865675 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.866418 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.870780 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055009 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.051324 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115220 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.078006 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070577 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064952 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135080 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.095008 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13760.441998 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14618.117504 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10718.591734 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39933.866818 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34387.685678 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 22405.427553 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21213.406413 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17462.222346 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13017.098596 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16481.908084 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14501.119895 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10458.530264 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 191338 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19385 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22795 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.909414 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.393858 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1546428 # number of writebacks -system.cpu0.dcache.writebacks::total 1546428 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 54 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 384012 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 384066 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1567 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32068 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 33635 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1621 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 416080 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 417701 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1621 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 416080 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 417701 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 160675 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 438131 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 598806 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62684 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 103369 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 166053 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63795 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 193085 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 256880 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 223359 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 541500 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 764859 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2470174689 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3635352900 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6105527589 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 932249000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770809752 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3703058752 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4458692939 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9348693664 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13807386603 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5390941939 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12119503416 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17510445355 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30496812500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33031149000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63527961500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600115500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 761942500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1362058000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31096928000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33793091500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64890019500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.062429 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084963 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046703 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035755 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031949 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019737 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865956 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850613 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.550993 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.051622 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.064525 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.036019 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065255 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085227 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.047082 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.027696 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13040.256827 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12862.027124 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39406.781459 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35168.695644 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36768.547325 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14613.198527 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14350.207173 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14415.519900 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19962.002601 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17264.438899 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18052.198644 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163421.889569 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 160883.484080 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162092.138802 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174047.418794 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196782.670455 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186073.497268 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 163614.652061 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 161547.981911 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 162531.827575 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1548927 # number of writebacks +system.cpu0.dcache.writebacks::total 1548927 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 51 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 386553 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 386604 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1542 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32157 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 33699 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1593 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 418710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 420303 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1593 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 418710 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 420303 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159090 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 441199 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 600289 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 61815 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 106936 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 168751 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63873 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 194014 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 257887 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 220905 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 548135 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 769040 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 284778 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 742149 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1026927 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 185834 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 205183 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 391017 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3059 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4433 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7492 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 188893 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209616 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 398509 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2030358500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5964591000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7994949500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2384524000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4092527864 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6477051864 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 931095000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2819292000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3750387000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4414882500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10057118864 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14472001364 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5345977500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12876410864 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 18222388364 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30572400500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33247121500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63819522000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 547435500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 878869500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1426305000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31119836000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34125991000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65245827000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061835 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085525 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046679 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035075 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020053 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865675 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851435 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.553105 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050956 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065322 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.036147 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.064591 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086105 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.047234 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.326356 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13519.049227 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13318.500755 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38575.167840 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38270.814917 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38382.302114 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14577.286177 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14531.384333 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14542.753221 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19985.434915 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18347.886678 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18818.268704 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18772.438531 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17350.169392 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17744.580057 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164514.569454 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162036.433330 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163214.187618 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178958.973521 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198256.147079 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190377.068873 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164748.487239 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162802.414892 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163724.851885 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 871419 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 127964014 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 871931 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 146.759335 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 150504235000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.667168 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 143.237667 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 106.336510 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509116 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.279761 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.207688 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996565 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 881776 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.250144 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 127955824 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 882288 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 145.027275 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149037485500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.904392 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 141.200601 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 108.145151 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509579 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.275782 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.211221 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996582 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 129734477 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 129734477 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 86118928 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38597787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3247299 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 127964014 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 86118928 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38597787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3247299 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 127964014 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 86118928 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38597787 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3247299 # number of overall hits -system.cpu0.icache.overall_hits::total 127964014 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 294029 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 171033 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 433450 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 898512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 294029 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 171033 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 433450 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 898512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 294029 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 171033 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 433450 # number of overall misses -system.cpu0.icache.overall_misses::total 898512 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424026997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5943573307 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8367600304 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2424026997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5943573307 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8367600304 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2424026997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5943573307 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8367600304 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 86412957 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38768820 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3680749 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 128862526 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 86412957 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38768820 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3680749 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 128862526 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 86412957 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38768820 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3680749 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 128862526 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003403 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004412 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117761 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006973 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003403 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004412 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117761 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006973 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003403 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004412 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117761 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006973 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14172.861360 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.246642 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.730719 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9312.730719 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9312.730719 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7161 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 313 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.878594 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 129749175 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 129749175 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 86200122 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38494727 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3260975 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 127955824 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86200122 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38494727 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3260975 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 127955824 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86200122 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38494727 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3260975 # number of overall hits +system.cpu0.icache.overall_hits::total 127955824 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 293889 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 163550 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 453609 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 911048 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 293889 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 163550 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 453609 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 911048 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 293889 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 163550 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 453609 # number of overall misses +system.cpu0.icache.overall_misses::total 911048 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2290465000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6298842980 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8589307980 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2290465000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 6298842980 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8589307980 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2290465000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 6298842980 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8589307980 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 86494011 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38658277 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3714584 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 128866872 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 86494011 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38658277 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3714584 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 128866872 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 86494011 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38658277 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3714584 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 128866872 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003398 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004231 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122116 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.007070 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003398 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004231 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122116 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.007070 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003398 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004231 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122116 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.007070 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14004.677469 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13886.062622 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9427.942304 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14004.677469 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13886.062622 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9427.942304 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14004.677469 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13886.062622 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9427.942304 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6492 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 22 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 290 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.386207 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 22 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 26561 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 26561 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 26561 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 26561 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 26561 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 26561 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 171033 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 406889 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 577922 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 171033 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 406889 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 577922 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 171033 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 406889 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 577922 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2166425503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5084799831 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7251225334 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2166425503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5084799831 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7251225334 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2166425503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5084799831 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7251225334 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004485 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004485 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004485 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12547.065753 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 28745 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 28745 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 28745 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 28745 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 28745 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 28745 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163550 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 424864 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 588414 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 163550 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 424864 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 588414 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 163550 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 424864 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 588414 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2126915000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5601122480 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7728037480 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2126915000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5601122480 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7728037480 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2126915000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5601122480 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7728037480 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004566 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004566 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004231 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114377 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004566 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13133.673706 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13133.673706 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13004.677469 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13183.330383 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13133.673706 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604016269 # number of cpu cycles simulated +system.cpu1.numCycles 2606017483 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35221864 # Number of instructions committed -system.cpu1.committedOps 68477973 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63543554 # Number of integer alu accesses +system.cpu1.committedInsts 35137560 # Number of instructions committed +system.cpu1.committedOps 68325691 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63404843 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 474559 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6488284 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63543554 # number of integer instructions +system.cpu1.num_func_calls 475454 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6463819 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63404843 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 117503426 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54764358 # number of times the integer registers were written +system.cpu1.num_int_register_reads 117292769 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54636862 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35994299 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26824776 # number of times the CC registers were written -system.cpu1.num_mem_refs 4585615 # number of memory refs -system.cpu1.num_load_insts 2831531 # Number of load instructions -system.cpu1.num_store_insts 1754084 # Number of store instructions -system.cpu1.num_idle_cycles 2478252415.347472 # Number of idle cycles -system.cpu1.num_busy_cycles 125763853.652528 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048296 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951704 # Percentage of idle cycles -system.cpu1.Branches 7131846 # Number of branches fetched -system.cpu1.op_class::No_OpClass 33642 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 63809884 93.18% 93.23% # Class of executed instruction -system.cpu1.op_class::IntMult 28068 0.04% 93.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 22761 0.03% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.31% # Class of executed instruction -system.cpu1.op_class::MemRead 2829816 4.13% 97.44% # Class of executed instruction -system.cpu1.op_class::MemWrite 1754084 2.56% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 35859650 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26723526 # number of times the CC registers were written +system.cpu1.num_mem_refs 4592942 # number of memory refs +system.cpu1.num_load_insts 2829969 # Number of load instructions +system.cpu1.num_store_insts 1762973 # Number of store instructions +system.cpu1.num_idle_cycles 2483716878.762911 # Number of idle cycles +system.cpu1.num_busy_cycles 122300604.237089 # Number of busy cycles +system.cpu1.not_idle_fraction 0.046930 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.953070 # Percentage of idle cycles +system.cpu1.Branches 7109683 # Number of branches fetched +system.cpu1.op_class::No_OpClass 33619 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 63651336 93.16% 93.21% # Class of executed instruction +system.cpu1.op_class::IntMult 27621 0.04% 93.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 22176 0.03% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.28% # Class of executed instruction +system.cpu1.op_class::MemRead 2828254 4.14% 97.42% # Class of executed instruction +system.cpu1.op_class::MemWrite 1762973 2.58% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68478255 # Class of executed instruction +system.cpu1.op_class::total 68325979 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29642945 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29642945 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 342109 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26793966 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26087449 # Number of BTB hits +system.cpu2.branchPred.lookups 29728292 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29728292 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 354491 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26875418 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26145153 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.363149 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 617263 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 68240 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154815215 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.282777 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 627673 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 71339 # Number of incorrect RAS predictions. +system.cpu2.numCycles 156747191 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 11226493 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 146138571 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29642945 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26704712 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 142088964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 715876 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 100355 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5095 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9800 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 59006 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1044 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3680756 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 177933 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3589 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 153848066 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.868751 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.040918 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 11575217 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 146531331 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29728292 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26772826 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143455759 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 740896 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 117693 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 8882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 9184 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 67495 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 36 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 614 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3714591 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 185121 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 4402 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 155604677 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.852545 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.032784 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97905187 63.64% 63.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 902052 0.59% 64.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23780045 15.46% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 607949 0.40% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 861058 0.56% 80.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 871308 0.57% 81.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 586027 0.38% 81.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 774714 0.50% 82.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27559726 17.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 99528214 63.96% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 894883 0.58% 64.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23827863 15.31% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 616054 0.40% 80.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 865023 0.56% 80.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 874152 0.56% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 593045 0.38% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 766815 0.49% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27638628 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 153848066 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.191473 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.943955 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10308577 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93114688 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23867360 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5032797 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 358589 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 284536277 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 358589 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12446525 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76456474 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4505534 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26483485 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12431465 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 283232358 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 203213 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5874103 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 62488 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4343022 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 338256341 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 618855518 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 379959971 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 144 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325490778 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12765563 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 164991 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 166448 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24511654 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6973831 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3905800 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 411343 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 337090 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 281177337 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 428187 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278961410 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 111637 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 9401758 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 14188384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 65116 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 153848066 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.813227 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.402216 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 155604677 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189658 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.934826 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10653655 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 94438460 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23846115 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5077401 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 371099 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 285226302 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 371099 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12813669 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77065666 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4747202 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 26484696 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12904465 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 283889044 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 204785 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5893747 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 54074 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4792782 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 339006774 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 620283621 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 380802622 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 280 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325933868 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13072904 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 167839 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 169378 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24708176 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6969767 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3922969 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 416514 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 341941 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 281777756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 433047 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 279489336 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 112446 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 9646678 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 14520235 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68066 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155604677 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.796150 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.396491 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90533816 58.85% 58.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5362080 3.49% 62.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3874219 2.52% 64.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3850508 2.50% 67.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22615321 14.70% 82.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2805299 1.82% 83.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24069627 15.65% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 503741 0.33% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 233455 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 92126087 59.21% 59.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5408193 3.48% 62.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3871909 2.49% 65.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3896687 2.50% 67.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22645736 14.55% 82.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2817206 1.81% 84.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24121295 15.50% 99.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 489992 0.31% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 227572 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 153848066 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155604677 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1762451 85.95% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.95% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 222010 10.83% 96.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 66103 3.22% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1782744 86.25% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 2 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 219490 10.62% 96.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 64665 3.13% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 83756 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 267874850 96.03% 96.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 60171 0.02% 96.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 55540 0.02% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 52 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.10% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 7279557 2.61% 98.71% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3607484 1.29% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 84223 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 268409283 96.04% 96.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 60791 0.02% 96.09% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 54867 0.02% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 128 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7262488 2.60% 98.71% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3617556 1.29% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278961410 # Type of FU issued -system.cpu2.iq.rate 1.801899 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2050564 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713932890 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 291011736 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 277302749 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 156 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280928122 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 96 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 764231 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 279489336 # Type of FU issued +system.cpu2.iq.rate 1.783058 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2066901 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007395 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 716762296 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 291861984 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 277802443 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 399 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 402 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 161 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 281471819 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 195 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 741069 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1280710 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6256 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5226 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 665708 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1314442 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6549 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5531 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 685228 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 750625 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 30616 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 750208 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28435 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 358589 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70562607 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 2840752 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281605524 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 45396 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6973831 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3905800 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 251212 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 165628 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2346507 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5226 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 195667 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 202777 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 398444 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 278332986 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 7126227 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 571848 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 371099 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70840326 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 3147966 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 282210803 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 45613 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6969767 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3922969 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 254598 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 166407 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2652713 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5531 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 201920 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 210112 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 412032 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 278837771 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 7102995 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 592219 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10641796 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28281444 # Number of branches executed -system.cpu2.iew.exec_stores 3515569 # Number of stores executed -system.cpu2.iew.exec_rate 1.797840 # Inst execution rate -system.cpu2.iew.wb_sent 278129863 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 277302825 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 216123267 # num instructions producing a value -system.cpu2.iew.wb_consumers 354504830 # num instructions consuming a value +system.cpu2.iew.exec_refs 10623704 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28332312 # Number of branches executed +system.cpu2.iew.exec_stores 3520709 # Number of stores executed +system.cpu2.iew.exec_rate 1.778901 # Inst execution rate +system.cpu2.iew.wb_sent 278631802 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 277802604 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 216492114 # num instructions producing a value +system.cpu2.iew.wb_consumers 355079818 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.791186 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609648 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.772297 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609700 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9397385 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 363071 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 345314 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152442881 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.785612 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.660258 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9642578 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364981 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 357554 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 154160156 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.768058 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.650606 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94319401 61.87% 61.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4425348 2.90% 64.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1302226 0.85% 65.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24740165 16.23% 81.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 979797 0.64% 82.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 733746 0.48% 82.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 423992 0.28% 83.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23324047 15.30% 98.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2194159 1.44% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95860610 62.18% 62.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4461430 2.89% 65.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1337416 0.87% 65.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24820120 16.10% 82.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1009976 0.66% 82.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 732580 0.48% 83.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 443548 0.29% 83.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23352402 15.15% 98.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2142074 1.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152442881 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 138052587 # Number of instructions committed -system.cpu2.commit.committedOps 272203766 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 154160156 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 138237412 # Number of instructions committed +system.cpu2.commit.committedOps 272564120 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8933213 # Number of memory references committed -system.cpu2.commit.loads 5693121 # Number of loads committed -system.cpu2.commit.membars 162094 # Number of memory barriers committed -system.cpu2.commit.branches 27859693 # Number of branches committed +system.cpu2.commit.refs 8893065 # Number of memory references committed +system.cpu2.commit.loads 5655324 # Number of loads committed +system.cpu2.commit.membars 162767 # Number of memory barriers committed +system.cpu2.commit.branches 27901240 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248852946 # Number of committed integer instructions. -system.cpu2.commit.function_calls 461863 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 49962 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 263110099 96.66% 96.68% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 57933 0.02% 96.70% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 52599 0.02% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.72% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5693065 2.09% 98.81% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3240092 1.19% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 249166189 # Number of committed integer instructions. +system.cpu2.commit.function_calls 462772 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 50638 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 263510022 96.68% 96.70% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 58397 0.02% 96.72% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 52041 0.02% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.74% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5655265 2.07% 98.81% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3237741 1.19% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 272203766 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2194159 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 431819572 # The number of ROB reads -system.cpu2.rob.rob_writes 564614589 # The number of ROB writes -system.cpu2.timesIdled 120593 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 967149 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4904349916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 138052587 # Number of Instructions Simulated -system.cpu2.committedOps 272203766 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.121422 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.121422 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.891725 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.891725 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 371027158 # number of integer regfile reads -system.cpu2.int_regfile_writes 222252306 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72988 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 141449053 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108603776 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90794642 # number of misc regfile reads -system.cpu2.misc_regfile_writes 144161 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3553347 # Transaction distribution -system.iobus.trans_dist::ReadResp 3553347 # Transaction distribution -system.iobus.trans_dist::WriteReq 57679 # Transaction distribution -system.iobus.trans_dist::WriteResp 10959 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1698 # Transaction distribution -system.iobus.trans_dist::MessageResp 1698 # Transaction distribution +system.cpu2.commit.op_class_0::total 272564120 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2142074 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 434194585 # The number of ROB reads +system.cpu2.rob.rob_writes 565865422 # The number of ROB writes +system.cpu2.timesIdled 127222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1142514 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4899644826 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 138237412 # Number of Instructions Simulated +system.cpu2.committedOps 272564120 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.133898 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.133898 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.881913 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.881913 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 371610814 # number of integer regfile reads +system.cpu2.int_regfile_writes 222643670 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73073 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 141701796 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108796323 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90941344 # number of misc regfile reads +system.cpu2.misc_regfile_writes 144983 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3552121 # Transaction distribution +system.iobus.trans_dist::ReadResp 3552121 # Transaction distribution +system.iobus.trans_dist::WriteReq 57703 # Transaction distribution +system.iobus.trans_dist::WriteResp 57703 # Transaction distribution +system.iobus.trans_dist::MessageReq 1657 # Transaction distribution +system.iobus.trans_dist::MessageResp 1657 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) @@ -1153,22 +1151,22 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082616 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080216 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27854 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7126806 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3396 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3396 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7225448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7222962 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) @@ -1177,425 +1175,437 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541308 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13927 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3569512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6604072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2741680 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6628 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6628 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6602825 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2786496 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 6074000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5677000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 141309000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 140109000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 285000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 441000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10492000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11327000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 155889253 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 104116682 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 301765000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 300127000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31644993 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 23084000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1151000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1172000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47568 # number of replacements -system.iocache.tags.tagsinuse 0.079964 # Cycle average of tags in use +system.iocache.tags.replacements 47567 # number of replacements +system.iocache.tags.tagsinuse 0.081431 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47583 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000587823009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079964 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004998 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000591236509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081431 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005089 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005089 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428607 # Number of tag accesses -system.iocache.tags.data_accesses 428607 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 903 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses -system.iocache.demand_misses::total 903 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses -system.iocache.overall_misses::total 903 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128377230 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128377230 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 5164742030 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5164742030 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 128377230 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 128377230 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 128377230 # number of overall miss cycles -system.iocache.overall_miss_latency::total 128377230 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428598 # Number of tag accesses +system.iocache.tags.data_accesses 428598 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 902 # number of ReadReq misses +system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses +system.iocache.demand_misses::pc.south_bridge.ide 902 # number of demand (read+write) misses +system.iocache.demand_misses::total 902 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 902 # number of overall misses +system.iocache.overall_misses::total 902 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 121586746 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 121586746 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2354972936 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2354972936 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 121586746 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 121586746 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 121586746 # number of overall miss cycles +system.iocache.overall_miss_latency::total 121586746 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 902 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 902 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 902 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142167.475083 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 110546.704409 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 110546.704409 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 142167.475083 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 142167.475083 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 17612 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 134796.835920 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 50406.098801 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 50406.098801 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134796.835920 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134796.835920 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134796.835920 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2632 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.691489 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 801 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28264 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 28264 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 801 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 801 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86423212 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 3695010034 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3695010034 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 86423212 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 86423212 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.887043 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.604966 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.604966 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.887043 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.887043 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 107894.147316 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130732.027809 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130732.027809 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 746 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 19960 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 19960 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 746 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 746 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 746 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 84286746 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1356972936 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1356972936 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 84286746 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 84286746 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 84286746 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.827051 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.427226 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.427226 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.827051 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827051 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.827051 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112984.914209 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67984.616032 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67984.616032 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 112984.914209 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 112984.914209 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 112984.914209 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 105369 # number of replacements -system.l2c.tags.tagsinuse 64830.626845 # Cycle average of tags in use -system.l2c.tags.total_refs 3705679 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169446 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.869380 # Average number of references to valid blocks. +system.l2c.tags.replacements 105904 # number of replacements +system.l2c.tags.tagsinuse 64832.216142 # Cycle average of tags in use +system.l2c.tags.total_refs 4698304 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 170185 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.607039 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50858.096780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1601.427587 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5289.246768 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 232.896636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1549.888722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.632040 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1227.720144 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4063.582728 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.776033 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50894.263020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125303 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1602.122983 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5170.967993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 244.936624 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1566.576743 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.469260 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1245.636306 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4101.114491 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.776585 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.024436 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.080708 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003554 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000116 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.018734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.062005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989237 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64077 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4057 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8155 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51563 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977737 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33969935 # Number of tag accesses -system.l2c.tags.data_accesses 33969935 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 287050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 476755 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 13141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7558 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 168208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 219838 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 66288 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 401625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 617193 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2301274 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.024446 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.078903 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003737 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023904 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.019007 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.062578 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989261 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64281 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 679 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3076 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7407 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53037 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.980850 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41908906 # Number of tag accesses +system.l2c.tags.data_accesses 41908906 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 18995 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12983 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7660 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 68713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 15994 # number of ReadReq hits +system.l2c.ReadReq_hits::total 134678 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1546428 # number of Writeback hits -system.l2c.Writeback_hits::total 1546428 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 105 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 96 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 248 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55987 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 35553 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67356 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 158896 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 287050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 532742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 13141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7558 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 168208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 255391 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 66288 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 401625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 684549 # number of demand (read+write) hits -system.l2c.demand_hits::total 2460172 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19552 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10771 # number of overall hits -system.l2c.overall_hits::cpu0.inst 287050 # number of overall hits -system.l2c.overall_hits::cpu0.data 532742 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 13141 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7558 # number of overall hits -system.l2c.overall_hits::cpu1.inst 168208 # number of overall hits -system.l2c.overall_hits::cpu1.data 255391 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 66288 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13297 # number of overall hits -system.l2c.overall_hits::cpu2.inst 401625 # number of overall hits -system.l2c.overall_hits::cpu2.data 684549 # number of overall hits -system.l2c.overall_hits::total 2460172 # number of overall hits +system.l2c.Writeback_hits::writebacks 1548927 # number of Writeback hits +system.l2c.Writeback_hits::total 1548927 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 114 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 55 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 87 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 256 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58015 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36167 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 65709 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159891 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 287726 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 161212 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 418246 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 867184 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 475648 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 219061 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 621112 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 1315821 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 18995 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10335 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 287726 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 533663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12983 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7660 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 161212 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 255228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 68713 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 15994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 418246 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 686821 # number of demand (read+write) hits +system.l2c.demand_hits::total 2477576 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 18995 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10335 # number of overall hits +system.l2c.overall_hits::cpu0.inst 287726 # number of overall hits +system.l2c.overall_hits::cpu0.data 533663 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12983 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7660 # number of overall hits +system.l2c.overall_hits::cpu1.inst 161212 # number of overall hits +system.l2c.overall_hits::cpu1.data 255228 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 68713 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 15994 # number of overall hits +system.l2c.overall_hits::cpu2.inst 418246 # number of overall hits +system.l2c.overall_hits::cpu2.data 686821 # number of overall hits +system.l2c.overall_hits::total 2477576 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6966 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 14460 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 35 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5226 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 13983 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48133 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 556 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 254 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 614 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1424 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68944 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 26842 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 35344 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131130 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 39 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::total 45 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 613 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 245 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 572 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1430 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 65210 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 25360 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 40614 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131184 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 6150 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 2338 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 6597 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15085 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 15362 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 3902 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 14056 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 33320 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6966 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 83404 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2825 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 31474 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 35 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5226 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 49327 # number of demand (read+write) misses -system.l2c.demand_misses::total 179263 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 80572 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2338 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 29262 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 39 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 6597 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 54670 # number of demand (read+write) misses +system.l2c.demand_misses::total 179634 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6966 # number of overall misses -system.l2c.overall_misses::cpu0.data 83404 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2825 # number of overall misses -system.l2c.overall_misses::cpu1.data 31474 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 35 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5226 # number of overall misses -system.l2c.overall_misses::cpu2.data 49327 # number of overall misses -system.l2c.overall_misses::total 179263 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 229197000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 387947750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3073999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 450638500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1224001500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2294941249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5739854 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 7551262 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 13291116 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2024405687 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2802525365 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4826931052 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 229197000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2412353437 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 3073999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 450638500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 4026526865 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7121872301 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 229197000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2412353437 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 3073999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 450638500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 4026526865 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7121872301 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 19552 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10774 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 294016 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 491215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 13142 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7558 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 171033 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 224470 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 66323 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 13297 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 406851 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 631176 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2349407 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 6150 # number of overall misses +system.l2c.overall_misses::cpu0.data 80572 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2338 # number of overall misses +system.l2c.overall_misses::cpu1.data 29262 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 39 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 6597 # number of overall misses +system.l2c.overall_misses::cpu2.data 54670 # number of overall misses +system.l2c.overall_misses::total 179634 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3644000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 97000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 3741000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5007000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 7177500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 12184500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1902681000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 3220187500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5122868500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 188281500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 560185000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 748466500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 326831000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 1213452000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1540283000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 188281500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2229512000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 3644000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 97000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 560185000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 4433639500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7415359000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 188281500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2229512000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 3644000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 97000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 560185000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 4433639500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7415359000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 18995 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 10338 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 12983 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7660 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 68752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 15995 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 134723 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1546428 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1546428 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 661 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 301 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 710 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1672 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 124931 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 62395 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 102700 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 290026 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 19552 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10776 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 294016 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 616146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 13142 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7558 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 171033 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 286865 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 66323 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 13297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 406851 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 733876 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2639435 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 19552 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10776 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 294016 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 616146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 13142 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7558 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 171033 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 286865 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 66323 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 13297 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 406851 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 733876 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2639435 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000464 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.023693 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.029437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016517 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020635 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.012845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.022154 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020487 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.841150 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.843854 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.864789 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.851675 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.551857 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.430195 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.344148 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.452132 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000464 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.023693 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.135364 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016517 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.109717 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.012845 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.067214 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.067917 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000464 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.023693 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.135364 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000076 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016517 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.109717 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000528 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.012845 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.067214 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.067917 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81131.681416 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83753.832038 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.099502 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 87534.971036 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 47679.165001 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 22597.850394 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12298.472313 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 9333.648876 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75419.331160 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79292.818159 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 36810.272645 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81131.681416 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76645.912086 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 86230.099502 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 81629.267237 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 39728.623871 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81131.681416 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76645.912086 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87828.542857 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 86230.099502 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 81629.267237 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 39728.623871 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1548927 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1548927 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 727 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 300 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 659 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1686 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 123225 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 61527 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 106323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 291075 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 293876 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 163550 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 424843 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 882269 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 491010 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 222963 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 635168 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1349141 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 18995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 10340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 293876 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 614235 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 12983 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7660 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 163550 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 284490 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 68752 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 15995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 424843 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 741491 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2657210 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 18995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 10340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 293876 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 614235 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 12983 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7660 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 163550 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 284490 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 68752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 15995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 424843 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 741491 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2657210 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000484 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000567 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000063 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.843191 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.816667 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.867982 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.848161 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.529195 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.412177 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.381987 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.450688 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.020927 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.014295 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.015528 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.017098 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.031287 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.017501 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.022130 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.024697 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000484 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020927 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.131175 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014295 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.102858 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000567 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000063 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015528 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.073730 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.067602 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000484 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.020927 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.131175 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014295 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.102858 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000567 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000063 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015528 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.073730 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.067602 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 93435.897436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 97000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 83133.333333 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20436.734694 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12548.076923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 8520.629371 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75026.853312 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79287.622495 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 39051.016130 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80531.009410 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84915.112930 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 49616.605900 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83759.866735 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86329.823563 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 46226.980792 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80531.009410 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76191.374479 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 93435.897436 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 97000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 84915.112930 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 81098.216572 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 41280.375653 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80531.009410 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76191.374479 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 93435.897436 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 97000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 84915.112930 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 81098.216572 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 41280.375653 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1604,206 +1614,218 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 97053 # number of writebacks -system.l2c.writebacks::total 97053 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2825 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4632 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 35 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 5224 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 13983 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 26700 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 254 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 614 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 868 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 26842 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 35344 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 62186 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2825 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 31474 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 35 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5224 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 49327 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 88886 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2825 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 31474 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 35 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5224 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 385025750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1049073500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1960621999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5213239 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10949612 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 16162851 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1688636313 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2360590135 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4049226448 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 193782500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2018673563 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 385025750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 3409663635 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6009848447 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 193782500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2018673563 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 385025750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 3409663635 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6009848447 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27827045500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30156785500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 57983831000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 554838500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 711575000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1266413500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28381884000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30868360500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59250244500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020635 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022154 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.011365 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.843854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.864789 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.519139 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.430195 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344148 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.214415 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.033676 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.033676 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71251.565199 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 75024.923121 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 73431.535543 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20524.562992 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17833.244300 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18620.796083 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62910.226995 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66788.992050 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65114.759721 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149115.529917 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 146883.437809 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147946.242266 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160916.038283 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 183774.535124 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173007.308743 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 149329.608233 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 147566.296018 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 148405.727060 # average overall mshr uncacheable latency +system.l2c.writebacks::writebacks 97557 # number of writebacks +system.l2c.writebacks::total 97557 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 39 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 40 # number of ReadReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 51 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 51 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 245 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 572 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 817 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 25360 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 40614 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 65974 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2338 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 6597 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 8935 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 3902 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 14056 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 17958 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2338 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 29262 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 39 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 6597 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 54670 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 92907 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2338 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 29262 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 39 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 6597 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 54670 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 92907 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 185834 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 205183 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 391017 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3059 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4433 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 7492 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 188893 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 209616 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 398509 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3254000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 87000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 3341000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5679500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 11921500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 17601000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1649081000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2814047500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4463128500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 164901500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 494215000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 659116500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 287811000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1073015000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1360826000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 164901500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1936892000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3254000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 87000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 494215000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3887062500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6486412000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 164901500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1936892000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3254000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 87000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 494215000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3887062500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6486412000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28249472000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30682332500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58931804500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 512257000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 827881000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1340138000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28761729000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31510213500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60271942500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.816667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.867982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.484579 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412177 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.381987 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.226656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010127 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.017501 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.022130 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.013311 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.102858 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.073730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.102858 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000567 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000063 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.073730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83525 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23181.632653 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20841.783217 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21543.451652 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65026.853312 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69287.622495 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67649.809016 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73767.935087 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73759.866735 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76338.574274 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75778.260385 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66191.374479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71100.466435 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69816.181773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70531.009410 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66191.374479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 83435.897436 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 87000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74915.112930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71100.466435 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69816.181773 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152014.550620 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149536.426020 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150714.174831 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167458.973521 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186754.116851 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178875.867592 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152264.663063 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150323.512995 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 151243.616832 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5117226 # Transaction distribution -system.membus.trans_dist::ReadResp 5117226 # Transaction distribution -system.membus.trans_dist::WriteReq 13905 # Transaction distribution -system.membus.trans_dist::WriteResp 13905 # Transaction distribution -system.membus.trans_dist::Writeback 143720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1707 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1707 # Transaction distribution -system.membus.trans_dist::ReadExReq 130847 # Transaction distribution -system.membus.trans_dist::ReadExResp 130847 # Transaction distribution -system.membus.trans_dist::MessageReq 1698 # Transaction distribution -system.membus.trans_dist::MessageResp 1698 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037388 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10622155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141555 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141555 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10767106 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074773 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17637504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27281789 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6011648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 820 # Total snoops (count) -system.membus.snoop_fanout::samples 5455844 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000311 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017639 # Request fanout histogram +system.membus.trans_dist::ReadReq 5067078 # Transaction distribution +system.membus.trans_dist::ReadResp 5116429 # Transaction distribution +system.membus.trans_dist::WriteReq 13886 # Transaction distribution +system.membus.trans_dist::WriteResp 13886 # Transaction distribution +system.membus.trans_dist::Writeback 144224 # Transaction distribution +system.membus.trans_dist::CleanEvict 8915 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1691 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1691 # Transaction distribution +system.membus.trans_dist::ReadExReq 130923 # Transaction distribution +system.membus.trans_dist::ReadExResp 130923 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 49352 # Transaction distribution +system.membus.trans_dist::MessageReq 1657 # Transaction distribution +system.membus.trans_dist::MessageResp 1657 # Transaction distribution +system.membus.trans_dist::BadAddressError 1 # Transaction distribution +system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3314 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 467564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10629494 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10774941 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6075045 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17691840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27335322 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3025024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30366974 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 812 # Total snoops (count) +system.membus.snoop_fanout::samples 5464824 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017410 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5454146 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1698 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5463167 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1657 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5455844 # Request fanout histogram -system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5464824 # Request fanout histogram +system.membus.reqLayer0.occupancy 233042000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 304115000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2302000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2344000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 670380805 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 525464887 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1151000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1172000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1321113701 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1340471277 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 32422007 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 38659394 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1817,50 +1839,54 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7449528 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7448995 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13907 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13907 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1546428 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 28278 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1672 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 1151 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 225048 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17030802 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55802432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213393597 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 74263 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9350095 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.022573 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.148538 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5232649 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7464311 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1628034 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 977588 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291075 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291075 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 882303 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1349887 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 1172 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 19960 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2645849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15085510 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 77708 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 228805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18037872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56466048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213762586 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 290440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 837080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 271356154 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 159100 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10426288 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.028740 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.167075 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9139035 97.74% 97.74% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 211060 2.26% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10126637 97.13% 97.13% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 299651 2.87% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9350095 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 10426288 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2853173500 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 868906655 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 883247245 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1944011740 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1934319786 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26208491 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 28757491 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 98848126 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 101435667 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |