diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
| commit | b1a58933e07d7af0eb5f43942f8ad9bc93f28039 (patch) | |
| tree | 21f36b849ba0aed06ec18ed45aef46feeacd7532 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 630068be6f7b6dc5c612867c764c37e41fd90a4a (diff) | |
| download | gem5-b1a58933e07d7af0eb5f43942f8ad9bc93f28039.tar.xz | |
stats: update stats for icache change not allowing dirty data
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
7 files changed, 983 insertions, 1052 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 1fa068d9c..2ecc483cf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -1261,7 +1261,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1281,7 +1281,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index e7dca044c..22a267134 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 08:05:39 -gem5 started Jul 22 2012 08:05:57 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jul 26 2012 21:30:36 +gem5 started Jul 27 2012 00:44:18 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5172902281500 because m5_exit instruction encountered +Exiting @ tick 5172910256500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 4fa4cc520..d3e4451ad 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.172902 # Number of seconds simulated -sim_ticks 5172902281500 # Number of ticks simulated -final_tick 5172902281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.172910 # Number of seconds simulated +sim_ticks 5172910256500 # Number of ticks simulated +final_tick 5172910256500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117061 # Simulator instruction rate (inst/s) -host_op_rate 230687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1419746087 # Simulator tick rate (ticks/s) -host_mem_usage 420308 # Number of bytes of host memory used -host_seconds 3643.54 # Real time elapsed on the host -sim_insts 426515724 # Number of instructions simulated -sim_ops 840516219 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2496512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1067840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10426304 # Number of bytes read from this memory -system.physmem.bytes_read::total 13994560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1067840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1067840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9194240 # Number of bytes written to this memory -system.physmem.bytes_written::total 9194240 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 39008 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 162911 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218665 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143660 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143660 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 206430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2015562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2705359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 206430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 206430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1777385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1777385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1777385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 206430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2015562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4482745 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 107419 # number of replacements -system.l2c.tagsinuse 64844.084797 # Cycle average of tags in use -system.l2c.total_refs 3992672 # Total number of references to valid blocks. -system.l2c.sampled_refs 171622 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.264337 # Average number of references to valid blocks. +host_inst_rate 136129 # Simulator instruction rate (inst/s) +host_op_rate 268264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1651021148 # Simulator tick rate (ticks/s) +host_mem_usage 373420 # Number of bytes of host memory used +host_seconds 3133.16 # Real time elapsed on the host +sim_insts 426513995 # Number of instructions simulated +sim_ops 840512563 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1067584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10442240 # Number of bytes read from this memory +system.physmem.bytes_read::total 13977280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1067584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1067584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9176384 # Number of bytes written to this memory +system.physmem.bytes_written::total 9176384 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16681 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 163160 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218395 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143381 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 206380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2018639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2702015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 206380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 206380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1773931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1773931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1773931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 206380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2018639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4475945 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 106892 # number of replacements +system.l2c.tagsinuse 64846.239814 # Cycle average of tags in use +system.l2c.total_refs 3994467 # Total number of references to valid blocks. +system.l2c.sampled_refs 171328 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.314735 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50135.967843 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 12.897301 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.156788 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3372.666022 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11322.396844 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.765014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051463 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172766 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989442 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 110667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8396 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1054432 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1345104 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2518599 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1613189 # number of Writeback hits -system.l2c.Writeback_hits::total 1613189 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 163997 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 163997 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 110667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8396 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1054432 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1509101 # number of demand (read+write) hits -system.l2c.demand_hits::total 2682596 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 110667 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8396 # number of overall hits -system.l2c.overall_hits::cpu.inst 1054432 # number of overall hits -system.l2c.overall_hits::cpu.data 1509101 # number of overall hits -system.l2c.overall_hits::total 2682596 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16686 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35012 # number of ReadReq misses -system.l2c.ReadReq_misses::total 51759 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1516 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1516 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 128839 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128839 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16686 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 163851 # number of demand (read+write) misses -system.l2c.demand_misses::total 180598 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 55 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses -system.l2c.overall_misses::cpu.inst 16686 # number of overall misses -system.l2c.overall_misses::cpu.data 163851 # number of overall misses -system.l2c.overall_misses::total 180598 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2907000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 885914499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1865182494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2754315993 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 39171500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39171500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6715513999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6715513999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2907000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 885914499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8580696493 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9469829992 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2907000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 885914499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8580696493 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9469829992 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 110722 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 8402 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1071118 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1380116 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2570358 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1613189 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1613189 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1853 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1853 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292836 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292836 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 110722 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 8402 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1071118 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1672952 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2863194 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 110722 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 8402 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1071118 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1672952 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2863194 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000497 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.015578 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.025369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020137 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.818133 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818133 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.439970 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.439970 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.015578 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.097941 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063076 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.015578 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.097941 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063076 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52854.545455 # average ReadReq miss latency +system.l2c.occ_blocks::writebacks 50145.406461 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 11.508776 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.169764 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3382.865025 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11306.289787 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.765158 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000176 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.051618 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172520 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989475 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 113294 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 9300 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1056563 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1345318 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2524475 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1607595 # number of Writeback hits +system.l2c.Writeback_hits::total 1607595 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 334 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 163366 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 163366 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 113294 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 9300 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1056563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1508684 # number of demand (read+write) hits +system.l2c.demand_hits::total 2687841 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 113294 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 9300 # number of overall hits +system.l2c.overall_hits::cpu.inst 1056563 # number of overall hits +system.l2c.overall_hits::cpu.data 1508684 # number of overall hits +system.l2c.overall_hits::total 2687841 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 16683 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 35188 # number of ReadReq misses +system.l2c.ReadReq_misses::total 51924 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2935 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 128896 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128896 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 16683 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 164084 # number of demand (read+write) misses +system.l2c.demand_misses::total 180820 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 46 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu.inst 16683 # number of overall misses +system.l2c.overall_misses::cpu.data 164084 # number of overall misses +system.l2c.overall_misses::total 180820 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2412500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 885747500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1875717995 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2764241995 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 38348000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 38348000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6718316497 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6718316497 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2412500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 885747500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8594034492 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9482558492 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2412500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 885747500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8594034492 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9482558492 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 113340 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 9307 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1073246 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1380506 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2576399 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1607595 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1607595 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3269 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3269 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 292262 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292262 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 113340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 9307 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1073246 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1672768 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2868661 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 113340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 9307 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1073246 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1672768 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2868661 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000406 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000752 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.015544 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.025489 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020154 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.897828 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.897828 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.441029 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.441029 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000406 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000752 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.015544 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.098091 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063033 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000406 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000752 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.015544 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.098091 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063033 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52445.652174 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53093.281733 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 53272.663487 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 53214.242798 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25838.720317 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 25838.720317 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.301167 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52123.301167 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53092.819037 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 53305.615409 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 53236.306814 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13065.758092 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13065.758092 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52121.993677 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52121.993677 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52445.652174 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52435.962702 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53092.819037 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52375.822701 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52441.978166 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52445.652174 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52435.962702 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53092.819037 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52375.822701 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52441.978166 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,99 +189,99 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96993 # number of writebacks -system.l2c.writebacks::total 96993 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 96714 # number of writebacks +system.l2c.writebacks::total 96714 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 16685 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 35011 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 51757 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 1516 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1516 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 128839 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128839 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 16685 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 163850 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 180596 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 16685 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 163850 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 180596 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2241000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682427500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1437356500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2122265000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 61068000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 61068000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5163609501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5163609501 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2241000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 682427500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6600966001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7285874501 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2241000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 682427500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6600966001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7285874501 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192209064 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 59192209064 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211526000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1211526000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 60403735064 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60403735064 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818133 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818133 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.439970 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.439970 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063075 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063075 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average ReadReq mshr miss latency +system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 16681 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 35187 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 51921 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2935 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 128896 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 128896 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 16681 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 164083 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 180817 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 16681 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 164083 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 180817 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 1851000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682272500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1445683499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2130086999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117833500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117833500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5165552500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5165552500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 1851000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 682272500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6611235999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7295639499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 1851000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 682272500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6611235999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7295639499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192780564 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59192780564 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1212414000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1212414000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 60405194564 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60405194564 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025488 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020153 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.897828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.897828 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.441029 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.441029 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.098091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000752 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015543 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.098091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40901.174990 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41085.727655 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41025.538780 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40147.700170 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40147.700170 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40075.351446 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.351446 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47565 # number of replacements -system.iocache.tagsinuse 0.200108 # Cycle average of tags in use +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.199376 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47581 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5000599162000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.200108 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012507 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012507 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 900 # number of ReadReq misses -system.iocache.ReadReq_misses::total 900 # number of ReadReq misses +system.iocache.warmup_cycle 5000598404000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.199376 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012461 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012461 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47620 # number of demand (read+write) misses -system.iocache.demand_misses::total 47620 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47620 # number of overall misses -system.iocache.overall_misses::total 47620 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135466932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 135466932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6926961160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6926961160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7062428092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7062428092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7062428092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7062428092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 900 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 900 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135906932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135906932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6908833160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6908833160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7044740092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7044740092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7044740092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7044740092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47620 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47620 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47620 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47620 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150518.813333 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 148265.435788 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 148308.023772 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 148308.023772 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150339.526549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150339.526549 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147877.422089 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 147877.422089 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 147924.157820 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 147924.157820 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -348,22 +348,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 900 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 900 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47620 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47620 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47620 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47620 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88635000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88635000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4497207944 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4497207944 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4585842944 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4585842944 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88867000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88867000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4479079912 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4479079912 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4567946912 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4567946912 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98304.203540 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98304.203540 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95870.717295 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 95870.717295 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,107 +393,107 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 472946175 # number of cpu cycles simulated +system.cpu.numCycles 473223088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90027772 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90027772 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1176455 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84282590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81704922 # Number of BTB hits +system.cpu.BPredUnit.lookups 90016360 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90016360 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1178248 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84343978 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81707122 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31264026 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 446943348 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90027772 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81704922 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169792009 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5327046 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 167003 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 104616235 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 45804 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9365381 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 539972 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5058 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 310035010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.836765 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31356562 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 446929489 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90016360 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81707122 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169790434 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5330018 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 171751 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 104797996 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37968 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 45006 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 453 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9363044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 536807 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5287 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 310312997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.834177 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376352 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140677603 45.37% 45.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1773611 0.57% 45.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72784877 23.48% 69.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 988899 0.32% 69.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1639325 0.53% 70.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3670845 1.18% 71.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1138945 0.37% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1446155 0.47% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85914750 27.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140957479 45.42% 45.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1776597 0.57% 46.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72781994 23.45% 69.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 982988 0.32% 69.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1642902 0.53% 70.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3674853 1.18% 71.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1139478 0.37% 71.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1444103 0.47% 72.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85912603 27.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 310035010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.190355 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.945019 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36438516 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100672732 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164105371 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4706760 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4111631 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876235114 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4111631 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40855551 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 44279722 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10981847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 163785428 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46020831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872430616 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10252 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35253394 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3952381 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31994944 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1394146617 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2488353855 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2488353319 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347546781 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46599829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 470336 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 478135 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48126988 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18909339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10455877 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1294020 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1017517 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865756561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1721302 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864328719 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 124616 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26046990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53600910 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205527 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 310035010 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.787842 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.396151 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 310312997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.190220 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.944437 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36508708 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100881020 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164105770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4704672 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4112827 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876214899 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4112827 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40925858 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 44314017 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11153757 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 163784094 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46022444 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872421528 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10519 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 35242822 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3962452 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 32001317 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1394162179 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2488413918 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2488413062 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 856 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1347546247 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46615925 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 471039 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478955 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48145791 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18923985 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10455746 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1291287 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1021115 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865765672 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1722965 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864313181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123185 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26037339 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53671952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207307 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 310312997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.785295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.396376 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 102334281 33.01% 33.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23751530 7.66% 40.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 19011662 6.13% 46.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7830278 2.53% 49.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80611792 26.00% 75.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3104970 1.00% 76.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72755101 23.47% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 522761 0.17% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 112635 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102585339 33.06% 33.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23772488 7.66% 40.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 19036495 6.13% 46.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7825788 2.52% 49.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 80603332 25.97% 75.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3104423 1.00% 76.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72752969 23.45% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 520222 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111941 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 310035010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 310312997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164564 7.88% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164594 7.88% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available @@ -522,12 +522,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1763434 84.48% 92.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159280 7.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1764434 84.50% 92.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159044 7.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 297202 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829439322 95.96% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 296261 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829427794 95.96% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued @@ -556,250 +556,248 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25154463 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9437732 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25158656 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9430470 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864328719 # Type of FU issued -system.cpu.iq.rate 1.827541 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2087278 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041042185 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893535851 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853927067 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866118699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 96 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1579181 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 864313181 # Type of FU issued +system.cpu.iq.rate 1.826439 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2088072 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002416 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2041288204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893536846 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853917717 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 410 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866104816 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1579729 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3618734 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20083 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12084 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2054359 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3631905 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20141 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12168 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2053612 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821519 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4487 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821470 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4399 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4111631 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27910035 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1927143 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867477863 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 297836 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18909339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10455877 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 883178 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 975186 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15536 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12084 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 697834 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 626380 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1324214 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862437508 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24726867 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1891210 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4112827 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27932530 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1927286 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867488637 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 301587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18923985 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10455746 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 885039 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 975379 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15665 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12168 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 701708 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 624080 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1325788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862427395 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24732275 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1885785 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33920253 # number of memory reference insts executed -system.cpu.iew.exec_branches 86495383 # Number of branches executed -system.cpu.iew.exec_stores 9193386 # Number of stores executed -system.cpu.iew.exec_rate 1.823543 # Inst execution rate -system.cpu.iew.wb_sent 861952908 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853927121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669642895 # num instructions producing a value -system.cpu.iew.wb_consumers 1918737755 # num instructions consuming a value +system.cpu.iew.exec_refs 33921373 # number of memory reference insts executed +system.cpu.iew.exec_branches 86494176 # Number of branches executed +system.cpu.iew.exec_stores 9189098 # Number of stores executed +system.cpu.iew.exec_rate 1.822454 # Inst execution rate +system.cpu.iew.wb_sent 861944484 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853917813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 669630870 # num instructions producing a value +system.cpu.iew.wb_consumers 1918703675 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.805548 # insts written-back per cycle +system.cpu.iew.wb_rate 1.804472 # insts written-back per cycle system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426515724 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840516219 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26857823 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515773 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1181578 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 305938932 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.747333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.861326 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426513995 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840512563 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26872606 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515656 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1183314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 306215725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.744838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.861126 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 125006118 40.86% 40.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14720749 4.81% 45.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4254060 1.39% 47.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76641454 25.05% 72.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3896789 1.27% 73.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1794252 0.59% 73.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1101361 0.36% 74.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71996786 23.53% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6527363 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 125266635 40.91% 40.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14734551 4.81% 45.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4258737 1.39% 47.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76646765 25.03% 72.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3892941 1.27% 73.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1792387 0.59% 74.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1104205 0.36% 74.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71994718 23.51% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6524786 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 305938932 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426515724 # Number of instructions committed -system.cpu.commit.committedOps 840516219 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 306215725 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426513995 # Number of instructions committed +system.cpu.commit.committedOps 840512563 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23692120 # Number of memory references committed -system.cpu.commit.loads 15290602 # Number of loads committed -system.cpu.commit.membars 781565 # Number of memory barriers committed -system.cpu.commit.branches 85505775 # Number of branches committed +system.cpu.commit.refs 23694211 # Number of memory references committed +system.cpu.commit.loads 15292077 # Number of loads committed +system.cpu.commit.membars 781571 # Number of memory barriers committed +system.cpu.commit.branches 85505598 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768334838 # Number of committed integer instructions. +system.cpu.commit.int_insts 768332766 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6527363 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6524786 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1166706140 # The number of ROB reads -system.cpu.rob.rob_writes 1738874776 # The number of ROB writes -system.cpu.timesIdled 2996123 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162911165 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9872855838 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426515724 # Number of Instructions Simulated -system.cpu.committedOps 840516219 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426515724 # Number of Instructions Simulated -system.cpu.cpi 1.108860 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108860 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901827 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.901827 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163141042 # number of integer regfile reads -system.cpu.int_regfile_writes 1362663536 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 281062978 # number of misc regfile reads -system.cpu.misc_regfile_writes 403820 # number of misc regfile writes -system.cpu.icache.replacements 1070658 # number of replacements -system.cpu.icache.tagsinuse 510.425099 # Cycle average of tags in use -system.cpu.icache.total_refs 8224431 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1071170 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.677989 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56932899000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.425099 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996924 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996924 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8224431 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8224431 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8224431 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8224431 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8224431 # number of overall hits -system.cpu.icache.overall_hits::total 8224431 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1140947 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1140947 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1140947 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1140947 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1140947 # number of overall misses -system.cpu.icache.overall_misses::total 1140947 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18841256486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18841256486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18841256486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18841256486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18841256486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18841256486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9365378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9365378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9365378 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9365378 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9365378 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9365378 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121826 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121826 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121826 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121826 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121826 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121826 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16513.700011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16513.700011 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3271992 # number of cycles access was blocked +system.cpu.rob.rob_reads 1166996622 # The number of ROB reads +system.cpu.rob.rob_writes 1738897212 # The number of ROB writes +system.cpu.timesIdled 2997983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162910091 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9872594876 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426513995 # Number of Instructions Simulated +system.cpu.committedOps 840512563 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426513995 # Number of Instructions Simulated +system.cpu.cpi 1.109514 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.109514 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901296 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.901296 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2163164515 # number of integer regfile reads +system.cpu.int_regfile_writes 1362660599 # number of integer regfile writes +system.cpu.fp_regfile_reads 96 # number of floating regfile reads +system.cpu.misc_regfile_reads 281055752 # number of misc regfile reads +system.cpu.misc_regfile_writes 403699 # number of misc regfile writes +system.cpu.icache.replacements 1072786 # number of replacements +system.cpu.icache.tagsinuse 510.225454 # Cycle average of tags in use +system.cpu.icache.total_refs 8218240 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1073298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.656997 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56932893000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.225454 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996534 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996534 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8218240 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8218240 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8218240 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8218240 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8218240 # number of overall hits +system.cpu.icache.overall_hits::total 8218240 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1144801 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1144801 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1144801 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1144801 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1144801 # number of overall misses +system.cpu.icache.overall_misses::total 1144801 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18871083485 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18871083485 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18871083485 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18871083485 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18871083485 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18871083485 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9363041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9363041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9363041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9363041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9363041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9363041 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122268 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.122268 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.122268 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.122268 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.122268 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.122268 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16484.160553 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16484.160553 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16484.160553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16484.160553 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3261491 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 378 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8200.481203 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8628.283069 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1605 # number of writebacks -system.cpu.icache.writebacks::total 1605 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69655 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69655 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69655 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69655 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69655 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69655 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071292 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1071292 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1071292 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1071292 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1071292 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1071292 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14719464992 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14719464992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14719464992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14719464992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14719464992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14719464992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114389 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114389 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114389 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69972 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69972 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69972 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69972 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69972 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69972 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074829 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1074829 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1074829 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1074829 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1074829 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1074829 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14733142991 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14733142991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14733142991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14733142991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14733142991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14733142991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114795 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114795 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114795 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13707.429732 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13707.429732 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10504 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.031363 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 31807 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10516 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.024629 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5135227037000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.031363 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376960 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376960 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31848 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 31848 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11223 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.037503 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 31260 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11237 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.781881 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5131387386000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.037503 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377344 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.377344 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31468 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 31468 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31851 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 31851 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31851 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 31851 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11386 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11386 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11386 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 11386 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11386 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 11386 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 182254500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 182254500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 182254500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 182254500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 182254500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 182254500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43234 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 43234 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31471 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 31471 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31471 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 31471 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12107 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12107 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12107 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12107 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12107 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12107 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 196957000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 196957000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 196957000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 196957000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 196957000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 196957000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43575 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43575 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43237 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 43237 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43237 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 43237 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.263358 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.263358 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.263339 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.263339 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.263339 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.263339 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43578 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 43578 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43578 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 43578 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.277843 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.277843 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.277824 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.277824 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.277824 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.277824 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16268.026761 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16268.026761 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16268.026761 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16268.026761 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,78 +806,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1641 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1641 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11386 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11386 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11386 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11386 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11386 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11386 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147453030 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147453030 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147453030 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147453030 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147453030 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147453030 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.263358 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.263358 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.263339 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.263339 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1700 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1700 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12107 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12107 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12107 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 12107 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12107 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 12107 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159950045 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159950045 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159950045 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159950045 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159950045 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159950045 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.277843 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.277843 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.277824 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.277824 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13211.369043 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 117278 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.523999 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 136775 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 117293 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.166097 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5112876101000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.523999 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.845250 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.845250 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 136779 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 136779 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 136779 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 136779 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 136779 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 136779 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 118304 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 118304 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 118304 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 118304 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 118304 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 118304 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2123660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2123660000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2123660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2123660000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2123660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2123660000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255083 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 255083 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255083 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 255083 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255083 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 255083 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463786 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463786 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463786 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463786 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463786 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463786 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 118986 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.873264 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 132191 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 119002 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.110830 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5112880781000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.873264 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.867079 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.867079 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 132191 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 132191 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 132191 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 132191 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 132191 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 132191 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 120057 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 120057 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 120057 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 120057 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 120057 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 120057 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2156991000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2156991000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2156991000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2156991000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2156991000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2156991000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 252248 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 252248 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 252248 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 252248 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 252248 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 252248 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.475948 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.475948 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.475948 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.475948 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.475948 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.475948 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17966.390964 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17966.390964 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17966.390964 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17966.390964 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,146 +886,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 37674 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 37674 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118304 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118304 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118304 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 118304 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 118304 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 118304 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1766049009 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1766049009 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1766049009 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463786 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463786 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463786 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 34205 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 34205 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 120057 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 120057 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 120057 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 120057 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 120057 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 120057 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1794187508 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1794187508 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1794187508 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.475948 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.475948 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.475948 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14944.463946 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673136 # number of replacements -system.cpu.dcache.tagsinuse 511.997556 # Cycle average of tags in use -system.cpu.dcache.total_refs 19006106 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673648 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.356095 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1672900 # number of replacements +system.cpu.dcache.tagsinuse 511.996980 # Cycle average of tags in use +system.cpu.dcache.total_refs 19011613 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673412 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.360988 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997556 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10928708 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10928708 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8074811 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8074811 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19003519 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19003519 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19003519 # number of overall hits -system.cpu.dcache.overall_hits::total 19003519 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2430538 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2430538 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317333 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317333 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2747871 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2747871 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2747871 # number of overall misses -system.cpu.dcache.overall_misses::total 2747871 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45186101000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45186101000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10603069990 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10603069990 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55789170990 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55789170990 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55789170990 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55789170990 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13359246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13359246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8392144 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8392144 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21751390 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21751390 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21751390 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21751390 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181937 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.181937 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.126331 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.126331 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.126331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.126331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20302.689242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20302.689242 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27875990 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.996980 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10933058 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10933058 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8074504 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8074504 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19007562 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19007562 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19007562 # number of overall hits +system.cpu.dcache.overall_hits::total 19007562 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2431156 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2431156 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318255 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2749411 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2749411 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2749411 # number of overall misses +system.cpu.dcache.overall_misses::total 2749411 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45213675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45213675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10676522982 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10676522982 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55890198482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55890198482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55890198482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55890198482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13364214 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13364214 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8392759 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8392759 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21756973 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21756973 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21756973 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21756973 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181915 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.181915 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037920 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.126369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.126369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.126369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.126369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18597.603568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18597.603568 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33547.070689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33547.070689 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20328.062440 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20328.062440 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20328.062440 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20328.062440 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26730982 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4911 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5623.560621 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5443.083282 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1572269 # number of writebacks -system.cpu.dcache.writebacks::total 1572269 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049151 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1049151 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22726 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22726 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1071877 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1071877 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1071877 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1071877 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381387 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381387 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294607 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294607 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1675994 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1675994 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1675994 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1675994 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23290713035 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23290713035 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9337845997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9337845997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32628559032 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32628559032 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32628559032 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32628559032 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207723000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207723000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386731000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386731000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594454000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594454000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035105 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035105 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077052 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1571690 # number of writebacks +system.cpu.dcache.writebacks::total 1571690 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049439 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1049439 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22786 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22786 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1072225 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1072225 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1072225 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1072225 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381717 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1381717 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295469 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 295469 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1677186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1677186 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1677186 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1677186 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23302977034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23302977034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9408800483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9408800483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32711777517 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32711777517 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32711777517 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32711777517 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208357000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208357000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386111000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386111000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594468000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594468000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035205 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077087 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077087 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16865.231472 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16865.231472 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31843.612978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31843.612978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index 7b9ea05e8..c9fc9d3a5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -642,30 +642,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -706,30 +696,20 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=32768 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.sequencer] type=RubySequencer @@ -766,16 +746,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=4194304 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.pc] type=Pc @@ -1020,7 +995,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1040,7 +1015,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1215,9 +1190,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=8 +width=64 default=system.pc.pciconfig.pio -master=system.physmem.port system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave +master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master [system.ruby] @@ -1244,104 +1219,74 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl1 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.ext_links3] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links3.int_node +int_node=system.ruby.network.topology.routers3 latency=1 link_id=3 weight=1 -[system.ruby.network.topology.ext_links3.int_node] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.ext_links4] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dma_cntrl0 -int_node=system.ruby.network.topology.ext_links4.int_node +int_node=system.ruby.network.topology.routers4 latency=1 link_id=4 weight=1 -[system.ruby.network.topology.ext_links4.int_node] -type=BasicRouter -router_id=4 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers5 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=5 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=6 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers5 weight=1 [system.ruby.network.topology.int_links2] @@ -1349,8 +1294,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=7 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers5 weight=1 [system.ruby.network.topology.int_links3] @@ -1358,8 +1303,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=8 -node_a=system.ruby.network.topology.ext_links3.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers3 +node_b=system.ruby.network.topology.routers5 weight=1 [system.ruby.network.topology.int_links4] @@ -1367,10 +1312,34 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=9 -node_a=system.ruby.network.topology.ext_links4.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers4 +node_b=system.ruby.network.topology.routers5 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers4] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers5] +type=BasicRouter +router_id=5 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr index a4244c4ca..62578ab56 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr @@ -3,10 +3,8 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: instruction 'fxsave' unimplemented -warn: x86 cpuid: unknown family 0x8086 warn: instruction 'wbinvd' unimplemented warn: instruction 'wbinvd' unimplemented -warn: x86 cpuid: unknown family 0x8086 hack: Assuming logical destinations are 1 << id. warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 00f64894a..d6cb455f2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 08:55:10 -gem5 started Jul 22 2012 08:55:16 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jun 4 2012 13:44:12 +gem5 started Jun 4 2012 17:11:29 +gem5 executing on zizzer command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5305568377500 because m5_exit instruction encountered +Exiting @ tick 5304689685500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 90df3051e..b7d143468 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,107 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305568 # Number of seconds simulated -sim_ticks 5305568377500 # Number of ticks simulated -final_tick 5305568377500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.304690 # Number of seconds simulated +sim_ticks 5304689685500 # Number of ticks simulated +final_tick 5304689685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148548 # Simulator instruction rate (inst/s) -host_op_rate 304739 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5673062484 # Simulator tick rate (ticks/s) -host_mem_usage 518516 # Number of bytes of host memory used -host_seconds 935.22 # Real time elapsed on the host -sim_insts 138925597 # Number of instructions simulated -sim_ops 284998538 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 843619360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40106316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 468873856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 53484588 # Number of bytes read from this memory -system.physmem.bytes_read::total 1406451096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 843619360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 468873856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1312493216 # Number of instructions bytes read from this memory +host_inst_rate 163049 # Simulator instruction rate (inst/s) +host_op_rate 333085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6301127704 # Simulator tick rate (ticks/s) +host_mem_usage 481488 # Number of bytes of host memory used +host_seconds 841.86 # Real time elapsed on the host +sim_insts 137264752 # Number of instructions simulated +sim_ops 280412254 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 126800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 827772912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 39626426 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 100784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 45696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470347440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 53905938 # Number of bytes read from this memory +system.physmem.bytes_read::total 1392025556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 827772912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470347440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1298120352 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 32433610 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 35512400 # Number of bytes written to this memory -system.physmem.bytes_written::total 70937130 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 105452420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6721793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58609232 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8980167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 179805900 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 32173132 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 35738580 # Number of bytes written to this memory +system.physmem.bytes_written::total 70902832 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15850 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 103471614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6642662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12598 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58793430 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9050935 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178001662 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4872539 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4951932 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9871209 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159006406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7559287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 88373916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10080840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265089618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159006406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 88373916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247380322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 4837067 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4982709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9866514 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 23903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 12143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 156045492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7470074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 18999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88666344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10161940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 262414135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 156045492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88666344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 244711836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563860 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6113126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6693420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13370317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159006406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13672414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 88373916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16774261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278459935 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.physmem.bw_write::cpu0.data 6065036 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6737167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13366066 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 23903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 12146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 156045492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13535110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 18999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88666344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16899107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275780201 # Total bandwidth to/from this memory (bytes/s) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -114,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10611136755 # number of cpu cycles simulated +system.cpu0.numCycles 10608177450 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 90467113 # Number of instructions committed -system.cpu0.committedOps 191744891 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 172320091 # Number of integer alu accesses +system.cpu0.committedInsts 88690468 # Number of instructions committed +system.cpu0.committedOps 187060545 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 168469813 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 18433408 # number of instructions that are conditional controls -system.cpu0.num_int_insts 172320091 # number of integer instructions +system.cpu0.num_conditional_control_insts 17923925 # number of instructions that are conditional controls +system.cpu0.num_int_insts 168469813 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 529438037 # number of times the integer registers were read -system.cpu0.num_int_register_writes 286410601 # number of times the integer registers were written +system.cpu0.num_int_register_reads 517963630 # number of times the integer registers were read +system.cpu0.num_int_register_writes 280483339 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 19683230 # number of memory refs -system.cpu0.num_load_insts 14799913 # Number of load instructions -system.cpu0.num_store_insts 4883317 # Number of store instructions -system.cpu0.num_idle_cycles 10087385086.886099 # Number of idle cycles -system.cpu0.num_busy_cycles 523751668.113901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles +system.cpu0.num_mem_refs 19132508 # number of memory refs +system.cpu0.num_load_insts 14284566 # Number of load instructions +system.cpu0.num_store_insts 4847942 # Number of store instructions +system.cpu0.num_idle_cycles 10086452980.871330 # Number of idle cycles +system.cpu0.num_busy_cycles 521724469.128670 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049181 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950819 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10608184676 # number of cpu cycles simulated +system.cpu1.numCycles 10609379371 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48458484 # Number of instructions committed -system.cpu1.committedOps 93253647 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88897203 # Number of integer alu accesses +system.cpu1.committedInsts 48574284 # Number of instructions committed +system.cpu1.committedOps 93351709 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 89110416 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8156142 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88897203 # number of integer instructions +system.cpu1.num_conditional_control_insts 8197841 # number of instructions that are conditional controls +system.cpu1.num_int_insts 89110416 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 272264147 # number of times the integer registers were read -system.cpu1.num_int_register_writes 138280138 # number of times the integer registers were written +system.cpu1.num_int_register_reads 273178604 # number of times the integer registers were read +system.cpu1.num_int_register_writes 138760228 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14383325 # number of memory refs -system.cpu1.num_load_insts 9129593 # Number of load instructions -system.cpu1.num_store_insts 5253732 # Number of store instructions -system.cpu1.num_idle_cycles 10274264583.773684 # Number of idle cycles -system.cpu1.num_busy_cycles 333920092.226317 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles +system.cpu1.num_mem_refs 14426742 # number of memory refs +system.cpu1.num_load_insts 9181010 # Number of load instructions +system.cpu1.num_store_insts 5245732 # Number of store instructions +system.cpu1.num_idle_cycles 10273661233.326063 # Number of idle cycles +system.cpu1.num_busy_cycles 335718137.673937 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031644 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968356 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |