diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
4 files changed, 3155 insertions, 2749 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index c0ebf9d4a..c331380ec 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -106,6 +114,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -167,6 +177,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -175,6 +186,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -190,6 +202,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -212,18 +225,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -234,6 +250,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -256,6 +273,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -263,15 +281,18 @@ size=1024 type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -280,16 +301,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -298,22 +322,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -322,22 +350,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -346,10 +378,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -358,124 +392,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -484,10 +539,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -496,16 +553,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -514,10 +574,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -528,6 +590,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -550,12 +613,14 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -566,16 +631,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -586,6 +654,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -608,6 +677,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -617,6 +687,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -639,12 +710,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -654,44 +727,52 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -699,6 +780,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -711,6 +793,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -722,6 +805,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -729,16 +813,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -749,6 +836,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -759,6 +847,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -769,6 +858,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -779,6 +869,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -789,6 +880,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -799,6 +891,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -809,6 +902,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -819,6 +913,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -829,6 +924,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -839,6 +935,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -849,6 +946,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -859,6 +957,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -869,6 +968,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -879,6 +979,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -889,6 +990,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -899,6 +1001,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -909,6 +1012,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -919,6 +1023,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -929,6 +1034,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -939,6 +1045,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -949,6 +1056,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -959,6 +1067,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -969,6 +1078,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -979,6 +1089,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -989,6 +1100,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -999,6 +1111,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1009,6 +1122,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1019,6 +1133,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1028,16 +1143,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1051,6 +1169,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1073,6 +1192,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1080,6 +1200,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1091,6 +1212,7 @@ slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side sy [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1107,13 +1229,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1132,6 +1256,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1141,13 +1266,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1156,6 +1275,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1173,6 +1293,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1190,6 +1311,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1207,6 +1329,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1224,6 +1347,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1242,6 +1366,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -1254,6 +1379,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -1266,6 +1392,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1275,10 +1402,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1307,6 +1436,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1316,8 +1446,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -1329,6 +1491,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1345,19 +1508,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1365,102 +1531,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1475,6 +1659,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1484,14 +1669,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1502,11 +1690,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1517,11 +1707,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1530,10 +1722,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1552,6 +1746,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1563,19 +1758,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1586,6 +1785,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1596,5 +1796,6 @@ version= [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 8fd17006a..f9f231b7b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133932 # Number of seconds simulated -sim_ticks 5133932129000 # Number of ticks simulated -final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133933 # Number of seconds simulated +sim_ticks 5133933067000 # Number of ticks simulated +final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157497 # Simulator instruction rate (inst/s) -host_op_rate 311329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1982921852 # Simulator tick rate (ticks/s) -host_mem_usage 759792 # Number of bytes of host memory used -host_seconds 2589.07 # Real time elapsed on the host -sim_insts 407772261 # Number of instructions simulated -sim_ops 806052921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory +host_inst_rate 121984 # Simulator instruction rate (inst/s) +host_op_rate 241126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1535878817 # Simulator tick rate (ticks/s) +host_mem_usage 781700 # Number of bytes of host memory used +host_seconds 3342.67 # Real time elapsed on the host +sim_insts 407751929 # Number of instructions simulated +sim_ops 806002693 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory -system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory -system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1029376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10746496 # Number of bytes read from this memory +system.physmem.bytes_read::total 14217280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1029376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1029376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9492672 # Number of bytes written to this memory +system.physmem.bytes_written::total 9492672 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38081 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16084 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167914 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222145 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148323 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148323 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 474721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2093229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2769276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1849006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1849006 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1849006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 474721 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222430 # Number of read requests accepted -system.physmem.writeReqs 148587 # Number of write requests accepted -system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue -system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 200504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2093229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4618282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222145 # Number of read requests accepted +system.physmem.writeReqs 148323 # Number of write requests accepted +system.physmem.readBursts 222145 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148323 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14211648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.bytesWritten 9492416 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14217280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9492672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14853 # Per bank write bursts -system.physmem.perBankRdBursts::1 13635 # Per bank write bursts -system.physmem.perBankRdBursts::2 14415 # Per bank write bursts -system.physmem.perBankRdBursts::3 13770 # Per bank write bursts -system.physmem.perBankRdBursts::4 14136 # Per bank write bursts -system.physmem.perBankRdBursts::5 13341 # Per bank write bursts -system.physmem.perBankRdBursts::6 13755 # Per bank write bursts -system.physmem.perBankRdBursts::7 13953 # Per bank write bursts -system.physmem.perBankRdBursts::8 13590 # Per bank write bursts -system.physmem.perBankRdBursts::9 13369 # Per bank write bursts -system.physmem.perBankRdBursts::10 13469 # Per bank write bursts -system.physmem.perBankRdBursts::11 13962 # Per bank write bursts -system.physmem.perBankRdBursts::12 14252 # Per bank write bursts -system.physmem.perBankRdBursts::13 14454 # Per bank write bursts -system.physmem.perBankRdBursts::14 13844 # Per bank write bursts -system.physmem.perBankRdBursts::15 13571 # Per bank write bursts -system.physmem.perBankWrBursts::0 10225 # Per bank write bursts -system.physmem.perBankWrBursts::1 9089 # Per bank write bursts -system.physmem.perBankWrBursts::2 9605 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1715 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14970 # Per bank write bursts +system.physmem.perBankRdBursts::1 13960 # Per bank write bursts +system.physmem.perBankRdBursts::2 14769 # Per bank write bursts +system.physmem.perBankRdBursts::3 13764 # Per bank write bursts +system.physmem.perBankRdBursts::4 13644 # Per bank write bursts +system.physmem.perBankRdBursts::5 13392 # Per bank write bursts +system.physmem.perBankRdBursts::6 13407 # Per bank write bursts +system.physmem.perBankRdBursts::7 13589 # Per bank write bursts +system.physmem.perBankRdBursts::8 13408 # Per bank write bursts +system.physmem.perBankRdBursts::9 13258 # Per bank write bursts +system.physmem.perBankRdBursts::10 13821 # Per bank write bursts +system.physmem.perBankRdBursts::11 13878 # Per bank write bursts +system.physmem.perBankRdBursts::12 14332 # Per bank write bursts +system.physmem.perBankRdBursts::13 14527 # Per bank write bursts +system.physmem.perBankRdBursts::14 13749 # Per bank write bursts +system.physmem.perBankRdBursts::15 13589 # Per bank write bursts +system.physmem.perBankWrBursts::0 10370 # Per bank write bursts +system.physmem.perBankWrBursts::1 9405 # Per bank write bursts +system.physmem.perBankWrBursts::2 9871 # Per bank write bursts system.physmem.perBankWrBursts::3 9165 # Per bank write bursts -system.physmem.perBankWrBursts::4 9475 # Per bank write bursts -system.physmem.perBankWrBursts::5 8866 # Per bank write bursts -system.physmem.perBankWrBursts::6 9032 # Per bank write bursts -system.physmem.perBankWrBursts::7 9363 # Per bank write bursts -system.physmem.perBankWrBursts::8 8843 # Per bank write bursts -system.physmem.perBankWrBursts::9 8764 # Per bank write bursts -system.physmem.perBankWrBursts::10 9099 # Per bank write bursts -system.physmem.perBankWrBursts::11 9352 # Per bank write bursts -system.physmem.perBankWrBursts::12 9596 # Per bank write bursts -system.physmem.perBankWrBursts::13 9639 # Per bank write bursts -system.physmem.perBankWrBursts::14 9447 # Per bank write bursts -system.physmem.perBankWrBursts::15 9010 # Per bank write bursts +system.physmem.perBankWrBursts::4 9017 # Per bank write bursts +system.physmem.perBankWrBursts::5 8953 # Per bank write bursts +system.physmem.perBankWrBursts::6 8740 # Per bank write bursts +system.physmem.perBankWrBursts::7 8992 # Per bank write bursts +system.physmem.perBankWrBursts::8 8721 # Per bank write bursts +system.physmem.perBankWrBursts::9 8568 # Per bank write bursts +system.physmem.perBankWrBursts::10 9309 # Per bank write bursts +system.physmem.perBankWrBursts::11 9216 # Per bank write bursts +system.physmem.perBankWrBursts::12 9686 # Per bank write bursts +system.physmem.perBankWrBursts::13 9800 # Per bank write bursts +system.physmem.perBankWrBursts::14 9415 # Per bank write bursts +system.physmem.perBankWrBursts::15 9091 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 5133932076000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 5133933013500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222430 # Read request sizes (log2) +system.physmem.readPktSize::6 222145 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148587 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148323 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 174666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1072 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 555 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -139,266 +139,264 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 6022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 7121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 7236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 68754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.735608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 150.882581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1084.800437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 30893 44.93% 44.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 10573 15.38% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 6859 9.98% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 4406 6.41% 76.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2663 3.87% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2166 3.15% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1652 2.40% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1226 1.78% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1018 1.48% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 978 1.42% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 656 0.95% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 637 0.93% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 446 0.65% 93.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 438 0.64% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 344 0.50% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 542 0.79% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 252 0.37% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 218 0.32% 95.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 163 0.24% 96.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 136 0.20% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 158 0.23% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 420 0.61% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 150 0.22% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 127 0.18% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 107 0.16% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 87 0.13% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 64 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 17 0.02% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 43 0.06% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 19 0.03% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 31 0.05% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 40 0.06% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.01% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 16 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 31 0.05% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 10 0.01% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 13 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 31 0.05% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 6 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 27 0.04% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 9 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 12 0.02% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 28 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 7 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 25 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 26 0.04% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 10 0.01% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 5 0.01% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 9 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 15 0.02% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 3 0.00% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 27 0.04% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 23 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 5 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 25 0.04% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 4 0.01% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 22 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.00% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 4 0.01% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 2 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 4 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 3 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 24 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 4 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 24 0.03% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 3 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 24 0.03% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 3 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 4 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 23 0.03% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 75 0.11% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 3 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 5 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 3 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 9 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 5 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 3 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 15 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 5 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 3 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 5 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 25 0.04% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 6 0.01% 99.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 3 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 8 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 4 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 10 0.01% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation -system.physmem.totQLat 5163279754 # Total ticks spent queuing -system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers -system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks -system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 68754 # Bytes accessed per row activation +system.physmem.totQLat 5103462500 # Total ticks spent queuing +system.physmem.totMemAccLat 9310522500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1110285000 # Total ticks spent in databus transfers +system.physmem.totBankLat 3096775000 # Total ticks spent accessing banks +system.physmem.avgQLat 22982.67 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13945.86 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41928.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s @@ -408,71 +406,71 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing -system.physmem.readRowHits 193089 # Number of row buffer hits during reads -system.physmem.writeRowHits 108689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 13837457.79 # Average gap between requests -system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing +system.physmem.readRowHits 193293 # Number of row buffer hits during reads +system.physmem.writeRowHits 108329 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes +system.physmem.avgGap 13857966.18 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 5101771 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662370 # Transaction distribution -system.membus.trans_dist::ReadResp 662362 # Transaction distribution -system.membus.trans_dist::WriteReq 13778 # Transaction distribution -system.membus.trans_dist::WriteResp 13778 # Transaction distribution -system.membus.trans_dist::Writeback 148587 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution -system.membus.trans_dist::ReadExReq 179504 # Transaction distribution -system.membus.trans_dist::ReadExResp 179502 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25543633 # Total data (bytes) -system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks) +system.membus.throughput 5095991 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662317 # Transaction distribution +system.membus.trans_dist::ReadResp 662311 # Transaction distribution +system.membus.trans_dist::WriteReq 13762 # Transaction distribution +system.membus.trans_dist::WriteResp 13762 # Transaction distribution +system.membus.trans_dist::Writeback 148323 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2201 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1734 # Transaction distribution +system.membus.trans_dist::ReadExReq 179351 # Transaction distribution +system.membus.trans_dist::ReadExResp 179346 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 474374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856159 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18286080 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20078023 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5423872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5423872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25508463 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25508463 # Total data (bytes) +system.membus.snoop_data_through_bus 654016 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250556000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583258500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1605908499 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3150989153 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429464748 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47576 # number of replacements -system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.103980 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 4992951939000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses @@ -483,14 +481,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47631 system.iocache.demand_misses::total 47631 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151022435 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151022435 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11480088301 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11480088301 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11631110736 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11631110736 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11631110736 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11631110736 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -507,19 +505,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165776.547750 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 245721.068086 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 244192.033256 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 244192.033256 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 172788 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10383 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.641433 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -533,14 +531,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 103624935 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 103624935 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9049102305 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9049102305 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9152727240 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9152727240 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9152727240 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -549,18 +547,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 192159.040121 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -570,16 +568,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638153 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225567 # Transaction distribution -system.iobus.trans_dist::ReadResp 225567 # Transaction distribution -system.iobus.trans_dist::WriteReq 57606 # Transaction distribution -system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.throughput 638147 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225559 # Transaction distribution +system.iobus.trans_dist::ReadResp 225559 # Transaction distribution +system.iobus.trans_dist::WriteReq 57591 # Transaction distribution +system.iobus.trans_dist::WriteResp 57591 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -595,15 +593,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569584 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -619,20 +617,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276232 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276202 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276202 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3916600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -662,153 +660,153 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424364988 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53080252 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85592238 # Number of BP lookups -system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits +system.cpu.branchPred.lookups 85602749 # Number of BP lookups +system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79146839 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77528417 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions. -system.cpu.numCycles 453841851 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions. +system.cpu.numCycles 453810576 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25587128 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422793434 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85602749 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78973010 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162653475 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3995125 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 108453 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71359520 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87857 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8489508 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 384110 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2391 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262908725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.175877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411274 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100670178 38.29% 38.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1530444 0.58% 38.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71820335 27.32% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 896426 0.34% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1566584 0.60% 67.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2396730 0.91% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1019321 0.39% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1330214 0.51% 68.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81678493 31.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262908725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188631 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931652 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29469022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68533895 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158500921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3336716 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3068171 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832628882 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3068171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32166033 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43333689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12473461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158788115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13079256 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829706187 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21464 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6056720 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5143219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991368832 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800529447 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1106981108 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 114 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963921381 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27447449 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 454679 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29562257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16738170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9831898 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099509 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 931888 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824922108 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1185282 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820965230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 150616 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19266581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29327510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130776 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262908725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.122625 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.401229 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76541753 29.11% 29.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15760378 5.99% 35.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10546081 4.01% 39.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7369618 2.80% 41.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75729447 28.80% 70.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3748882 1.43% 72.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72293205 27.50% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 772480 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 146881 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262908725 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 349560 33.18% 33.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1967 0.19% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548780 52.08% 85.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153094 14.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 307236 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793474466 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149866 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124488 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -835,283 +833,283 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17682042 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9227132 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued -system.cpu.iq.rate 1.808871 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820965230 # Type of FU issued +system.cpu.iq.rate 1.809048 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1053642 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001283 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906151693 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845384400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817050943 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 198 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821711543 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694469 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2748093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19141 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11819 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1409863 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931395 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11998 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3068171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31463417 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2151711 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826107390 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 248376 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16738170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9831898 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690155 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12279 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11819 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498534 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508074 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1006608 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819554351 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17378079 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1410878 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed -system.cpu.iew.exec_branches 83090404 # Number of branches executed -system.cpu.iew.exec_stores 9036920 # Number of stores executed -system.cpu.iew.exec_rate 1.805776 # Inst execution rate -system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638560375 # num instructions producing a value -system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value +system.cpu.iew.exec_refs 26421028 # number of memory reference insts executed +system.cpu.iew.exec_branches 83090233 # Number of branches executed +system.cpu.iew.exec_stores 9042949 # Number of stores executed +system.cpu.iew.exec_rate 1.805939 # Inst execution rate +system.cpu.iew.wb_sent 819150966 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817050997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638575855 # num instructions producing a value +system.cpu.iew.wb_consumers 1043882621 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800423 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611731 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19994665 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054506 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892807 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259840554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.101913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863847 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88304488 33.98% 33.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11858711 4.56% 38.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3833949 1.48% 40.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74748511 28.77% 68.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2384583 0.92% 69.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1475819 0.57% 70.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859128 0.33% 70.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70844564 27.26% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5530801 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407772261 # Number of instructions committed -system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259840554 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407751929 # Number of instructions committed +system.cpu.commit.committedOps 806002693 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22412414 # Number of memory references committed -system.cpu.commit.loads 13990896 # Number of loads committed -system.cpu.commit.membars 474709 # Number of memory barriers committed -system.cpu.commit.branches 82160310 # Number of branches committed +system.cpu.commit.refs 22412111 # Number of memory references committed +system.cpu.commit.loads 13990076 # Number of loads committed +system.cpu.commit.membars 474663 # Number of memory barriers committed +system.cpu.commit.branches 82157264 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734896243 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155289 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734852381 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155163 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5530801 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080212949 # The number of ROB reads -system.cpu.rob.rob_writes 1654925831 # The number of ROB writes -system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407772261 # Number of Instructions Simulated -system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated -system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads -system.cpu.int_regfile_writes 653799671 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads -system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes -system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads -system.cpu.misc_regfile_writes 402440 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080228878 # The number of ROB reads +system.cpu.rob.rob_writes 1655077473 # The number of ROB writes +system.cpu.timesIdled 1260592 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190901851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9814061063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407751929 # Number of Instructions Simulated +system.cpu.committedOps 806002693 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407751929 # Number of Instructions Simulated +system.cpu.cpi 1.112958 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112958 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898507 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898507 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088763208 # number of integer regfile reads +system.cpu.int_regfile_writes 653821136 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.cc_regfile_reads 415622850 # number of cc regfile reads +system.cpu.cc_regfile_writes 321492626 # number of cc regfile writes +system.cpu.misc_regfile_reads 264082516 # number of misc regfile reads +system.cpu.misc_regfile_writes 402300 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53661983 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3016761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3016231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1581663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19443 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 154439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8213573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61324288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207594695 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 616960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5463872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 274999815 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274973191 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 523840 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4039348922 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 624000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1440815600 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3139539816 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14707994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 103656142 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959142 # number of replacements -system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 957724 # number of replacements +system.cpu.icache.tags.tagsinuse 509.254964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7477774 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958236 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.803687 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits -system.cpu.icache.overall_hits::total 7468451 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses -system.cpu.icache.overall_misses::total 1013022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14016.290921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14016.290921 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5333 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.827027 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9803 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9803 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9803 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9803 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9803 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9803 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 89573259 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 89573259 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 89573259 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 89573259 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 89573259 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 89573259 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.324409 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.324409 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.324388 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.324388 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.324388 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9137.331327 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9137.331327 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9137.331327 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 68011 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.842846 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 91726 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 68027 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.348376 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 91726 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91726 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 91726 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69066 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 69066 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69066 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 69066 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69066 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 69066 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 860977213 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 860977213 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 860977213 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 860977213 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 860977213 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 860977213 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160792 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 160792 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160792 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 160792 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160792 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 160792 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429536 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429536 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429536 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429536 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429536 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429536 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1200,146 +1198,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21216 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21216 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69066 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69066 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69066 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 69066 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69066 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 69066 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 722730929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 722730929 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 722730929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 722730929 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 722730929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 722730929 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429536 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429536 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429536 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429536 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1657437 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1656829 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997280 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18997986 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657341 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.462931 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits -system.cpu.dcache.overall_hits::total 18986697 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses 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0.170241 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency 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of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8412501 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412501 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21547385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21547385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21547385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21547385 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170237 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170237 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037570 # miss rate for WriteReq accesses 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average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17740.688563 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 395761 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42262 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.364465 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks -system.cpu.dcache.writebacks::total 1558744 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses 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-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558454 # number of writebacks +system.cpu.dcache.writebacks::total 1558454 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866560 # number of ReadReq MSHR hits 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accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077023 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077023 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077023 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.980852 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.980852 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39085.580621 # average WriteReq mshr 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175285 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.612140 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50850.934653 # Average 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+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370476500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370476500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620751000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620751000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819617 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819617 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461479 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461479 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000654 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016786 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67847.162397 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68719.838612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68468.598373 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10700.436726 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10700.436726 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58587.895543 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58587.895543 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67847.162397 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 404746deb..4079b1ad3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -87,6 +95,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -118,6 +127,7 @@ icache_port=system.cpu0.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu0.dcache] type=BaseCache @@ -125,6 +135,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -147,18 +158,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.toL2Bus.slave[3] @@ -169,6 +183,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -191,12 +206,14 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=X86LocalApic clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -207,22 +224,26 @@ pio=system.membus.master[1] [system.cpu0.isa] type=X86ISA +eventq_index=0 [system.cpu0.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -234,6 +255,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -255,32 +277,38 @@ workload= [system.cpu1.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu1.isa] type=X86ISA +eventq_index=0 [system.cpu1.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -311,6 +339,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -373,6 +403,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -385,12 +416,14 @@ predType=tournament [system.cpu2.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system @@ -398,15 +431,18 @@ system=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -415,16 +451,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -433,22 +472,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -457,22 +500,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -481,10 +528,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -493,124 +542,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -619,10 +689,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -631,16 +703,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -649,69 +724,82 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=X86ISA +eventq_index=0 [system.cpu2.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -719,6 +807,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -731,6 +820,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -742,6 +832,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -749,16 +840,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -769,6 +863,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -779,6 +874,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -789,6 +885,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -799,6 +896,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -809,6 +907,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -819,6 +918,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -829,6 +929,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -839,6 +940,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -849,6 +951,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -859,6 +962,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -869,6 +973,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -879,6 +984,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -889,6 +995,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -899,6 +1006,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -909,6 +1017,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -919,6 +1028,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -929,6 +1039,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -939,6 +1050,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -949,6 +1061,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -959,6 +1072,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -969,6 +1083,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -979,6 +1094,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -989,6 +1105,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -999,6 +1116,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1009,6 +1127,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1019,6 +1138,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1029,6 +1149,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -1039,6 +1160,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -1048,16 +1170,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -1071,6 +1196,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1093,6 +1219,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1102,6 +1229,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1124,6 +1252,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1131,6 +1260,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1142,6 +1272,7 @@ slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1158,13 +1289,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -1183,6 +1316,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -1192,13 +1326,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1207,6 +1335,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -1224,6 +1353,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -1241,6 +1371,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -1258,6 +1389,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -1275,6 +1407,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -1293,6 +1426,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -1305,6 +1439,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -1317,6 +1452,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -1326,10 +1462,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -1358,6 +1496,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1367,8 +1506,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -1380,6 +1551,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1396,19 +1568,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1416,102 +1591,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1526,6 +1719,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1535,14 +1729,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1553,11 +1750,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1568,11 +1767,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1581,10 +1782,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1603,6 +1806,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1614,19 +1818,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1637,6 +1845,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1648,6 +1857,7 @@ version= [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1657,5 +1867,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index e884e1c2d..2b6efde37 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137942 # Number of seconds simulated -sim_ticks 5137941673500 # Number of ticks simulated -final_tick 5137941673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137456 # Number of seconds simulated +sim_ticks 5137456264000 # Number of ticks simulated +final_tick 5137456264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248874 # Simulator instruction rate (inst/s) -host_op_rate 494699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5246911955 # Simulator tick rate (ticks/s) -host_mem_usage 994832 # Number of bytes of host memory used -host_seconds 979.23 # Real time elapsed on the host -sim_insts 243705182 # Number of instructions simulated -sim_ops 484425104 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2466368 # Number of bytes read from this memory +host_inst_rate 176189 # Simulator instruction rate (inst/s) +host_op_rate 350219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3709429360 # Simulator tick rate (ticks/s) +host_mem_usage 1030148 # Number of bytes of host memory used +host_seconds 1384.97 # Real time elapsed on the host +sim_insts 244016231 # Number of instructions simulated +sim_ops 485043652 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2422400 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 426944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5894144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1789248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 385728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2633280 # Number of bytes read from this memory -system.physmem.bytes_read::total 13744640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 426944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 385728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 959872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9091584 # Number of bytes written to this memory -system.physmem.bytes_written::total 9091584 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38537 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 383808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5693376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 137536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1729152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 448384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2947264 # Number of bytes read from this memory +system.physmem.bytes_read::total 13764480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 137536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 448384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 969728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9086592 # Number of bytes written to this memory +system.physmem.bytes_written::total 9086592 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37850 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 92096 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 27957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214760 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142056 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142056 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480030 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 88959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 46051 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141978 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141978 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 471517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 83096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1147180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 28650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 348242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 75074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 512517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2675126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 83096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 28650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 75074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 186820 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1769499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1769499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1108209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 336577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 87277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 573682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2679240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 87277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1768695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1768695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 471517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 83096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1147180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 28650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 75074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 512517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4444625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 100936 # Number of read requests accepted -system.physmem.writeReqs 78380 # Number of write requests accepted -system.physmem.readBursts 100936 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 78380 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6458816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1088 # Total number of bytes read from write queue -system.physmem.bytesWritten 5015040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6459904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5016320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 17 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 74708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1108209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 336577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 87277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 573682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4447935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 102292 # Number of read requests accepted +system.physmem.writeReqs 78374 # Number of write requests accepted +system.physmem.readBursts 102292 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 78374 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6544384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2304 # Total number of bytes read from write queue +system.physmem.bytesWritten 5015936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6546688 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5015936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 699 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5898 # Per bank write bursts -system.physmem.perBankRdBursts::1 6403 # Per bank write bursts -system.physmem.perBankRdBursts::2 6411 # Per bank write bursts -system.physmem.perBankRdBursts::3 6523 # Per bank write bursts -system.physmem.perBankRdBursts::4 6306 # Per bank write bursts -system.physmem.perBankRdBursts::5 6840 # Per bank write bursts -system.physmem.perBankRdBursts::6 6199 # Per bank write bursts -system.physmem.perBankRdBursts::7 6896 # Per bank write bursts -system.physmem.perBankRdBursts::8 5528 # Per bank write bursts -system.physmem.perBankRdBursts::9 5898 # Per bank write bursts -system.physmem.perBankRdBursts::10 6128 # Per bank write bursts -system.physmem.perBankRdBursts::11 6570 # Per bank write bursts -system.physmem.perBankRdBursts::12 6317 # Per bank write bursts -system.physmem.perBankRdBursts::13 6334 # Per bank write bursts -system.physmem.perBankRdBursts::14 6542 # Per bank write bursts -system.physmem.perBankRdBursts::15 6126 # Per bank write bursts -system.physmem.perBankWrBursts::0 4721 # Per bank write bursts -system.physmem.perBankWrBursts::1 4902 # Per bank write bursts -system.physmem.perBankWrBursts::2 4923 # Per bank write bursts -system.physmem.perBankWrBursts::3 5159 # Per bank write bursts -system.physmem.perBankWrBursts::4 5192 # Per bank write bursts -system.physmem.perBankWrBursts::5 5457 # Per bank write bursts -system.physmem.perBankWrBursts::6 4843 # Per bank write bursts -system.physmem.perBankWrBursts::7 5797 # Per bank write bursts -system.physmem.perBankWrBursts::8 4085 # Per bank write bursts -system.physmem.perBankWrBursts::9 4367 # Per bank write bursts -system.physmem.perBankWrBursts::10 4807 # Per bank write bursts -system.physmem.perBankWrBursts::11 4903 # Per bank write bursts -system.physmem.perBankWrBursts::12 4884 # Per bank write bursts -system.physmem.perBankWrBursts::13 4699 # Per bank write bursts -system.physmem.perBankWrBursts::14 5116 # Per bank write bursts -system.physmem.perBankWrBursts::15 4505 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 862 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6805 # Per bank write bursts +system.physmem.perBankRdBursts::1 7244 # Per bank write bursts +system.physmem.perBankRdBursts::2 6375 # Per bank write bursts +system.physmem.perBankRdBursts::3 6857 # Per bank write bursts +system.physmem.perBankRdBursts::4 6927 # Per bank write bursts +system.physmem.perBankRdBursts::5 6780 # Per bank write bursts +system.physmem.perBankRdBursts::6 5925 # Per bank write bursts +system.physmem.perBankRdBursts::7 6310 # Per bank write bursts +system.physmem.perBankRdBursts::8 5868 # Per bank write bursts +system.physmem.perBankRdBursts::9 5795 # Per bank write bursts +system.physmem.perBankRdBursts::10 5783 # Per bank write bursts +system.physmem.perBankRdBursts::11 6231 # Per bank write bursts +system.physmem.perBankRdBursts::12 6160 # Per bank write bursts +system.physmem.perBankRdBursts::13 6316 # Per bank write bursts +system.physmem.perBankRdBursts::14 6211 # Per bank write bursts +system.physmem.perBankRdBursts::15 6669 # Per bank write bursts +system.physmem.perBankWrBursts::0 5462 # Per bank write bursts +system.physmem.perBankWrBursts::1 5811 # Per bank write bursts +system.physmem.perBankWrBursts::2 4880 # Per bank write bursts +system.physmem.perBankWrBursts::3 5445 # Per bank write bursts +system.physmem.perBankWrBursts::4 5542 # Per bank write bursts +system.physmem.perBankWrBursts::5 5461 # Per bank write bursts +system.physmem.perBankWrBursts::6 4520 # Per bank write bursts +system.physmem.perBankWrBursts::7 4685 # Per bank write bursts +system.physmem.perBankWrBursts::8 4152 # Per bank write bursts +system.physmem.perBankWrBursts::9 4422 # Per bank write bursts +system.physmem.perBankWrBursts::10 4208 # Per bank write bursts +system.physmem.perBankWrBursts::11 4507 # Per bank write bursts +system.physmem.perBankWrBursts::12 4889 # Per bank write bursts +system.physmem.perBankWrBursts::13 4664 # Per bank write bursts +system.physmem.perBankWrBursts::14 4834 # Per bank write bursts +system.physmem.perBankWrBursts::15 4892 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 5136941479000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5136272146500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 100936 # Read request sizes (log2) +system.physmem.readPktSize::6 102292 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 78380 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 75816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 78374 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -163,226 +163,227 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.217991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.094116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1121.662575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16547 46.47% 46.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5535 15.54% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3551 9.97% 71.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2213 6.22% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1334 3.75% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1101 3.09% 85.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 807 2.27% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 584 1.64% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 515 1.45% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 517 1.45% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 309 0.87% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 309 0.87% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 205 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 200 0.56% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 177 0.50% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 272 0.76% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 139 0.39% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 84 0.24% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 95 0.27% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 94 0.26% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 81 0.23% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 178 0.50% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 83 0.23% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 58 0.16% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 45 0.13% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 38 0.11% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 29 0.08% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 19 0.05% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 15 0.04% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 14 0.04% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 11 0.03% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 10 0.03% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 6 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 5 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 8 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 3 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 8 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 3 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 5 0.01% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 6 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 10 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 6 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 3 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 3 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.30% # Bytes accessed per row activation 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0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 2 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 2 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 2 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 2 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 3 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 2 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 2 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 3 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 3 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 12 0.03% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.03% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 3 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 5 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 9 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 8 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 29 0.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35607 # Bytes accessed per row activation -system.physmem.totQLat 2741683498 # Total ticks spent queuing -system.physmem.totMemAccLat 4643457248 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 504595000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1397178750 # Total ticks spent accessing banks -system.physmem.avgQLat 27167.17 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13844.56 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 37207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.623700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.064630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1005.971949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16908 45.44% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5765 15.49% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3845 10.33% 71.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2398 6.45% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1477 3.97% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1206 3.24% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 882 2.37% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 634 1.70% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 564 1.52% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 479 1.29% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 331 0.89% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 285 0.77% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 209 0.56% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 204 0.55% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 197 0.53% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 303 0.81% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 153 0.41% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 117 0.31% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 75 0.20% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 61 0.16% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 106 0.28% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 199 0.53% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 97 0.26% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.23% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 45 0.12% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 43 0.12% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 26 0.07% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 28 0.08% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 16 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 12 0.03% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 10 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 10 0.03% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 17 0.05% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 7 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 3 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 9 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 6 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 13 0.03% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 99.13% # Bytes accessed per row activation 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0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 25 0.07% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.40% # Bytes accessed per row activation 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0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 5 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 6 0.02% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 2 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 2 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.02% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 2 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 3 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 11 0.03% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 14 0.04% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 22 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37207 # Bytes accessed per row activation +system.physmem.totQLat 2596442750 # Total ticks spent queuing +system.physmem.totMemAccLat 4566061500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 511280000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1458338750 # Total ticks spent accessing banks +system.physmem.avgQLat 25391.59 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14261.64 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46011.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -390,322 +391,318 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.11 # Average write queue length when enqueuing -system.physmem.readRowHits 85240 # Number of row buffer hits during reads -system.physmem.writeRowHits 58432 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes -system.physmem.avgGap 28647423.98 # Average gap between requests -system.physmem.pageHitRate 80.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.12 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6427951 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 423177 # Transaction distribution -system.membus.trans_dist::ReadResp 423176 # Transaction distribution -system.membus.trans_dist::WriteReq 6474 # Transaction distribution -system.membus.trans_dist::WriteResp 6474 # Transaction distribution -system.membus.trans_dist::Writeback 78380 # Transaction distribution -system.membus.trans_dist::UpgradeReq 714 # Transaction distribution -system.membus.trans_dist::UpgradeResp 714 # Transaction distribution -system.membus.trans_dist::ReadExReq 80216 # Transaction distribution -system.membus.trans_dist::ReadExResp 80216 # Transaction distribution -system.membus.trans_dist::MessageReq 892 # Transaction distribution -system.membus.trans_dist::MessageResp 892 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 310648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 207711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1015985 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 78748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1096517 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159467 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995245 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8228608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9383320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12634504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32719620 # Total data (bytes) -system.membus.snoop_data_through_bus 306816 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 163512000 # Layer occupancy (ticks) +system.physmem.readRowHits 86197 # Number of row buffer hits during reads +system.physmem.writeRowHits 57226 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 28429655.53 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.13 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6440814 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 424797 # Transaction distribution +system.membus.trans_dist::ReadResp 424797 # Transaction distribution +system.membus.trans_dist::WriteReq 7056 # Transaction distribution +system.membus.trans_dist::WriteResp 7056 # Transaction distribution +system.membus.trans_dist::Writeback 78374 # Transaction distribution +system.membus.trans_dist::UpgradeReq 877 # Transaction distribution +system.membus.trans_dist::UpgradeResp 877 # Transaction distribution +system.membus.trans_dist::ReadExReq 80570 # Transaction distribution +system.membus.trans_dist::ReadExResp 80570 # Transaction distribution +system.membus.trans_dist::MessageReq 957 # Transaction distribution +system.membus.trans_dist::MessageResp 957 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 221000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1030868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 68894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1101676 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160435 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995417 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8741760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9897612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2820864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12722304 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32756791 # Total data (bytes) +system.membus.snoop_data_through_bus 332608 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 164980499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315210000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315323500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1784000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1914000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 830204748 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 859913497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 892000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1595294481 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1658568572 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 252511249 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 223775499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103855 # number of replacements -system.l2c.tags.tagsinuse 64822.347448 # Cycle average of tags in use -system.l2c.tags.total_refs 3646219 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167877 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.719586 # Average number of references to valid blocks. +system.l2c.tags.replacements 103968 # number of replacements +system.l2c.tags.tagsinuse 64819.095791 # Cycle average of tags in use +system.l2c.tags.total_refs 3669692 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168243 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.811855 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51292.264352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1278.615227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4499.945934 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 292.458405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1505.357985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.212632 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1370.507166 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4576.860668 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782658 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51211.809516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1304.363790 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4492.907273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 251.742289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1518.622796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.780510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.958868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1352.233300 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4674.555536 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.781430 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068664 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004463 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020912 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.069837 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989111 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 19693 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10326 # number of ReadReq hits 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+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63006.996081 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62486.765295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62439.186047 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59468.858606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 72875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70759.386383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63006.996081 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62486.765295 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -849,39 +846,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.094274 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.092731 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000200819009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094274 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005892 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000213887009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092731 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005796 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005796 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129801048 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129801048 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6845673540 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6845673540 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6975474588 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6975474588 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6975474588 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6975474588 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135882017 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135882017 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5955673280 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5955673280 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6091555297 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6091555297 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6091555297 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6091555297 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -890,56 +887,56 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142638.514286 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 142638.514286 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 146525.546661 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 146525.546661 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 146451.282553 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 146451.282553 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 105453 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 149485.167217 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 149485.167217 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 127475.883562 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 127475.883562 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 127895.930987 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127895.930987 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 91729 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6453 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5124 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.341702 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 17.901835 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 724 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 27280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 27280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 28004 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 28004 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 28004 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 28004 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92126548 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92126548 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5426189542 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5518316090 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5518316090 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5518316090 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.795604 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.583904 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.587949 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.587949 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.587949 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127246.613260 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127246.613260 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 198907.241276 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 198907.241276 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 197054.566848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 197054.566848 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 754 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 754 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24064 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 24064 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 24818 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 24818 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 24818 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 24818 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96648017 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96648017 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4703544282 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4800192299 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4800192299 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4800192299 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.829483 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.515068 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.521069 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.521069 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.521069 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 128180.393899 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128180.393899 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195459.785655 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 195459.785655 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 193415.758683 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -953,459 +950,458 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52188015 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1787129 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1786595 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6474 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6474 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 905502 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 665 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 665 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 176137 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 148862 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 991248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3625702 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34347 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 125379 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4776676 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31718784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120252184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 463592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152554720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268001344 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 137632 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5049278590 # Layer occupancy (ticks) +system.toL2Bus.throughput 52370833 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1836862 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1836332 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 7056 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 7056 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 922959 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 811 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 181042 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 156978 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1050040 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3684115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 38115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 140219 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4912489 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 33600320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 122621708 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 135720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 527336 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 156885084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268925359 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 127504 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5157428290 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 882000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1008000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2232669307 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2365130940 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4714355905 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4803653283 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19343965 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 21171206 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 67521559 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 74417261 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276093 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 150466 # Transaction distribution -system.iobus.trans_dist::ReadResp 150466 # Transaction distribution -system.iobus.trans_dist::WriteReq 32862 # Transaction distribution -system.iobus.trans_dist::WriteResp 32862 # Transaction distribution -system.iobus.trans_dist::MessageReq 892 # Transaction distribution -system.iobus.trans_dist::MessageResp 892 # Transaction distribution +system.iobus.throughput 1276721 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150736 # Transaction distribution +system.iobus.trans_dist::ReadResp 150736 # Transaction distribution +system.iobus.trans_dist::WriteReq 30161 # Transaction distribution +system.iobus.trans_dist::WriteResp 30161 # Transaction distribution +system.iobus.trans_dist::MessageReq 957 # Transaction distribution +system.iobus.trans_dist::MessageResp 957 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 580 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15082 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 310648 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 56008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1784 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 368440 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49636 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 363708 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3380 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 17 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143595 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7541 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 159467 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1782176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1945211 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6556491 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2113460 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 160435 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1576592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1740855 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6559098 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2255722 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3772000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4948000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143596000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143539000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 394000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 458000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11170000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11248000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 248070339 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 218954798 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 305066000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306061000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 32957751 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 29747501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 892000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 957000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1184263733 # number of cpu cycles simulated +system.cpu0.numCycles 1152461068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72124506 # Number of instructions committed -system.cpu0.committedOps 146682326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134713165 # Number of integer alu accesses +system.cpu0.committedInsts 71542662 # Number of instructions committed +system.cpu0.committedOps 145644721 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133686522 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 981373 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14229217 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134713165 # number of integer instructions +system.cpu0.num_func_calls 963574 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14130614 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133686522 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247622256 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115606613 # number of times the integer registers were written +system.cpu0.num_int_register_reads 245609809 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114802156 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83816060 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55907358 # number of times the CC registers were written -system.cpu0.num_mem_refs 14049102 # number of memory refs -system.cpu0.num_load_insts 10253492 # Number of load instructions -system.cpu0.num_store_insts 3795610 # Number of store instructions -system.cpu0.num_idle_cycles 1123870108.492543 # Number of idle cycles -system.cpu0.num_busy_cycles 60393624.507457 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050997 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949003 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83145706 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55494396 # number of times the CC registers were written +system.cpu0.num_mem_refs 13834339 # number of memory refs +system.cpu0.num_load_insts 10142209 # Number of load instructions +system.cpu0.num_store_insts 3692130 # Number of store instructions +system.cpu0.num_idle_cycles 1095316733.110107 # Number of idle cycles +system.cpu0.num_busy_cycles 57144334.889893 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049585 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950415 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 848510 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.789516 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129618382 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 849022 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 152.667872 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147463418500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 302.993641 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 130.368033 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 77.427843 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.591784 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.254625 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.151226 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997636 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 87771297 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39145197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2701888 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129618382 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87771297 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39145197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2701888 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129618382 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87771297 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39145197 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2701888 # number of overall hits -system.cpu0.icache.overall_hits::total 129618382 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 353389 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 157925 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 356099 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 867413 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 353389 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 157925 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 356099 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 867413 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 353389 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 157925 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 356099 # number of overall misses -system.cpu0.icache.overall_misses::total 867413 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2216316250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5093590204 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7309906454 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2216316250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5093590204 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7309906454 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2216316250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5093590204 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7309906454 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 88124686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39303122 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3057987 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130485795 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 88124686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39303122 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3057987 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130485795 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 88124686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39303122 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3057987 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130485795 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004010 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004018 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116449 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006648 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004010 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004018 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116449 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006648 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004010 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004018 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116449 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006648 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14033.979737 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14303.859893 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8427.250288 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14033.979737 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14303.859893 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8427.250288 # average overall miss latency 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latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17108.474048 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16811.111790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16900.837037 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1544272 # number of writebacks +system.cpu0.dcache.writebacks::total 1544272 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 375629 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 375629 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17363 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 392992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 392992 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 392992 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 227972 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 589816 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 817788 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 58525 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99219 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 157744 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 286497 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 689035 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 975532 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 286497 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 689035 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 975532 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2789367492 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8524003053 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11313370545 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2071430220 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3281431451 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5352861671 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4860797712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11805434504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16666232216 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4860797712 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11805434504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16666232216 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30612926500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63859429000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 519657500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 815190500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1334848000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31132584000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34061693000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65194277000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084932 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.117207 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061741 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034718 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032833 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018787 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.045076 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065561 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085550 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045076 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12235.570561 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14451.969857 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13834.111707 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35393.937975 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33072.611607 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33933.852768 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16966.312778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17133.287139 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17084.249636 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1416,306 +1412,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606010326 # number of cpu cycles simulated +system.cpu1.numCycles 2606011326 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35502902 # Number of instructions committed -system.cpu1.committedOps 69019443 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64128875 # Number of integer alu accesses +system.cpu1.committedInsts 35164948 # Number of instructions committed +system.cpu1.committedOps 68413270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63529188 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 466888 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6511590 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64128875 # number of integer instructions +system.cpu1.num_func_calls 457891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6471423 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63529188 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 118555351 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55341107 # number of times the integer registers were written +system.cpu1.num_int_register_reads 117257194 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54850904 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36337345 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27074895 # number of times the CC registers were written -system.cpu1.num_mem_refs 4724906 # number of memory refs -system.cpu1.num_load_insts 2973846 # Number of load instructions -system.cpu1.num_store_insts 1751060 # Number of store instructions -system.cpu1.num_idle_cycles 2477242501.972853 # Number of idle cycles -system.cpu1.num_busy_cycles 128767824.027147 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049412 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950588 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36014934 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26882843 # number of times the CC registers were written +system.cpu1.num_mem_refs 4560424 # number of memory refs +system.cpu1.num_load_insts 2872895 # Number of load instructions +system.cpu1.num_store_insts 1687529 # Number of store instructions +system.cpu1.num_idle_cycles 2475874291.383945 # Number of idle cycles +system.cpu1.num_busy_cycles 130137034.616055 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049937 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950063 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28668505 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28668505 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 293936 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26313496 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25716329 # Number of BTB hits +system.cpu2.branchPred.lookups 29049356 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29049356 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 330189 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26516680 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25920061 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.730568 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 531231 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 59742 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154176343 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.750024 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 553809 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 66194 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157465018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9183670 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141279801 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28668505 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26247560 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54165747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1372429 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 60595 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24017130 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 2633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7414 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 19025 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3057990 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 134510 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1720 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.147296 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.411069 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10014190 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143120520 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29049356 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26473870 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54776048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1540394 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 78659 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 25463388 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3574 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6100 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 25165 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3264432 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 152504 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2125 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.080398 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.405930 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34483261 38.96% 38.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 569039 0.64% 39.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23712203 26.79% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 303942 0.34% 66.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 596203 0.67% 67.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 791828 0.89% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 321684 0.36% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 518300 0.59% 69.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27224128 30.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 36927513 40.33% 40.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 611138 0.67% 41.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23812381 26.01% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 328703 0.36% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 619714 0.68% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 832275 0.91% 68.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 355282 0.39% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 540716 0.59% 69.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27533111 30.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 88520588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185946 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.916352 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10629848 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 22917593 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 30946726 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1286674 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1067388 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 277843876 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 5 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1067388 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11607450 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13707721 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4125990 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 31086433 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5253313 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 276918591 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6816 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2458805 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2129053 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 330941436 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 602250525 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 370032440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321416172 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9525262 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 139074 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 139963 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11350220 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6069912 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3334552 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 325084 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 284462 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275324678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 401766 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273874447 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 58026 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6719880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10332541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 51920 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 88520588 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.093907 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.392477 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 91560833 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184481 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.908904 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 11521398 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 24357574 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 32837645 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1316376 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1196608 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 281192085 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 11 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1196608 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12539536 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14626708 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4503596 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 32964525 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5398696 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280154725 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 7234 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2491982 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2219031 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 334708153 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 610319016 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 374834819 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 324049688 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10658465 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 153621 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 154561 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11685330 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6409686 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3556417 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 350066 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 288206 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 278401976 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 420214 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 276663998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 65469 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7519016 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11586940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 57670 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 91560833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.021641 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.405034 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 25429283 28.73% 28.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6033030 6.82% 35.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3870306 4.37% 39.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2690716 3.04% 42.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25010151 28.25% 71.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1323131 1.49% 72.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23827077 26.92% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 285216 0.32% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 51678 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 27548029 30.09% 30.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6302445 6.88% 36.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 4040687 4.41% 41.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2809709 3.07% 44.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25166051 27.49% 71.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1389542 1.52% 73.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23947180 26.15% 99.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 301462 0.33% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 55728 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 88520588 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 91560833 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 120453 33.21% 33.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 124 0.03% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 190037 52.39% 85.63% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 52134 14.37% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 136321 35.17% 35.17% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 124 0.03% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 194124 50.09% 85.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 56993 14.71% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 69880 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264196051 96.47% 96.49% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 53857 0.02% 96.51% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 45427 0.02% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.53% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6378380 2.33% 98.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3130852 1.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 81905 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 266468718 96.31% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56660 0.02% 96.37% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48242 0.02% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6674536 2.41% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3333937 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273874447 # Type of FU issued -system.cpu2.iq.rate 1.776371 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 362748 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001325 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 636728050 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282449613 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272560977 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 75 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 276663998 # Type of FU issued +system.cpu2.iq.rate 1.756987 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387562 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 645385259 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 286345237 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275267423 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 106 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274167280 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 35 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 638144 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 276969613 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 42 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 657734 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 933920 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7005 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3826 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 481474 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1052819 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4672 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 529632 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656274 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10618 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656268 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10631 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9024497 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 812904 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275726444 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 67814 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6069912 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3334552 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 224273 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 631637 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3885 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3826 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 167894 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164610 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 332504 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273407129 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6276348 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 467317 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1196608 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9811775 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 820688 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 278822190 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 75669 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6409704 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3556417 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 239796 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 634227 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4101 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4672 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184871 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 190702 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 375573 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276137017 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6556879 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 526981 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9343774 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27815177 # Number of branches executed -system.cpu2.iew.exec_stores 3067426 # Number of stores executed -system.cpu2.iew.exec_rate 1.773340 # Inst execution rate -system.cpu2.iew.wb_sent 273265355 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272560999 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212629872 # num instructions producing a value -system.cpu2.iew.wb_consumers 347702126 # num instructions consuming a value +system.cpu2.iew.exec_refs 9821909 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28090459 # Number of branches executed +system.cpu2.iew.exec_stores 3265030 # Number of stores executed +system.cpu2.iew.exec_rate 1.753640 # Inst execution rate +system.cpu2.iew.wb_sent 275979435 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275267445 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 214496489 # num instructions producing a value +system.cpu2.iew.wb_consumers 350700107 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.767852 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611529 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.748118 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611624 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7002811 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 349846 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 295934 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 87453200 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.072767 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870996 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7834345 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 362544 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 332977 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 90364225 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 2.998816 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.871519 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30168588 34.50% 34.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4310788 4.93% 39.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1198483 1.37% 40.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24616834 28.15% 68.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 847666 0.97% 69.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 576601 0.66% 70.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 339942 0.39% 70.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302626 26.65% 97.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2091672 2.39% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 32381210 35.83% 35.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4545159 5.03% 40.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1281676 1.42% 42.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24783522 27.43% 69.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 890698 0.99% 70.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 597656 0.66% 71.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 358639 0.40% 71.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23381642 25.87% 97.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2144023 2.37% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 87453200 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136077774 # Number of instructions committed -system.cpu2.commit.committedOps 268723335 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 90364225 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137308621 # Number of instructions committed +system.cpu2.commit.committedOps 270985661 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7989069 # Number of memory references committed -system.cpu2.commit.loads 5135991 # Number of loads committed -system.cpu2.commit.membars 163538 # Number of memory barriers committed -system.cpu2.commit.branches 27499066 # Number of branches committed +system.cpu2.commit.refs 8383670 # Number of memory references committed +system.cpu2.commit.loads 5356885 # Number of loads committed +system.cpu2.commit.membars 165489 # Number of memory barriers committed +system.cpu2.commit.branches 27738642 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245318960 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428759 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2091672 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 247503684 # Number of committed integer instructions. +system.cpu2.commit.function_calls 442390 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2144023 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 361063162 # The number of ROB reads -system.cpu2.rob.rob_writes 552523197 # The number of ROB writes -system.cpu2.timesIdled 466136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65655755 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909695924 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136077774 # Number of Instructions Simulated -system.cpu2.committedOps 268723335 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136077774 # Number of Instructions Simulated -system.cpu2.cpi 1.133002 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.133002 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882611 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882611 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363659019 # number of integer regfile reads -system.cpu2.int_regfile_writes 218348978 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads +system.cpu2.rob.rob_reads 367011505 # The number of ROB reads +system.cpu2.rob.rob_writes 558841004 # The number of ROB writes +system.cpu2.timesIdled 481956 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65904185 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4905068069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137308621 # Number of Instructions Simulated +system.cpu2.committedOps 270985661 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 137308621 # Number of Instructions Simulated +system.cpu2.cpi 1.146796 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.146796 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.871994 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.871994 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 367544012 # number of integer regfile reads +system.cpu2.int_regfile_writes 220503659 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72990 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138971726 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107072573 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88484504 # number of misc regfile reads -system.cpu2.misc_regfile_writes 124462 # number of misc regfile writes +system.cpu2.cc_regfile_reads 140406201 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108013944 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89640596 # number of misc regfile reads +system.cpu2.misc_regfile_writes 136839 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |