diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
3 files changed, 3341 insertions, 2298 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 8f4e7d03c..369e97796 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.140938 # Number of seconds simulated -sim_ticks 5140937585000 # Number of ticks simulated -final_tick 5140937585000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125717 # Number of seconds simulated +sim_ticks 5125716951000 # Number of ticks simulated +final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121697 # Simulator instruction rate (inst/s) -host_op_rate 240559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1534230705 # Simulator tick rate (ticks/s) -host_mem_usage 773616 # Number of bytes of host memory used -host_seconds 3350.82 # Real time elapsed on the host -sim_insts 407786881 # Number of instructions simulated -sim_ops 806071515 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2479872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory +host_inst_rate 203249 # Simulator instruction rate (inst/s) +host_op_rate 401765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2555120499 # Simulator tick rate (ticks/s) +host_mem_usage 728844 # Number of bytes of host memory used +host_seconds 2006.06 # Real time elapsed on the host +sim_insts 407728401 # Number of instructions simulated +sim_ops 805963181 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1026240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10765120 # Number of bytes read from this memory -system.physmem.bytes_read::total 14275328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1026240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1026240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9536256 # Number of bytes written to this memory -system.physmem.bytes_written::total 9536256 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory +system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory +system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168205 # Number of read requests responded to by this memory -system.physmem.num_reads::total 223052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149004 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149004 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 199621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2093999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2776795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1854964 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1854964 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1854964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2093999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4631759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 223052 # Total number of read requests seen -system.physmem.writeReqs 149004 # Total number of write requests seen -system.physmem.cpureqs 373790 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14275328 # Total number of bytes read from memory -system.physmem.bytesWritten 9536256 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14275328 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9536256 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q +system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222005 # Total number of read requests seen +system.physmem.writeReqs 148125 # Total number of write requests seen +system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14208320 # Total number of bytes read from memory +system.physmem.bytesWritten 9480000 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13124 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13111 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15809 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11661 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8790 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8601 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8761 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 5140937531500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 5125716897500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 223052 # Categorize read packet sizes +system.physmem.readPktSize::6 222005 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149004 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 172997 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 18175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148125 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -136,92 +136,347 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 4794975750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9301923250 # Sum of mem lat for all requests -system.physmem.totBusLat 1114905000 # Total cycles spent in databus access -system.physmem.totBankLat 3392042500 # Total cycles spent in bank access -system.physmem.avgQLat 21503.97 # Average queueing delay per request -system.physmem.avgBankLat 15212.25 # Average bank access latency per request +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation +system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests +system.physmem.totBusLat 1109565000 # Total cycles spent in databus access +system.physmem.totBankLat 3154263750 # Total cycles spent in bank access +system.physmem.avgQLat 18030.39 # Average queueing delay per request +system.physmem.avgBankLat 14213.97 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41716.21 # Average memory access latency -system.physmem.avgRdBW 2.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 37244.35 # Average memory access latency +system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 15.58 # Average write queue length over time -system.physmem.readRowHits 191257 # Number of row buffer hits during reads -system.physmem.writeRowHits 105612 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.88 # Row buffer hit rate for writes -system.physmem.avgGap 13817644.47 # Average gap between requests -system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.128763 # Cycle average of tags in use +system.physmem.avgWrQLen 11.40 # Average write queue length over time +system.physmem.readRowHits 198637 # Number of row buffer hits during reads +system.physmem.writeRowHits 108987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes +system.physmem.avgGap 13848423.25 # Average gap between requests +system.membus.throughput 5098961 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662131 # Transaction distribution +system.membus.trans_dist::ReadResp 662131 # Transaction distribution +system.membus.trans_dist::WriteReq 13694 # Transaction distribution +system.membus.trans_dist::WriteResp 13694 # Transaction distribution +system.membus.trans_dist::Writeback 148125 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution +system.membus.trans_dist::ReadExReq 179249 # Transaction distribution +system.membus.trans_dist::ReadExResp 179246 # Transaction distribution +system.membus.trans_dist::MessageReq 1640 # Transaction distribution +system.membus.trans_dist::MessageResp 1640 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25486679 # Total data (bytes) +system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.079131 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991974997000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.128763 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.008048 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.008048 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses -system.iocache.demand_misses::total 47631 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses -system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147497397 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 147497397 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10072244306 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10072244306 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10219741703 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10219741703 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10219741703 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10219741703 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +485,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 161907.131723 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 215587.420933 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214560.721022 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214560.721022 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 139153 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12645 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.004587 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100104427 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100104427 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7641446543 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7641446543 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7741550970 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7741550970 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,14 +527,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -293,144 +548,286 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 85620726 # Number of BP lookups -system.cpu.branchPred.condPredicted 85620726 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 882198 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79268619 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77534559 # Number of BTB hits +system.iobus.throughput 639145 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225496 # Transaction distribution +system.iobus.trans_dist::ReadResp 225496 # Transaction distribution +system.iobus.trans_dist::WriteReq 57527 # Transaction distribution +system.iobus.trans_dist::WriteResp 57527 # Transaction distribution +system.iobus.trans_dist::MessageReq 1640 # Transaction distribution +system.iobus.trans_dist::MessageResp 1640 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276074 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 85601186 # Number of BP lookups +system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.812426 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1442315 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180251 # Number of incorrect RAS predictions. -system.cpu.numCycles 447791761 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions. +system.cpu.numCycles 453375451 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25559948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422856490 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85620726 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78976874 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162677741 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4000997 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 98298 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 65919320 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86507 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 459 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8492083 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 383635 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2345 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257461374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.243647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.415529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95198026 36.98% 36.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1534816 0.60% 37.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71825104 27.90% 65.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 895357 0.35% 65.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1570607 0.61% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2391332 0.93% 67.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1020158 0.40% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1325162 0.51% 68.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81700812 31.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257461374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.191207 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.944315 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29461192 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63064302 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158550724 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3309649 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3075507 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832761340 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 863 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3075507 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32153278 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38465118 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12079112 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158824437 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12863922 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829829025 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19879 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6055166 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4924546 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11525 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 991492877 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800847756 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1800847292 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963999366 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27493506 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 456551 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 462682 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29304477 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16752339 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9837983 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1099709 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 928773 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825036488 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1186686 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 821069910 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 146070 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19309743 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29357166 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 131932 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257461374 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.189099 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.383585 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71259249 27.68% 27.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15575755 6.05% 33.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10479111 4.07% 37.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7383615 2.87% 40.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75752504 29.42% 70.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3772068 1.47% 71.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72307575 28.08% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 782694 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 148803 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257461374 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 356313 33.63% 33.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 2452 0.23% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547502 51.68% 85.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152922 14.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308526 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793557907 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150412 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124298 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -457,246 +854,280 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17694567 2.16% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9234200 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 821069910 # Type of FU issued -system.cpu.iq.rate 1.833598 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1059430 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1900915279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845543458 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817157785 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821820724 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1686147 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued +system.cpu.iq.rate 1.810787 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2748440 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11930 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1411969 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931504 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11624 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3075507 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26873503 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2150322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826223174 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241070 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16752339 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9837983 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 692103 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1621529 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12267 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11930 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 498132 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506603 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1004735 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819660888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17391685 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1409021 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26440023 # number of memory reference insts executed -system.cpu.iew.exec_branches 83107253 # Number of branches executed -system.cpu.iew.exec_stores 9048338 # Number of stores executed -system.cpu.iew.exec_rate 1.830451 # Inst execution rate -system.cpu.iew.wb_sent 819258374 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817157837 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638799704 # num instructions producing a value -system.cpu.iew.wb_consumers 1044337102 # num instructions consuming a value +system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed +system.cpu.iew.exec_branches 83095032 # Number of branches executed +system.cpu.iew.exec_stores 9034738 # Number of stores executed +system.cpu.iew.exec_rate 1.807683 # Inst execution rate +system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638600685 # num instructions producing a value +system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.824861 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611680 # average fanout of values written-back +system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 20042352 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054753 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 891546 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254385866 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.168696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.858566 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82972146 32.62% 32.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11724447 4.61% 37.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3813249 1.50% 38.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74747378 29.38% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2384925 0.94% 69.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1476326 0.58% 69.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865615 0.34% 69.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70850824 27.85% 97.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5550956 2.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254385866 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407786881 # Number of instructions committed -system.cpu.commit.committedOps 806071515 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407728401 # Number of instructions committed +system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22429911 # Number of memory references committed -system.cpu.commit.loads 14003897 # Number of loads committed -system.cpu.commit.membars 474463 # Number of memory barriers committed -system.cpu.commit.branches 82163817 # Number of branches committed +system.cpu.commit.refs 22399743 # Number of memory references committed +system.cpu.commit.loads 13982748 # Number of loads committed +system.cpu.commit.membars 474399 # Number of memory barriers committed +system.cpu.commit.branches 82153759 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735061477 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156045 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5550956 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734952654 # Number of committed integer instructions. +system.cpu.commit.function_calls 1154691 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1074870508 # The number of ROB reads -system.cpu.rob.rob_writes 1655318425 # The number of ROB writes -system.cpu.timesIdled 1256763 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190330387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9834088814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407786881 # Number of Instructions Simulated -system.cpu.committedOps 806071515 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407786881 # Number of Instructions Simulated -system.cpu.cpi 1.098102 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098102 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910662 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910662 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1504614065 # number of integer regfile reads -system.cpu.int_regfile_writes 975429838 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 264130300 # number of misc regfile reads -system.cpu.misc_regfile_writes 403010 # number of misc regfile writes -system.cpu.icache.replacements 955437 # number of replacements -system.cpu.icache.tagsinuse 509.903328 # Cycle average of tags in use -system.cpu.icache.total_refs 7482159 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 955949 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.826944 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 146514700000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.903328 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995905 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995905 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7482159 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7482159 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7482159 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7482159 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7482159 # number of overall hits -system.cpu.icache.overall_hits::total 7482159 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1009922 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1009922 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1009922 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1009922 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1009922 # number of overall misses -system.cpu.icache.overall_misses::total 1009922 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13938284992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13938284992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13938284992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13938284992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13938284992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13938284992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8492081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8492081 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8492081 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8492081 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8492081 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8492081 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118925 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118925 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118925 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118925 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118925 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118925 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13801.348017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13801.348017 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8199 # number of cycles access was blocked +system.cpu.rob.rob_reads 1079657633 # The number of ROB reads +system.cpu.rob.rob_writes 1655096826 # The number of ROB writes +system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407728401 # Number of Instructions Simulated +system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated +system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads +system.cpu.int_regfile_writes 975319683 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads +system.cpu.misc_regfile_writes 401987 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 953322 # number of replacements +system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use +system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits +system.cpu.icache.overall_hits::total 7473092 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses +system.cpu.icache.overall_misses::total 1006614 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.389163 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53908 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53908 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53908 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53908 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53908 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53908 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956014 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 956014 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 956014 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 956014 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 956014 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 956014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11502740492 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11502740492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11502740492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11502740492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11502740492 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11502740492 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112577 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112577 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112577 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 7960 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.326712 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 20386 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 7973 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.556879 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5107329698000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.326712 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.395420 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.395420 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20403 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 20403 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 7857 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20405 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 20405 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20405 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 20405 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8843 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 8843 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8843 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 8843 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8843 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 8843 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 96821500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 96821500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 96821500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 96821500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 96821500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 96821500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29246 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 29246 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29248 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 29248 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29248 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 29248 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.302366 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.302366 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.302345 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.302345 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.302345 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.302345 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10948.942667 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10948.942667 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +1136,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1394 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1394 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8843 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8843 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8843 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8843 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8843 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79135500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 79135500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 79135500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 79135500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 79135500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 79135500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.302366 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.302366 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.302345 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.302345 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8948.942667 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 67560 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 14.837353 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 92239 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 67575 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.364987 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100574572500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.837353 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.927335 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.927335 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92240 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92240 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92240 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92240 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92240 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92240 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68644 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68644 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68644 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68644 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68644 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68644 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 852599000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 852599000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 852599000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 852599000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 852599000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 852599000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160884 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 160884 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160884 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 160884 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160884 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 160884 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426668 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426668 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426668 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426668 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426668 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426668 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 67431 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +1216,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 19876 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 19876 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68644 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68644 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68644 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68644 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68644 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68644 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 715311000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 715311000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 715311000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 715311000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 715311000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 715311000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426668 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426668 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426668 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31946998000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31946998000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9622210995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9622210995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41569208995 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41569208995 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41569208995 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41569208995 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13156849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13156849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8416527 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8416527 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21573376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21573376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21573376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21573376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037437 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037437 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118418 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118418 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118418 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118418 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14264.733684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14264.733684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30537.782600 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30537.782600 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16271.844396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16271.844396 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 387071 # number of cycles access was blocked +system.cpu.dcache.replacements 1656381 # number of replacements +system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use +system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8091896 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33108471000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12021128996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12021128996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45129599996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42390 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.131187 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1557214 # number of writebacks -system.cpu.dcache.writebacks::total 1557214 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 870911 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 870911 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16050 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168662 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 184779 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5260750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1193323263 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545977303 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3744991316 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15894959 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15894959 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7671814321 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7671814321 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5260750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1193323263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10217791624 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11416805637 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5260750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1193323263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10217791624 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11416805637 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236814500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236814500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356578000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356578000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593392500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593392500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823791 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823791 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461819 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461819 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068927 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068927 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74350.359065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70971.965071 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72032.916253 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10725.343455 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10725.343455 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57774.471688 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57774.471688 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index f3136422c..11c0ff3fa 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.205149 # Number of seconds simulated -sim_ticks 5205148879000 # Number of ticks simulated -final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5205149326500 # Number of ticks simulated +final_tick 5205149326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131600 # Simulator instruction rate (inst/s) -host_op_rate 252290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6421585329 # Simulator tick rate (ticks/s) -host_mem_usage 872300 # Number of bytes of host memory used -host_seconds 810.57 # Real time elapsed on the host -sim_insts 106671342 # Number of instructions simulated -sim_ops 204498751 # Number of ops (including micro ops) simulated +host_inst_rate 156279 # Simulator instruction rate (inst/s) +host_op_rate 299599 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7625516175 # Simulator tick rate (ticks/s) +host_mem_usage 825184 # Number of bytes of host memory used +host_seconds 682.60 # Real time elapsed on the host +sim_insts 106675228 # Number of instructions simulated +sim_ops 204505420 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 160408 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 562944184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 41978278 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 62896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 563007384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41989554 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 62960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 30152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448071240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 51341424 # Number of bytes read from this memory -system.physmem.bytes_read::total 1104699086 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 562944184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448071240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1011015424 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448053480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 51339228 # Number of bytes read from this memory +system.physmem.bytes_read::total 1104753734 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 563007384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448053480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1011060864 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 33612947 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 34199698 # Number of bytes written to this memory -system.physmem.bytes_written::total 70803765 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 33620576 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 34199208 # Number of bytes written to this memory +system.physmem.bytes_written::total 70810904 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 821 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 20043 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 20051 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 9416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 70368023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6999506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 7862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 70375923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 7001118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7870 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 3769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56008905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8662168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142080513 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56006685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8661478 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142087131 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 5025316 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4781707 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9853761 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 5026389 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4781632 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9854759 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 6770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 30805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 30817 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 14472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 108151409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 8064760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 12083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 108163541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 8066926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 12096 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 5793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 86082310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 9863584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 212231986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 108151409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 86082310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 194233719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 86078891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 9863161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 212242467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 108163541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 86078891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 194242432 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574643 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6457634 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6570359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13602640 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 30805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6459099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6570265 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13604010 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 30817 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 14475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 108151409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 14522394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 12083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 108163541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 14526025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 12096 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 5793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 86082310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16433943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 225834626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 86078891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16433426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 225846477 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 821 # Total number of read requests seen system.physmem.writeReqs 46736 # Total number of write requests seen -system.physmem.cpureqs 47279 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 47259 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 52544 # Total number of bytes read from memory system.physmem.bytesWritten 2991104 # Total number of bytes written to memory system.physmem.bytesConsumedRd 35240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 3024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2896 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 2816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2640 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3064 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2648 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 3312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 3024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2672 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 3008 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 31 # Number of times wr buffer was full causing retry -system.physmem.totGap 64277169000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry +system.physmem.totGap 64277565999 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -162,15 +162,15 @@ system.physmem.rdQLenPdf::28 2 # Wh system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2021 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see @@ -185,23 +185,66 @@ system.physmem.wrQLenPdf::19 2032 # Wh system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see -system.physmem.totQLat 41690522 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 53523022 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::23 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5552.207792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3362.695639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3316.858883 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 30 5.57% 5.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 2 0.37% 5.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 6 1.11% 7.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 9 1.67% 8.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2 0.37% 9.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 3 0.56% 9.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1 0.19% 9.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1 0.19% 10.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1 0.19% 10.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2 0.37% 10.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2 0.37% 10.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1 0.19% 11.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.37% 11.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1 0.19% 11.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 2 0.37% 12.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 69 12.80% 24.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.19% 25.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.56% 25.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.37% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.37% 26.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.19% 26.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.19% 26.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.19% 26.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 11 2.04% 28.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.19% 29.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 9 1.67% 30.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.19% 30.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.19% 31.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.19% 31.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 41 7.61% 38.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 1.11% 40.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.19% 40.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 4 0.74% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.19% 41.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 5 0.93% 42.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.19% 42.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 1 0.19% 42.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 310 57.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 539 # Bytes accessed per row activation +system.physmem.totQLat 47710768 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 58058268 # Sum of mem lat for all requests system.physmem.totBusLat 4105000 # Total cycles spent in databus access -system.physmem.totBankLat 7727500 # Total cycles spent in bank access -system.physmem.avgQLat 50780.17 # Average queueing delay per request -system.physmem.avgBankLat 9412.30 # Average bank access latency per request +system.physmem.totBankLat 6242500 # Total cycles spent in bank access +system.physmem.avgQLat 58112.99 # Average queueing delay per request +system.physmem.avgBankLat 7603.53 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 65192.48 # Average memory access latency +system.physmem.avgMemAccLat 70716.53 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s @@ -210,11 +253,207 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.15 # Average write queue length over time -system.physmem.readRowHits 704 # Number of row buffer hits during reads -system.physmem.writeRowHits 45223 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes -system.physmem.avgGap 1351581.66 # Average gap between requests +system.physmem.readRowHits 756 # Number of row buffer hits during reads +system.physmem.writeRowHits 46262 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.99 # Row buffer hit rate for writes +system.physmem.avgGap 1351590.01 # Average gap between requests +system.piobus.throughput 974238 # Throughput (bytes/s) +system.piobus.trans_dist::ReadReq 863748 # Transaction distribution +system.piobus.trans_dist::ReadResp 863748 # Transaction distribution +system.piobus.trans_dist::WriteReq 83560 # Transaction distribution +system.piobus.trans_dist::WriteResp 83560 # Transaction distribution +system.piobus.trans_dist::MessageReq 1915 # Transaction distribution +system.piobus.trans_dist::MessageResp 1915 # Transaction distribution +system.piobus.pkt_count_system.pc.south_bridge.ide.dma::system.physmem.port 95114 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1680 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1624 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 6496 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 732 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 90 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1000 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 15614 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1714112 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 4730 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 632 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 4 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 31770 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 328 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 31858 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 10796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 85390 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 330 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 330 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 196 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 196 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.physmem.port 95114 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11226 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.pit.pio 31800 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1328 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.i_dont_exist.pio 31948 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.com_1.pio 26410 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu0.interrupts.int_slave 1876 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.cpu1.interrupts.int_slave 1954 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 1898446 # Packet count per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026344 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3360 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3248 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 3698 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 366 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2000 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 7807 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1985488 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3066 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 316 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 15885 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 656 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 15929 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 5398 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 51561 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 660 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 660 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 392 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 392 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6764 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15900 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2656 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 15974 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.com_1.pio 13205 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 3752 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 3908 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.piobus.tot_pkt_size::total 5071053 # Cumulative packet size per connected master and slave (bytes) +system.piobus.data_through_bus 5071053 # Total data (bytes) +system.piobus.reqLayer0.occupancy 421750668 # Layer occupancy (ticks) +system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer1.occupancy 46000 # Layer occupancy (ticks) +system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) +system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer3.occupancy 10348000 # Layer occupancy (ticks) +system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks) +system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer5.occupancy 1063000 # Layer occupancy (ticks) +system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer6.occupancy 95500 # Layer occupancy (ticks) +system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer7.occupancy 56000 # Layer occupancy (ticks) +system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer8.occupancy 21210500 # Layer occupancy (ticks) +system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer9.occupancy 586857500 # Layer occupancy (ticks) +system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer10.occupancy 1290500 # Layer occupancy (ticks) +system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer11.occupancy 39914000 # Layer occupancy (ticks) +system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) +system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer13.occupancy 23057500 # Layer occupancy (ticks) +system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) +system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer18.occupancy 470748000 # Layer occupancy (ticks) +system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer19.occupancy 2244320 # Layer occupancy (ticks) +system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer20.occupancy 5358000 # Layer occupancy (ticks) +system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer21.occupancy 2333580 # Layer occupancy (ticks) +system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.piobus.reqLayer22.occupancy 1074500 # Layer occupancy (ticks) +system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer0.occupancy 52258179 # Layer occupancy (ticks) +system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer1.occupancy 2331400 # Layer occupancy (ticks) +system.piobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer2.occupancy 1919239500 # Layer occupancy (ticks) +system.piobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer3.occupancy 68175500 # Layer occupancy (ticks) +system.piobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer4.occupancy 210500 # Layer occupancy (ticks) +system.piobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer5.occupancy 121000 # Layer occupancy (ticks) +system.piobus.respLayer5.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -227,12 +466,12 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11503621 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 550662 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12054283 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 70015833 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 352190 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 70368023 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11506236 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 550740 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12056976 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 70023521 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 352402 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 70375923 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -242,12 +481,12 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12163827 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291679 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13455506 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 55549058 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 459847 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 56008905 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12162992 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291757 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13454749 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 55546818 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 459867 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 56006685 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -257,55 +496,55 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l2_cntrl0.L2cache.demand_hits 2426575 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227803 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2654378 # Number of cache demand accesses -system.cpu0.numCycles 10410297758 # number of cpu cycles simulated +system.ruby.l2_cntrl0.L2cache.demand_hits 2426890 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 227876 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2654766 # Number of cache demand accesses +system.cpu0.numCycles 10410298653 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 60288276 # Number of instructions committed -system.cpu0.committedOps 115773079 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses +system.cpu0.committedInsts 60294243 # Number of instructions committed +system.cpu0.committedOps 115784968 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108743289 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1065656 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108731496 # number of integer instructions +system.cpu0.num_func_calls 1066196 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 10278204 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108743289 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 267473663 # number of times the integer registers were read -system.cpu0.num_int_register_writes 137108635 # number of times the integer registers were written +system.cpu0.num_int_register_reads 267504308 # number of times the integer registers were read +system.cpu0.num_int_register_writes 137121782 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 12880520 # number of memory refs -system.cpu0.num_load_insts 7843945 # Number of load instructions -system.cpu0.num_store_insts 5036575 # Number of store instructions -system.cpu0.num_idle_cycles 9879714305.974102 # Number of idle cycles -system.cpu0.num_busy_cycles 530583452.025898 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050967 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949033 # Percentage of idle cycles +system.cpu0.num_mem_refs 12883291 # number of memory refs +system.cpu0.num_load_insts 7845612 # Number of load instructions +system.cpu0.num_store_insts 5037679 # Number of store instructions +system.cpu0.num_idle_cycles 9879654975.894102 # Number of idle cycles +system.cpu0.num_busy_cycles 530643677.105898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050973 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949027 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10407399002 # number of cpu cycles simulated +system.cpu1.numCycles 10407399919 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 46383066 # Number of instructions committed -system.cpu1.committedOps 88725672 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses +system.cpu1.committedInsts 46380985 # Number of instructions committed +system.cpu1.committedOps 88720452 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 85213748 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1670749 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls -system.cpu1.num_int_insts 85218419 # number of integer instructions +system.cpu1.num_func_calls 1670555 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7954622 # number of instructions that are conditional controls +system.cpu1.num_int_insts 85213748 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 213998429 # number of times the integer registers were read -system.cpu1.num_int_register_writes 102139748 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213988355 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102135039 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 13480502 # number of memory refs -system.cpu1.num_load_insts 8673583 # Number of load instructions -system.cpu1.num_store_insts 4806919 # Number of store instructions -system.cpu1.num_idle_cycles 10081113907.619320 # Number of idle cycles -system.cpu1.num_busy_cycles 326285094.380681 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031351 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968649 # Percentage of idle cycles +system.cpu1.num_mem_refs 13479662 # number of memory refs +system.cpu1.num_load_insts 8672840 # Number of load instructions +system.cpu1.num_store_insts 4806822 # Number of store instructions +system.cpu1.num_idle_cycles 10081140022.903200 # Number of idle cycles +system.cpu1.num_busy_cycles 326259896.096799 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031349 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968651 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index a3f0789f4..88911e3ab 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,150 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.139557 # Number of seconds simulated -sim_ticks 5139557121500 # Number of ticks simulated -final_tick 5139557121500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.143601 # Number of seconds simulated +sim_ticks 5143601047500 # Number of ticks simulated +final_tick 5143601047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183644 # Simulator instruction rate (inst/s) -host_op_rate 364835 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3871369364 # Simulator tick rate (ticks/s) -host_mem_usage 967408 # Number of bytes of host memory used -host_seconds 1327.58 # Real time elapsed on the host -sim_insts 243802016 # Number of instructions simulated -sim_ops 484348047 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2455296 # Number of bytes read from this memory +host_inst_rate 337830 # Simulator instruction rate (inst/s) +host_op_rate 671266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7140786618 # Simulator tick rate (ticks/s) +host_mem_usage 909440 # Number of bytes of host memory used +host_seconds 720.31 # Real time elapsed on the host +sim_insts 243343656 # Number of instructions simulated +sim_ops 483521256 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2435392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 466944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5828928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 127616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1842944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 356032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2734144 # Number of bytes read from this memory -system.physmem.bytes_read::total 13813760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 466944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 127616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 356032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 950592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9154048 # Number of bytes written to this memory -system.physmem.bytes_written::total 9154048 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38364 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6105280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 134592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1637632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 319296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2611264 # Number of bytes read from this memory +system.physmem.bytes_read::total 13733504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 134592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 319296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 942336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9060160 # Number of bytes written to this memory +system.physmem.bytes_written::total 9060160 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38053 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 91077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28796 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42721 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215840 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143032 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143032 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 477725 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 95395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2103 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 25588 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 40801 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214586 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141565 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 473480 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1134130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 24830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 358580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 69273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 531980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2687734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90853 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 24830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 69273 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 184956 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1781097 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1781097 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1781097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 477725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 94962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1186966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 318382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 62076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 507672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2670017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 94962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 62076 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 183205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1761443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1761443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1761443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 473480 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1134130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 24830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 358580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 69273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 531980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4468830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 99105 # Total number of read requests seen -system.physmem.writeReqs 78746 # Total number of write requests seen -system.physmem.cpureqs 178569 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 6342720 # Total number of bytes read from memory -system.physmem.bytesWritten 5039744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 6342720 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5039744 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 712 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 5671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 5539 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5876 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 5654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 5883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6334 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 5868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 5656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7374 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5859 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4494 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4605 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5921 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4668 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4422 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4757 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6137 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 94962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1186966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 318382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 62076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 507672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4431460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 90446 # Total number of read requests seen +system.physmem.writeReqs 70433 # Total number of write requests seen +system.physmem.cpureqs 161351 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 5788544 # Total number of bytes read from memory +system.physmem.bytesWritten 4507712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 5788544 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4507712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 472 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 5853 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 5163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 5410 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 5863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 5951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6069 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 4925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 4669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 5184 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 5694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 5914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 5934 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4493 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4309 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4025 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4893 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 3572 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4337 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4609 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4582 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4499 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry -system.physmem.totGap 5135869541000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 5140092000000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 99105 # Categorize read packet sizes +system.physmem.readPktSize::6 90446 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 78746 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 75637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 70433 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,304 +156,522 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3407 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.totQLat 2229520000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4250910000 # Sum of mem lat for all requests -system.physmem.totBusLat 495470000 # Total cycles spent in databus access -system.physmem.totBankLat 1525920000 # Total cycles spent in bank access -system.physmem.avgQLat 22499.04 # Average queueing delay per request -system.physmem.avgBankLat 15398.71 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3071 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 30233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.294645 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 151.805560 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1124.042449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13536 44.77% 44.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 4627 15.30% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 2854 9.44% 69.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 1864 6.17% 75.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1230 4.07% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1007 3.33% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 772 2.55% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 598 1.98% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 458 1.51% 89.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 438 1.45% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 281 0.93% 91.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 279 0.92% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 209 0.69% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 207 0.68% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 177 0.59% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 236 0.78% 95.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 132 0.44% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 98 0.32% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 103 0.34% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 81 0.27% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 87 0.29% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 80 0.26% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 236 0.78% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 88 0.29% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 47 0.16% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 40 0.13% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 31 0.10% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 30 0.10% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 19 0.06% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 8 0.03% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 13 0.04% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 8 0.03% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 5 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 4 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 2 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 4 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 5 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 2 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 5 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 12 0.04% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 3 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 29 0.10% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 3 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 2 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 15 0.05% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 11 0.04% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 6 0.02% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 2 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 5 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 2 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 3 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 21 0.07% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 30233 # Bytes accessed per row activation +system.physmem.totQLat 1718746250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3502520000 # Sum of mem lat for all requests +system.physmem.totBusLat 452100000 # Total cycles spent in databus access +system.physmem.totBankLat 1331673750 # Total cycles spent in bank access +system.physmem.avgQLat 19008.47 # Average queueing delay per request +system.physmem.avgBankLat 14727.65 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 42897.75 # Average memory access latency -system.physmem.avgRdBW 1.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38736.12 # Average memory access latency +system.physmem.avgRdBW 1.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.88 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.88 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.10 # Average write queue length over time -system.physmem.readRowHits 83478 # Number of row buffer hits during reads -system.physmem.writeRowHits 56534 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes -system.physmem.avgGap 28877372.30 # Average gap between requests -system.l2c.replacements 104936 # number of replacements -system.l2c.tagsinuse 64827.217537 # Cycle average of tags in use -system.l2c.total_refs 3630977 # Total number of references to valid blocks. -system.l2c.sampled_refs 168979 # Sample count of references to valid blocks. -system.l2c.avg_refs 21.487741 # Average number of references to valid blocks. +system.physmem.avgWrQLen 0.11 # Average write queue length over time +system.physmem.readRowHits 78857 # Number of row buffer hits during reads +system.physmem.writeRowHits 51763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.49 # Row buffer hit rate for writes +system.physmem.avgGap 31950049.42 # Average gap between requests +system.membus.throughput 6398386 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 425816 # Transaction distribution +system.membus.trans_dist::ReadResp 425816 # Transaction distribution +system.membus.trans_dist::WriteReq 5631 # Transaction distribution +system.membus.trans_dist::WriteResp 5631 # Transaction distribution +system.membus.trans_dist::Writeback 70433 # Transaction distribution +system.membus.trans_dist::UpgradeReq 476 # Transaction distribution +system.membus.trans_dist::UpgradeResp 476 # Transaction distribution +system.membus.trans_dist::ReadExReq 69519 # Transaction distribution +system.membus.trans_dist::ReadExResp 69519 # Transaction distribution +system.membus.trans_dist::MessageReq 269 # Transaction distribution +system.membus.trans_dist::MessageResp 269 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 197349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1007895 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 60171 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 60171 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 257520 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 312424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1068604 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 1076 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7851072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9006954 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2445184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2445184 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 10296256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 11453214 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32574935 # Total data (bytes) +system.membus.snoop_data_through_bus 335808 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 770602000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 164025500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 314786000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 538000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 269000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1575668988 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 198012000 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.l2c.replacements 103562 # number of replacements +system.l2c.tagsinuse 64796.800964 # Cycle average of tags in use +system.l2c.total_refs 3619781 # Total number of references to valid blocks. +system.l2c.sampled_refs 167743 # Sample count of references to valid blocks. +system.l2c.avg_refs 21.579327 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50639.454481 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.125451 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 1092.997242 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4517.674660 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 223.356063 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 1300.523613 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 6.306120 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1891.819622 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 5154.960284 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.772697 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 51276.359665 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.126176 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 1273.083994 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4560.482374 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 265.925814 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 1312.167499 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 5.741812 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1370.746219 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 4732.167410 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.782415 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.016678 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.068934 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.003408 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.019844 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000096 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.028867 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.078658 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989185 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 20688 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11397 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 368018 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 524840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3790 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1830 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 151783 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 229669 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 45217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 8673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 312711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 544544 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2223160 # number of ReadReq hits +system.l2c.occ_percent::cpu0.inst 0.019426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.069587 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.004058 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.020022 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000088 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.020916 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.072207 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.988721 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21527 # 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number of Writeback hits -system.l2c.Writeback_hits::total 1544951 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 152 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 67 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 260 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 71407 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43953 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 57565 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172925 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20688 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 11399 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 368018 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 596247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3790 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018087 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.026017 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.011253 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.828283 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.201917 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.352133 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.346248 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.160687 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58676.429218 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64587.759371 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63501.423682 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -585,39 +803,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # 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average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 112590.537329 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 112590.537329 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 110904.377861 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 110904.377861 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 110904.377861 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 67344 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145447.587912 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145447.587912 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 99235.135595 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 99235.135595 # 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average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 169 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24864 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 24864 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 25033 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 25033 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 25033 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 25033 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 12912498 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12912498 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3966572850 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3966572850 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3979485348 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3979485348 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.186534 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.186534 # 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number of overall MSHR misses +system.iocache.overall_mshr_misses::total 21965 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95889055 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95889055 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3530226785 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3530226785 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3626115840 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3626115840 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.770330 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.770330 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.455137 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.455137 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.461159 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.461159 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 136788.951498 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136788.951498 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 166018.942109 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 166018.942109 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -689,336 +907,488 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 1838156995 # number of cpu cycles simulated +system.toL2Bus.throughput 52020310 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1696057 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1695532 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 5631 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 5631 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 870189 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 384 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 384 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 160044 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 138785 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 912543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3510594 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 23321 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 95695 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 4542153 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29200384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 115384682 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 82512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 359600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 145027178 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 267476487 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 95232 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4838788408 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 814500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2054232112 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4517736918 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 13025458 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 50823334 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1261125 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 151553 # Transaction distribution +system.iobus.trans_dist::ReadResp 151553 # Transaction distribution +system.iobus.trans_dist::WriteReq 26624 # Transaction distribution +system.iobus.trans_dist::WriteResp 26624 # Transaction distribution +system.iobus.trans_dist::MessageReq 269 # Transaction distribution +system.iobus.trans_dist::MessageResp 269 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 356892 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 159641 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1557685 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6486722 # Total data (bytes) +system.iobus.reqLayer0.occupancy 624016 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 3409000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 24000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 145153000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 43000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 11757000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 193475840 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 307064000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 26474000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 269000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.numCycles 1771999673 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 73261263 # Number of instructions committed -system.cpu0.committedOps 148566469 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 136919559 # Number of integer alu accesses +system.cpu0.committedInsts 74314462 # Number of instructions committed +system.cpu0.committedOps 150407349 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 138687072 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1069041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14289344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 136919559 # number of integer instructions +system.cpu0.num_func_calls 1088594 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14472613 # number of instructions that are conditional controls +system.cpu0.num_int_insts 138687072 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 336929611 # number of times the integer registers were read -system.cpu0.num_int_register_writes 173945922 # number of times the integer registers were written +system.cpu0.num_int_register_reads 341744011 # number of times the integer registers were read +system.cpu0.num_int_register_writes 175930003 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 14717824 # number of memory refs -system.cpu0.num_load_insts 10660250 # Number of load instructions -system.cpu0.num_store_insts 4057574 # Number of store instructions -system.cpu0.num_idle_cycles 1090327710419.609375 # Number of idle cycles -system.cpu0.num_busy_cycles -1088489553424.609375 # Number of busy cycles -system.cpu0.not_idle_fraction -592.163540 # Percentage of non-idle cycles -system.cpu0.idle_fraction 593.163540 # Percentage of idle cycles +system.cpu0.num_mem_refs 15165282 # number of memory refs +system.cpu0.num_load_insts 10883561 # Number of load instructions +system.cpu0.num_store_insts 4281721 # Number of store instructions +system.cpu0.num_idle_cycles 1050845405256.983643 # Number of idle cycles +system.cpu0.num_busy_cycles -1049073405583.983643 # Number of busy cycles +system.cpu0.not_idle_fraction -592.027991 # Percentage of non-idle cycles +system.cpu0.idle_fraction 593.027991 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.replacements 846873 # number of replacements -system.cpu0.icache.tagsinuse 510.809979 # Cycle average of tags in use -system.cpu0.icache.total_refs 129726169 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 847385 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 153.089999 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 147287067000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 322.415881 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 27.501112 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 160.892986 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.629719 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.053713 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.314244 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997676 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 89310227 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 37866681 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2549261 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129726169 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 89310227 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 37866681 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2549261 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129726169 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 89310227 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 37866681 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2549261 # number of overall hits -system.cpu0.icache.overall_hits::total 129726169 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 375314 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 153777 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 335702 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 864793 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 375314 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 153777 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 335702 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 864793 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 375314 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 153777 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 335702 # number of overall misses -system.cpu0.icache.overall_misses::total 864793 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2109411000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4767990981 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6877401981 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2109411000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4767990981 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6877401981 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2109411000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4767990981 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6877401981 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 89685541 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38020458 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2884963 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130590962 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 89685541 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38020458 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2884963 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130590962 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 89685541 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10451842999 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15061563999 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31167993500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33212773000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64380766500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 368756500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 730986500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1099743000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31536750000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33943759500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65480509500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.095720 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.120441 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.059855 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042784 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031393 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018453 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.043778 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.074628 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087399 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.043778 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11932.806637 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14625.649630 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13832.065698 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26315.178275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26401.324191 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26362.920003 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15218.020415 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16195.092434 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15882.984298 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1541993 # number of writebacks +system.cpu0.dcache.writebacks::total 1541993 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 342834 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 342834 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 12370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 12370 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 355204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 355204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 355204 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 355204 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 229498 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 546200 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 775698 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 61819 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 77322 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 139141 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 291317 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 623522 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 914839 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 291317 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 623522 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 914839 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2809489500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8130780549 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10940270049 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1990477500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2600292531 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4590770031 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4799967000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10731073080 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15531040080 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4799967000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10731073080 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15531040080 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31033142000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33153511000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64186653000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 465277000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 664192000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1129469000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31498419000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33817703000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65316122000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.090541 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.126495 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.058734 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038803 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030557 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016561 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.042337 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.042337 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.890997 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14886.086688 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14103.774986 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32198.474579 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33629.400830 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32993.654142 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1029,303 +1399,303 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606004355 # number of cpu cycles simulated +system.cpu1.numCycles 2608004713 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34463532 # Number of instructions committed -system.cpu1.committedOps 67005357 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62150402 # Number of integer alu accesses +system.cpu1.committedInsts 34942757 # Number of instructions committed +system.cpu1.committedOps 68016284 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63114732 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 411236 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6382216 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62150402 # number of integer instructions +system.cpu1.num_func_calls 430753 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6467325 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63114732 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 149729485 # number of times the integer registers were read -system.cpu1.num_int_register_writes 79937808 # number of times the integer registers were written +system.cpu1.num_int_register_reads 152021040 # number of times the integer registers were read +system.cpu1.num_int_register_writes 81233840 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 4253944 # number of memory refs -system.cpu1.num_load_insts 2634755 # Number of load instructions -system.cpu1.num_store_insts 1619189 # Number of store instructions -system.cpu1.num_idle_cycles 7677367348.593150 # Number of idle cycles -system.cpu1.num_busy_cycles -5071362993.593150 # Number of busy cycles -system.cpu1.not_idle_fraction -1.946030 # Percentage of non-idle cycles -system.cpu1.idle_fraction 2.946030 # Percentage of idle cycles +system.cpu1.num_mem_refs 4322210 # number of memory refs +system.cpu1.num_load_insts 2726743 # Number of load instructions +system.cpu1.num_store_insts 1595467 # Number of store instructions +system.cpu1.num_idle_cycles 9296961839.327438 # Number of idle cycles +system.cpu1.num_busy_cycles -6688957126.327438 # Number of busy cycles +system.cpu1.not_idle_fraction -2.564780 # Percentage of non-idle cycles +system.cpu1.idle_fraction 3.564780 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28657213 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28657213 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 282528 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26332341 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25809696 # Number of BTB hits +system.cpu2.branchPred.lookups 28107723 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28107723 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 253065 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 25890078 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25466613 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.015197 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 509678 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 56598 # Number of incorrect RAS predictions. -system.cpu2.numCycles 152138342 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 98.364373 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 482621 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 53231 # Number of incorrect RAS predictions. +system.cpu2.numCycles 150677905 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8765036 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141230370 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28657213 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26319374 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54195726 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1350224 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 59186 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 22546148 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6465 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 18223 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 777 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2884967 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 126552 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1685 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 86648155 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.214672 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.414816 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8157389 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 138649085 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28107723 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 25949234 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 53330196 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1190060 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 46897 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 22689996 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 1645 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6110 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 10082 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2679696 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 114342 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1368 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 85168083 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.213895 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.414010 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 32565830 37.58% 37.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 546380 0.63% 38.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23846422 27.52% 65.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 287955 0.33% 66.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 558507 0.64% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 803239 0.93% 67.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 320738 0.37% 68.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 484990 0.56% 68.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27234094 31.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 31941663 37.50% 37.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 506826 0.60% 38.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23646883 27.76% 65.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 259157 0.30% 66.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 526154 0.62% 66.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 751269 0.88% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 273870 0.32% 67.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 459070 0.54% 68.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 26803191 31.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 86648155 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.188363 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.928302 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10203383 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 21434341 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 42926723 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1270829 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1056674 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 277800524 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 10 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1056674 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11171095 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 12732005 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 3756843 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 43068844 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5106557 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 276894625 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6426 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2483944 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 1961652 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 2548 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 331033770 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 601753258 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 601753178 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 80 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321557178 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9476592 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 136008 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 137084 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11206153 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 5917951 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3223233 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 365517 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 302609 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275352384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 397965 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273886109 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53996 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6700477 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10323870 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 50144 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 86648155 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.160899 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.377923 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 85168083 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.186542 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.920169 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9520844 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 21607924 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 39424228 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1229084 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 928772 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 273051293 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 928772 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10439907 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 13089260 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 3699901 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 39570553 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 4982521 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 272244708 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 6270 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2417106 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 1932594 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 1355 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 325535285 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 590374943 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 590374855 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 317221539 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 8313746 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 122579 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 123510 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 10816950 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 5506267 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2968253 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 324837 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 268098 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 270840712 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 382144 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 269680817 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 48233 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 5882884 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 8996381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 45929 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 85168083 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.166454 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.381789 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 23779115 27.44% 27.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5842995 6.74% 34.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3792974 4.38% 38.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2596888 3.00% 41.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25119641 28.99% 70.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1266341 1.46% 72.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23944050 27.63% 99.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 257275 0.30% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48876 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 23491447 27.58% 27.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5639421 6.62% 34.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3592727 4.22% 38.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2433201 2.86% 41.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 24826332 29.15% 70.43% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1184872 1.39% 71.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23718098 27.85% 99.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 237817 0.28% 99.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44168 0.05% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 86648155 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 85168083 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 118795 33.06% 33.06% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.07% 33.13% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 86 0.02% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 188736 52.53% 85.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 51440 14.32% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 103037 31.19% 31.19% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 241 0.07% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 31.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 181800 55.03% 86.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 45300 13.71% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 68063 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264478225 96.57% 96.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 51078 0.02% 96.61% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 47173 0.02% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6223177 2.27% 98.90% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3018393 1.10% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 57001 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 260895656 96.74% 96.76% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 47542 0.02% 96.78% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 43696 0.02% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 5855050 2.17% 98.97% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2781872 1.03% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273886109 # Type of FU issued -system.cpu2.iq.rate 1.800244 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 359298 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001312 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 634870698 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282454128 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272600027 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 31 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 8 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274177330 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 14 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 614321 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 269680817 # Type of FU issued +system.cpu2.iq.rate 1.789783 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 330378 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001225 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 624940807 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 277108342 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 268465757 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 40 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 38 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 269954173 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 21 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 584645 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 929558 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6267 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3704 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 478908 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 814531 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6351 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3024 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 433740 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656133 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10377 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 655738 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10426 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1056674 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8226180 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 803204 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275750349 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 63685 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 5917951 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3223233 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 220549 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 623968 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3956 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3704 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 161931 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 157888 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 319819 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273437676 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6124763 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 448433 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 928772 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8598252 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 798569 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 271222856 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 58264 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 5506267 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2968253 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 206333 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 621407 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3570 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3024 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 146514 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 137704 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 284218 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 269282728 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 5768116 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 398089 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9083662 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27821550 # Number of branches executed -system.cpu2.iew.exec_stores 2958899 # Number of stores executed -system.cpu2.iew.exec_rate 1.797296 # Inst execution rate -system.cpu2.iew.wb_sent 273301697 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272600035 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212879972 # num instructions producing a value -system.cpu2.iew.wb_consumers 348297595 # num instructions consuming a value +system.cpu2.iew.exec_refs 8495654 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27379135 # Number of branches executed +system.cpu2.iew.exec_stores 2727538 # Number of stores executed +system.cpu2.iew.exec_rate 1.787141 # Inst execution rate +system.cpu2.iew.wb_sent 269160909 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 268465771 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 209852405 # num instructions producing a value +system.cpu2.iew.wb_consumers 343221010 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.791790 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611201 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.781720 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611421 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6973062 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 347821 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 284653 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 85591481 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.140222 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.867307 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 6125563 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 336215 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 254201 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 84239311 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.146959 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.869440 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 28429929 33.22% 33.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4148762 4.85% 38.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1193631 1.39% 39.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24678313 28.83% 68.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 797871 0.93% 69.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 541346 0.63% 69.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 330295 0.39% 70.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23445398 27.39% 97.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2025936 2.37% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 28027655 33.27% 33.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 3948624 4.69% 37.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1090324 1.29% 39.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24397189 28.96% 68.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 757994 0.90% 69.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 507340 0.60% 69.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 301970 0.36% 70.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23269432 27.62% 97.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1938783 2.30% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 85591481 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136077221 # Number of instructions committed -system.cpu2.commit.committedOps 268776221 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 84239311 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 134086437 # Number of instructions committed +system.cpu2.commit.committedOps 265097623 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7732718 # Number of memory references committed -system.cpu2.commit.loads 4988393 # Number of loads committed -system.cpu2.commit.membars 163760 # Number of memory barriers committed -system.cpu2.commit.branches 27507890 # Number of branches committed +system.cpu2.commit.refs 7226249 # Number of memory references committed +system.cpu2.commit.loads 4691736 # Number of loads committed +system.cpu2.commit.membars 162513 # Number of memory barriers committed +system.cpu2.commit.branches 27101249 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245262632 # Number of committed integer instructions. -system.cpu2.commit.function_calls 414873 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2025936 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 241753447 # Number of committed integer instructions. +system.cpu2.commit.function_calls 394614 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1938783 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 359289994 # The number of ROB reads -system.cpu2.rob.rob_writes 552558663 # The number of ROB writes -system.cpu2.timesIdled 454161 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65490187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4914041775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136077221 # Number of Instructions Simulated -system.cpu2.committedOps 268776221 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 136077221 # Number of Instructions Simulated -system.cpu2.cpi 1.118029 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.118029 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.894431 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.894431 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 502349004 # number of integer regfile reads -system.cpu2.int_regfile_writes 325553024 # number of integer regfile writes -system.cpu2.fp_regfile_reads 62552 # number of floating regfile reads -system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88383748 # number of misc regfile reads -system.cpu2.misc_regfile_writes 121022 # number of misc regfile writes +system.cpu2.rob.rob_reads 353502675 # The number of ROB reads +system.cpu2.rob.rob_writes 543377618 # The number of ROB writes +system.cpu2.timesIdled 448607 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65509822 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4919608430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 134086437 # Number of Instructions Simulated +system.cpu2.committedOps 265097623 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 134086437 # Number of Instructions Simulated +system.cpu2.cpi 1.123737 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.123737 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.889888 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.889888 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 494284042 # number of integer regfile reads +system.cpu2.int_regfile_writes 320739139 # number of integer regfile writes +system.cpu2.fp_regfile_reads 62606 # number of floating regfile reads +system.cpu2.fp_regfile_writes 62592 # number of floating regfile writes +system.cpu2.misc_regfile_reads 86692309 # number of misc regfile reads +system.cpu2.misc_regfile_writes 109016 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |