diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1868 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt | 324 |
2 files changed, 1254 insertions, 938 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 908c82993..0613cfd5e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,84 +1,242 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133289 # Number of seconds simulated -sim_ticks 5133289198000 # Number of ticks simulated -final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.128875 # Number of seconds simulated +sim_ticks 5128875494000 # Number of ticks simulated +final_tick 5128875494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170996 # Simulator instruction rate (inst/s) -host_op_rate 338013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2151657827 # Simulator tick rate (ticks/s) -host_mem_usage 361992 # Number of bytes of host memory used -host_seconds 2385.74 # Real time elapsed on the host -sim_insts 407952579 # Number of instructions simulated -sim_ops 806410876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory +host_inst_rate 179743 # Simulator instruction rate (inst/s) +host_op_rate 355302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2259848354 # Simulator tick rate (ticks/s) +host_mem_usage 404644 # Number of bytes of host memory used +host_seconds 2269.57 # Real time elapsed on the host +sim_insts 407937807 # Number of instructions simulated +sim_ops 806381430 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2484160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory -system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory -system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1082048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10897856 # Number of bytes read from this memory +system.physmem.bytes_read::total 14467456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1082048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1082048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9613376 # Number of bytes written to this memory +system.physmem.bytes_written::total 9613376 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 170279 # Number of read requests responded to by this memory +system.physmem.num_reads::total 226054 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 150209 # Number of write requests responded to by this memory +system.physmem.num_writes::total 150209 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 484348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 574 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2124804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2820785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1874363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1874363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1874363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 484348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 574 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s) -system.iocache.replacements 47577 # number of replacements -system.iocache.tagsinuse 0.116486 # Cycle average of tags in use +system.physmem.bw_total::cpu.inst 210972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2124804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4695148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 226054 # Total number of read requests seen +system.physmem.writeReqs 150209 # Total number of write requests seen +system.physmem.cpureqs 390083 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14467456 # Total number of bytes read from memory +system.physmem.bytesWritten 9613376 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14467456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9613376 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 85 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3870 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 14969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14927 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15009 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8995 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 10163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9599 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 10025 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 10138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10156 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 5128875413000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 226054 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 150209 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3870 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 177383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3329517724 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7605839724 # Sum of mem lat for all requests +system.physmem.totBusLat 903876000 # Total cycles spent in databus access +system.physmem.totBankLat 3372446000 # Total cycles spent in bank access +system.physmem.avgQLat 14734.40 # Average queueing delay per request +system.physmem.avgBankLat 14924.37 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 33658.77 # Average memory access latency +system.physmem.avgRdBW 2.82 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 14.06 # Average write queue length over time +system.physmem.readRowHits 199198 # Number of row buffer hits during reads +system.physmem.writeRowHits 88428 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.87 # Row buffer hit rate for writes +system.physmem.avgGap 13631091.58 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.091613 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 912 # number of ReadReq misses +system.iocache.warmup_cycle 4991895066000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.091613 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.005726 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.005726 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses -system.iocache.demand_misses::total 47632 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses -system.iocache.overall_misses::total 47632 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143697932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143697932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8983849160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 8983849160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9127547092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9127547092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9127547092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9127547092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -87,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157736.478595 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 157736.478595 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192291.291952 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 192291.291952 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191630.389704 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191630.389704 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56345 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7566 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.447132 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96295990 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96295990 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6552154765 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6552154765 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6648450755 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6648450755 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -129,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105703.611416 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105703.611416 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140243.038634 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 140243.038634 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -150,141 +308,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448600431 # number of cpu cycles simulated +system.cpu.numCycles 448887765 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits +system.cpu.BPredUnit.lookups 86493598 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86493598 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1184200 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81985656 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79438611 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28044653 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427268280 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86493598 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79438611 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164008180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5056188 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 124973 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62751260 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 62335 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9257771 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 519239 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3803 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 258861392 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.258152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.417945 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95283812 36.81% 36.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1591927 0.61% 37.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71954404 27.80% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971846 0.38% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1615863 0.62% 66.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2450126 0.95% 67.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1121647 0.43% 67.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1424659 0.55% 68.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82447108 31.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 258861392 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192684 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.951838 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31762033 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60235448 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159762632 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3267698 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3833581 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840104917 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1244 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3833581 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34530134 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37412206 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10702091 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159938633 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12444747 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836257763 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19698 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5896480 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4716940 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7816 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 997992319 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816026440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816025416 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1024 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964353103 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33639209 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466352 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 473282 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28808345 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17312855 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10260076 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1206444 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 946818 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829834961 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1255797 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824342965 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165215 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23689940 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36113140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 258861392 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.184496 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385380 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 154456 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72001826 27.81% 27.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15596239 6.02% 33.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10365970 4.00% 37.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7555139 2.92% 40.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75952295 29.34% 70.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3901347 1.51% 71.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72539766 28.02% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 795622 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 153188 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 258861392 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 354431 33.41% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 554175 52.24% 85.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152275 14.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 306719 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796534260 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -313,246 +471,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18029662 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9472324 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued -system.cpu.iq.rate 1.837676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824342965 # Type of FU issued +system.cpu.iq.rate 1.836412 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1060881 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1908906757 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854790380 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819662460 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825097030 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650086 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3338406 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26898 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11294 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1845192 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932288 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11793 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 725973 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11358 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 710415 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1333170 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17608498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3833581 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26182715 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2118325 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831090758 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 325842 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17312855 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10260082 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 724912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616921 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11294 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 708686 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 624381 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1333067 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822327193 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17600649 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2015771 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26834247 # number of memory reference insts executed -system.cpu.iew.exec_branches 83283502 # Number of branches executed -system.cpu.iew.exec_stores 9225749 # Number of stores executed -system.cpu.iew.exec_rate 1.833188 # Inst execution rate -system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819707466 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640500741 # num instructions producing a value -system.cpu.iew.wb_consumers 1046431080 # num instructions consuming a value +system.cpu.iew.exec_refs 26823265 # number of memory reference insts executed +system.cpu.iew.exec_branches 83275848 # Number of branches executed +system.cpu.iew.exec_stores 9222616 # Number of stores executed +system.cpu.iew.exec_rate 1.831922 # Inst execution rate +system.cpu.iew.wb_sent 821819072 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819662518 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640525310 # num instructions producing a value +system.cpu.iew.wb_consumers 1046521436 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back +system.cpu.iew.wb_rate 1.825985 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612052 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052864 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1189777 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255221218 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.159655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.852368 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24603279 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052602 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1189396 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255043204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.161744 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853415 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11920052 4.67% 37.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4017826 1.57% 38.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74972744 29.38% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2476508 0.97% 69.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1494072 0.59% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1000652 0.39% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70934036 27.79% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5202298 2.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83146159 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11856679 4.65% 37.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3955758 1.55% 38.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74970525 29.40% 68.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2479858 0.97% 69.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1486016 0.58% 69.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951787 0.37% 70.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70929950 27.81% 97.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5266472 2.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255221218 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407952579 # Number of instructions committed -system.cpu.commit.committedOps 806410876 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255043204 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407937807 # Number of instructions committed +system.cpu.commit.committedOps 806381430 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22397454 # Number of memory references committed -system.cpu.commit.loads 13980397 # Number of loads committed -system.cpu.commit.membars 473477 # Number of memory barriers committed -system.cpu.commit.branches 82193415 # Number of branches committed +system.cpu.commit.refs 22389336 # Number of memory references committed +system.cpu.commit.loads 13974446 # Number of loads committed +system.cpu.commit.membars 473457 # Number of memory barriers committed +system.cpu.commit.branches 82191509 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735346024 # Number of committed integer instructions. +system.cpu.commit.int_insts 735317730 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5202298 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5266472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080968615 # The number of ROB reads -system.cpu.rob.rob_writes 1665910047 # The number of ROB writes -system.cpu.timesIdled 1218526 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189561046 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817975385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407952579 # Number of Instructions Simulated -system.cpu.committedOps 806410876 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated -system.cpu.cpi 1.099639 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads -system.cpu.ipc 0.909390 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.909390 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508324148 # number of integer regfile reads -system.cpu.int_regfile_writes 977861305 # number of integer regfile writes -system.cpu.fp_regfile_reads 65 # number of floating regfile reads -system.cpu.misc_regfile_reads 265169626 # number of misc regfile reads -system.cpu.misc_regfile_writes 402500 # number of misc regfile writes -system.cpu.icache.replacements 1068646 # number of replacements -system.cpu.icache.tagsinuse 510.896112 # Cycle average of tags in use -system.cpu.icache.total_refs 8129454 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1069158 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.603604 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.896112 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997844 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997844 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8129454 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8129454 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8129454 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8129454 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8129454 # number of overall hits -system.cpu.icache.overall_hits::total 8129454 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1139394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1139394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1139394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1139394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1139394 # number of overall misses -system.cpu.icache.overall_misses::total 1139394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15246811490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15246811490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15246811490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15246811490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15246811490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15246811490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9268848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9268848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9268848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9268848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9268848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9268848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122927 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122927 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122927 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122927 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122927 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122927 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13381.509373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13381.509373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13381.509373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13381.509373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13381.509373 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5114 # number of cycles access was blocked +system.cpu.rob.rob_reads 1080683249 # The number of ROB reads +system.cpu.rob.rob_writes 1665823647 # The number of ROB writes +system.cpu.timesIdled 1223181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190026373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9808860643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407937807 # Number of Instructions Simulated +system.cpu.committedOps 806381430 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407937807 # Number of Instructions Simulated +system.cpu.cpi 1.100383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.100383 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908775 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908775 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508172140 # number of integer regfile reads +system.cpu.int_regfile_writes 977803744 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.misc_regfile_reads 265152690 # number of misc regfile reads +system.cpu.misc_regfile_writes 402177 # number of misc regfile writes +system.cpu.icache.replacements 1074366 # number of replacements +system.cpu.icache.tagsinuse 510.322538 # Cycle average of tags in use +system.cpu.icache.total_refs 8113553 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1074878 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.548348 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.322538 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996724 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996724 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8113553 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8113553 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8113553 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8113553 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8113553 # number of overall hits +system.cpu.icache.overall_hits::total 8113553 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1144218 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1144218 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1144218 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1144218 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1144218 # number of overall misses +system.cpu.icache.overall_misses::total 1144218 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15461286493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15461286493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15461286493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15461286493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15461286493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15461286493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9257771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9257771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9257771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9257771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9257771 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9257771 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123595 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123595 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123595 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123595 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123595 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123595 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13512.535630 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13512.535630 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13512.535630 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13512.535630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13512.535630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13512.535630 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7080 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 251 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.519084 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.207171 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68044 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68044 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68044 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68044 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68044 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68044 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071350 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1071350 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1071350 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1071350 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1071350 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1071350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12542463990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12542463990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12542463990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12542463990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12542463990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12542463990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115586 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115586 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115586 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115586 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11707.158249 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11707.158249 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11707.158249 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11707.158249 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67124 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67124 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67124 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67124 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67124 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67124 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077094 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1077094 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1077094 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1077094 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1077094 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1077094 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12721673493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12721673493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12721673493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12721673493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12721673493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12721673493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116345 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116345 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116345 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.107938 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.107938 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9707 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.043772 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27693 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9719 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.849367 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5100157918000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.043772 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377736 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.377736 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27843 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27843 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 10271 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.965877 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 29367 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 10284 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.855601 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103910768500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.965877 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.435367 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.435367 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29379 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 29379 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27846 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27846 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27846 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27846 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10592 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10592 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10592 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10592 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10592 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10592 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116124000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116124000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116124000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 116124000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116124000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 116124000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38435 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38435 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29382 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 29382 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29382 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 29382 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11163 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 11163 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11163 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 11163 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11163 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 11163 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 123160000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 123160000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 123160000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 123160000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 123160000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 123160000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40542 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 40542 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38438 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38438 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38438 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38438 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275582 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275582 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275561 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.275561 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275561 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.275561 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10963.368580 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10963.368580 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10963.368580 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10963.368580 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10963.368580 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40545 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 40545 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40545 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 40545 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275344 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275344 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275324 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.275324 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275324 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.275324 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11032.876467 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11032.876467 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11032.876467 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11032.876467 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1540 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1540 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10592 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10592 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10592 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10592 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10592 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10592 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94940000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94940000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94940000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94940000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94940000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94940000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275582 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275582 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275561 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275561 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275561 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8963.368580 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8963.368580 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8963.368580 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1731 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1731 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11163 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11163 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11163 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 11163 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11163 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 11163 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 100834000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 100834000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 100834000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 100834000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 100834000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 100834000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275344 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275344 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275324 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275324 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9032.876467 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 107637 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 11.991971 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139374 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 107653 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.294660 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5096875914000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.991971 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749498 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.749498 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139374 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139374 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139374 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139374 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139374 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139374 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108671 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 108671 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108671 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 108671 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108671 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 108671 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1362724500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1362724500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1362724500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1362724500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1362724500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1362724500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248045 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 248045 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248045 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 248045 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248045 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.438110 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.438110 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.438110 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.438110 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.438110 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.438110 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12539.909451 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12539.909451 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109401 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.751867 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 137796 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109417 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.259366 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100515626500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.751867 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.859492 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.859492 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137796 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 137796 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137796 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 137796 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137796 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 137796 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110443 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110443 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110443 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110443 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110443 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110443 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1382584000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1382584000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1382584000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1382584000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1382584000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1382584000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248239 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 248239 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248239 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 248239 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248239 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 248239 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.444906 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.444906 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.444906 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.444906 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.444906 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.444906 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12518.529920 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12518.529920 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12518.529920 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12518.529920 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 32720 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 32720 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108671 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108671 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108671 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 108671 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108671 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 108671 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1145382500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1145382500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1145382500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1145382500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.438110 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.438110 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.438110 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.438110 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10539.909451 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 36585 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 36585 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110443 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110443 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110443 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110443 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110443 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110443 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1161698000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1161698000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1161698000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.444906 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.444906 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.444906 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10518.529920 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1673658 # number of replacements -system.cpu.dcache.tagsinuse 511.992942 # Cycle average of tags in use -system.cpu.dcache.total_refs 19220297 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1674170 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.480493 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 32836000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992942 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11126575 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11126575 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8088656 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8088656 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19215231 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19215231 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19215231 # number of overall hits -system.cpu.dcache.overall_hits::total 19215231 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2269640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2269640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 319173 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 319173 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2588813 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2588813 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2588813 # number of overall misses -system.cpu.dcache.overall_misses::total 2588813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31726602500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31726602500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9823121491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9823121491 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41549723991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41549723991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41549723991 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41549723991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13396215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13396215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8407829 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8407829 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21804044 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21804044 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21804044 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21804044 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169424 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169424 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037961 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037961 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118731 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13978.693758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.693758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30776.793435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30776.793435 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16049.720081 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16049.720081 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16049.720081 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 366322 # number of cycles access was blocked +system.cpu.dcache.replacements 1672817 # number of replacements +system.cpu.dcache.tagsinuse 511.996932 # Cycle average of tags in use +system.cpu.dcache.total_refs 19210877 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673329 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.480634 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.996932 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11119324 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11119324 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8086692 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8086692 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19206016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19206016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19206016 # number of overall hits +system.cpu.dcache.overall_hits::total 19206016 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2269518 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2269518 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318969 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318969 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2588487 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2588487 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2588487 # number of overall misses +system.cpu.dcache.overall_misses::total 2588487 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32394569000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32394569000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9644667991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9644667991 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42039236991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42039236991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42039236991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42039236991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13388842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13388842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8405661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8405661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21794503 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21794503 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21794503 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21794503 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169508 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169508 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037947 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037947 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14273.766060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14273.766060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30237.007330 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30237.007330 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16240.853051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16240.853051 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 395046 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42954 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.528240 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.287988 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1573837 # number of writebacks -system.cpu.dcache.writebacks::total 1573837 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 884183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26057 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26057 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 910240 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 910240 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 910240 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 910240 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1385457 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1385457 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293116 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 293116 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1678573 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1678573 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1678573 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1678573 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17084942000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17084942000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8988357491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8988357491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26073299491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26073299491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26073299491 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26073299491 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296962500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296962500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470375500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470375500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767338000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767338000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103422 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103422 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076984 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076984 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076984 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12331.629202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12331.629202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30664.847675 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30664.847675 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15533.014942 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15533.014942 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1572293 # number of writebacks +system.cpu.dcache.writebacks::total 1572293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885972 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 885972 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7867222930 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3366085 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 392014 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 796439838 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7067024993 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7867222930 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185355500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185355500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304598500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304598500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489954000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489954000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026977 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916178 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916178 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.065824 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.065824 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47107.105814 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51997.122677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50491.707979 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.673804 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.673804 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38288.169829 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.169829 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index ccb436843..c24f73d04 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,77 +1,235 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.205007 # Number of seconds simulated -sim_ticks 5205006924000 # Number of ticks simulated -final_tick 5205006924000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.205006 # Number of seconds simulated +sim_ticks 5205006494000 # Number of ticks simulated +final_tick 5205006494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143770 # Simulator instruction rate (inst/s) -host_op_rate 275863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6917470976 # Simulator tick rate (ticks/s) -host_mem_usage 505276 # Number of bytes of host memory used -host_seconds 752.44 # Real time elapsed on the host -sim_insts 108178578 # Number of instructions simulated -sim_ops 207571464 # Number of ops (including micro ops) simulated +host_inst_rate 176611 # Simulator instruction rate (inst/s) +host_op_rate 338881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8497542071 # Simulator tick rate (ticks/s) +host_mem_usage 459536 # Number of bytes of host memory used +host_seconds 612.53 # Real time elapsed on the host +sim_insts 108179755 # Number of instructions simulated +sim_ops 207574747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 173936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 174032 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 86216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 870514880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 69689841 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 49504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 870539632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 69693671 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 20312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 157070368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27207776 # Number of bytes read from this memory -system.physmem.bytes_read::total 1124848049 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 870514880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 157070368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1027585248 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157047256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27202450 # Number of bytes read from this memory +system.physmem.bytes_read::total 1124848257 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 870539632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157047256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1027586888 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 48549302 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 21364054 # Number of bytes written to this memory -system.physmem.bytes_written::total 72904476 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 48549554 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 21360352 # Number of bytes written to this memory +system.physmem.bytes_written::total 72901026 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 818 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 21742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 21754 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 10777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 108814360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 12175547 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 108817454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 12176562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6184 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2539 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 19633796 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4005942 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144671709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 19630907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4005282 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144672277 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 7160367 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2936343 # Number of write requests responded to by this memory -system.physmem.num_writes::total 10143448 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 7160394 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2935820 # Number of write requests responded to by this memory +system.physmem.num_writes::total 10142952 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 6766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 33417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 33436 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 16564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 167245672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13389001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 9511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 167250441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13389738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 9505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30176784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5227231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 216108848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 167245672 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30176784 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197422456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30172346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5226209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 216108906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 167250441 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30172346 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197422787 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574659 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 9327423 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 4104520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 14006605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 9327472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 4103809 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 14005943 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 581425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 33417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 33436 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 16567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 167245672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 22716424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 9511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 167250441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 22717210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 9505 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30176784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 9331751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 230115453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30172346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 9330018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 230114849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 818 # Total number of read requests seen +system.physmem.writeReqs 46736 # Total number of write requests seen +system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 52352 # Total number of bytes read from memory +system.physmem.bytesWritten 2991104 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 35216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 322 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 3080 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 3056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2944 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2640 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 3152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 3016 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 63209426000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 306 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 512 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 46736 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 40984666 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 52278666 # Sum of mem lat for all requests +system.physmem.totBusLat 3272000 # Total cycles spent in databus access +system.physmem.totBankLat 8022000 # Total cycles spent in bank access +system.physmem.avgQLat 50103.50 # Average queueing delay per request +system.physmem.avgBankLat 9806.85 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 63910.35 # Average memory access latency +system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.57 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.15 # Average write queue length over time +system.physmem.readRowHits 695 # Number of row buffer hits during reads +system.physmem.writeRowHits 45891 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.19 # Row buffer hit rate for writes +system.physmem.avgGap 1329213.65 # Average gap between requests system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -114,52 +272,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10410013848 # number of cpu cycles simulated +system.cpu0.numCycles 10410012988 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 93129090 # Number of instructions committed -system.cpu0.committedOps 179514856 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 169447650 # Number of integer alu accesses +system.cpu0.committedInsts 93132190 # Number of instructions committed +system.cpu0.committedOps 179521943 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 169453705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16553172 # number of instructions that are conditional controls -system.cpu0.num_int_insts 169447650 # number of integer instructions +system.cpu0.num_conditional_control_insts 16554212 # number of instructions that are conditional controls +system.cpu0.num_int_insts 169453705 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 418656867 # number of times the integer registers were read -system.cpu0.num_int_register_writes 211655789 # number of times the integer registers were written +system.cpu0.num_int_register_reads 418670977 # number of times the integer registers were read +system.cpu0.num_int_register_writes 211662649 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 20197632 # number of memory refs -system.cpu0.num_load_insts 13022518 # Number of load instructions -system.cpu0.num_store_insts 7175114 # Number of store instructions -system.cpu0.num_idle_cycles 9667682114.054142 # Number of idle cycles -system.cpu0.num_busy_cycles 742331733.945857 # Number of busy cycles -system.cpu0.not_idle_fraction 0.071309 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.928691 # Percentage of idle cycles +system.cpu0.num_mem_refs 20198672 # number of memory refs +system.cpu0.num_load_insts 13023532 # Number of load instructions +system.cpu0.num_store_insts 7175140 # Number of store instructions +system.cpu0.num_idle_cycles 9667664508.054142 # Number of idle cycles +system.cpu0.num_busy_cycles 742348479.945857 # Number of busy cycles +system.cpu0.not_idle_fraction 0.071311 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.928689 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10407072224 # number of cpu cycles simulated +system.cpu1.numCycles 10407071288 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15049488 # Number of instructions committed -system.cpu1.committedOps 28056608 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 27537877 # Number of integer alu accesses +system.cpu1.committedInsts 15047565 # Number of instructions committed +system.cpu1.committedOps 28052804 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 27533880 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1864532 # number of instructions that are conditional controls -system.cpu1.num_int_insts 27537877 # number of integer instructions +system.cpu1.num_conditional_control_insts 1864518 # number of instructions that are conditional controls +system.cpu1.num_int_insts 27533880 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 71380294 # number of times the integer registers were read -system.cpu1.num_int_register_writes 31003707 # number of times the integer registers were written +system.cpu1.num_int_register_reads 71369326 # number of times the integer registers were read +system.cpu1.num_int_register_writes 30999444 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 6975131 # number of memory refs -system.cpu1.num_load_insts 4014934 # Number of load instructions -system.cpu1.num_store_insts 2960197 # Number of store instructions -system.cpu1.num_idle_cycles 10279839396.425842 # Number of idle cycles -system.cpu1.num_busy_cycles 127232827.574158 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012226 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987774 # Percentage of idle cycles +system.cpu1.num_mem_refs 6973948 # number of memory refs +system.cpu1.num_load_insts 4014274 # Number of load instructions +system.cpu1.num_store_insts 2959674 # Number of store instructions +system.cpu1.num_idle_cycles 10279858503.692720 # Number of idle cycles +system.cpu1.num_busy_cycles 127212784.307279 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012224 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987776 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |