diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
3 files changed, 985 insertions, 1014 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index f7ba63a28..71b7ba73e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -16,9 +16,10 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 readfile=tests/halt.sh @@ -98,7 +99,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -158,6 +158,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -174,21 +175,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -213,21 +209,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port @@ -503,21 +494,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -530,7 +516,7 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system -int_master=system.membus.slave[4] +int_master=system.membus.slave[3] int_slave=system.membus.master[3] pio=system.membus.master[2] @@ -556,21 +542,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port @@ -583,25 +564,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[3] +mem_side=system.membus.slave[2] [system.cpu.toL2Bus] type=CoherentBus @@ -997,25 +973,20 @@ assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[18] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[4] [system.membus] type=CoherentBus @@ -1027,7 +998,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1297,7 +1268,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-x86.img +image_file=/gem5/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1317,7 +1288,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/gem5/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 334789158..a2d9ec174 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:14:29 -gem5 started Oct 30 2012 18:26:17 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 23:13:25 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5132789913000 because m5_exit instruction encountered +Exiting @ tick 5136797077000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 87b53a299..48207d64f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132790 # Number of seconds simulated -sim_ticks 5132789913000 # Number of ticks simulated -final_tick 5132789913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136797 # Number of seconds simulated +sim_ticks 5136797077000 # Number of ticks simulated +final_tick 5136797077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148899 # Simulator instruction rate (inst/s) -host_op_rate 294332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1873578722 # Simulator tick rate (ticks/s) -host_mem_usage 406892 # Number of bytes of host memory used -host_seconds 2739.56 # Real time elapsed on the host -sim_insts 407917143 # Number of instructions simulated -sim_ops 806342485 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2491072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1075264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10835456 # Number of bytes read from this memory -system.physmem.bytes_read::total 14405312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1075264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1075264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9578880 # Number of bytes written to this memory -system.physmem.bytes_written::total 9578880 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16801 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169304 # Number of read requests responded to by this memory -system.physmem.num_reads::total 225083 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149670 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149670 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 485325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 209489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2111027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2806527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 209489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 209489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1866213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1866213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1866213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 485325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 209489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2111027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4672740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 225083 # Total number of read requests seen -system.physmem.writeReqs 149670 # Total number of write requests seen -system.physmem.cpureqs 388719 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14405312 # Total number of bytes read from memory -system.physmem.bytesWritten 9578880 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14405312 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9578880 # bytesWritten derated as per pkt->getSize() +host_inst_rate 59794 # Simulator instruction rate (inst/s) +host_op_rate 118197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 752889080 # Simulator tick rate (ticks/s) +host_mem_usage 765888 # Number of bytes of host memory used +host_seconds 6822.78 # Real time elapsed on the host +sim_insts 407963976 # Number of instructions simulated +sim_ops 806432115 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2490112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1077440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10840448 # Number of bytes read from this memory +system.physmem.bytes_read::total 14411520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1077440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1077440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9595008 # Number of bytes written to this memory +system.physmem.bytes_written::total 9595008 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169382 # Number of read requests responded to by this memory +system.physmem.num_reads::total 225180 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149922 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149922 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 484760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2110352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2805546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1867897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1867897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1867897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 484760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 209749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2110352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4673443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 225180 # Total number of read requests seen +system.physmem.writeReqs 149922 # Total number of write requests seen +system.physmem.cpureqs 389082 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14411520 # Total number of bytes read from memory +system.physmem.bytesWritten 9595008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14411520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9595008 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4102 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14545 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14098 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 14962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 14901 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 10390 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 10526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9654 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 10118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9236 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 10295 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9932 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8008 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 10206 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 4150 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15044 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13538 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13271 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12817 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15188 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8767 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10396 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8323 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 10117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9956 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 9930 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10179 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8298 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9881 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8122 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10268 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 49 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132789860500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136797025000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 225083 # Categorize read packet sizes +system.physmem.readPktSize::6 225180 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 149719 # categorize write packet sizes +system.physmem.writePktSize::6 149922 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -114,33 +114,33 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4102 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4150 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 176543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 176541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -150,47 +150,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 841 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3269589754 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7518085754 # Sum of mem lat for all requests -system.physmem.totBusLat 900032000 # Total cycles spent in databus access -system.physmem.totBankLat 3348464000 # Total cycles spent in bank access -system.physmem.avgQLat 14530.99 # Average queueing delay per request -system.physmem.avgBankLat 14881.53 # Average bank access latency per request +system.physmem.totQLat 3390959114 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7646017114 # Sum of mem lat for all requests +system.physmem.totBusLat 900420000 # Total cycles spent in databus access +system.physmem.totBankLat 3354638000 # Total cycles spent in bank access +system.physmem.avgQLat 15063.90 # Average queueing delay per request +system.physmem.avgBankLat 14902.55 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33412.53 # Average memory access latency +system.physmem.avgMemAccLat 33966.45 # Average memory access latency system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s @@ -198,45 +198,45 @@ system.physmem.avgConsumedWrBW 1.87 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.37 # Average write queue length over time -system.physmem.readRowHits 198566 # Number of row buffer hits during reads -system.physmem.writeRowHits 87960 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.77 # Row buffer hit rate for writes -system.physmem.avgGap 13696461.03 # Average gap between requests -system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.103964 # Cycle average of tags in use +system.physmem.avgWrQLen 11.93 # Average write queue length over time +system.physmem.readRowHits 198524 # Number of row buffer hits during reads +system.physmem.writeRowHits 88099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes +system.physmem.avgGap 13694400.52 # Average gap between requests +system.iocache.replacements 47577 # number of replacements +system.iocache.tagsinuse 0.116411 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991828572000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103964 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.warmup_cycle 4991829125000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.116411 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007276 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007276 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses -system.iocache.demand_misses::total 47631 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses -system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146267932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 146267932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8962382160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 8962382160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9108650092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9108650092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9108650092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9108650092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146446932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 146446932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9011912160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9011912160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9158359092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9158359092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9158359092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9158359092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160557.554336 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160557.554336 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191831.809932 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 191831.809932 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191233.652285 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191233.652285 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191233.652285 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51554 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160577.776316 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160577.776316 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192891.955479 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 192891.955479 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192273.242610 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192273.242610 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 57584 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7256 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7533 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.105017 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.644232 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98865990 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 98865990 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6530591975 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 6530591975 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6629457965 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6629457965 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6629457965 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98991992 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98991992 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6580127962 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6580127962 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6679119954 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6679119954 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,18 +287,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108524.687157 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108524.687157 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139781.506314 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 139781.506314 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139183.682161 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 139183.682161 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108543.850877 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108543.850877 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140841.780009 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 140841.780009 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -308,141 +308,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 447650408 # number of cpu cycles simulated +system.cpu.numCycles 447871414 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86252473 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86252473 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1112360 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81440812 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79250759 # Number of BTB hits +system.cpu.BPredUnit.lookups 86248524 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86248524 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1109719 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81324372 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79248318 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27455337 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426133339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86252473 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79250759 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163637491 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4749598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 117040 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62764723 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36355 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 51011 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 275 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9043493 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 487667 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3497 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257661797 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.265027 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27555812 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426098303 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86248524 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79248318 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163629889 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4731856 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 116400 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62921622 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 35870 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 52533 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 368 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9034264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 488269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3183 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257896503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.261731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418044 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94448905 36.66% 36.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1567012 0.61% 37.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71922195 27.91% 65.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 935544 0.36% 65.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1602565 0.62% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2433530 0.94% 67.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1078893 0.42% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1381790 0.54% 68.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82291363 31.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94692515 36.72% 36.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1566812 0.61% 37.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71928839 27.89% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 936780 0.36% 65.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1600320 0.62% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2427387 0.94% 67.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1078261 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1378215 0.53% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82287374 31.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257661797 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192678 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.951933 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31146269 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60227421 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159444515 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3244027 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3599565 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838112106 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 919 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3599565 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33887749 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37302672 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10848429 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159621170 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12402212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834448767 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20383 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5810954 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4749020 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7935 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 996003699 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1811552283 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1811551779 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964308271 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31695421 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 457655 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 465271 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28736743 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17096853 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10140380 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1243307 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 975146 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828306292 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1248163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823283697 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148415 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22289625 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33892420 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 195525 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257661797 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.195211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.383294 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257896503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192574 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.951385 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31239529 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60388203 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159435692 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3249070 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3584009 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838053376 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 983 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3584009 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33976924 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37367105 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10941861 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159620502 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12406102 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834408692 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19434 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5810292 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4754441 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7847 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995994396 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1811420133 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1811419405 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 728 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964426992 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31567397 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 458567 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 466421 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28739056 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17094362 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10134243 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1234841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 965780 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 828292865 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1249354 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823298492 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 149694 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22192286 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33736795 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 196434 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257896503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.192360 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.384089 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71201357 27.63% 27.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15459797 6.00% 33.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10286150 3.99% 37.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7472850 2.90% 40.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75924697 29.47% 69.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3857138 1.50% 71.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72522119 28.15% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 785654 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152035 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71417814 27.69% 27.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15473003 6.00% 33.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10302554 3.99% 37.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7467952 2.90% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75909427 29.43% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3864522 1.50% 71.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72522780 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 788081 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 150370 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257661797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257896503 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364358 34.12% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 552545 51.74% 85.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150975 14.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 363959 34.09% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552647 51.76% 85.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 151055 14.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 312887 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795710532 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 310624 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795733525 96.65% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -471,246 +471,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17869782 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9390496 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17867181 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9387162 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823283697 # Type of FU issued -system.cpu.iq.rate 1.839122 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1067878 # FU busy when requested +system.cpu.iq.FU_type_0::total 823298492 # Type of FU issued +system.cpu.iq.rate 1.838247 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067661 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905576298 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851854038 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818789401 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824038596 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1642479 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 1905840686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851744345 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818819585 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 303 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 346 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 824055392 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 137 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1644579 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3121524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22243 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11430 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1726583 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3112367 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 23963 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11499 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1716857 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932632 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11779 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932401 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11954 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3599565 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26096083 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2112224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829554455 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 302739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17096853 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10140380 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 717341 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1614771 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11695 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11430 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 654771 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 594016 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1248787 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821389011 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17449263 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1894685 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3584009 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26166561 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2112396 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829542219 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 307602 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17094362 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10134243 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718774 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1614614 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11947 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11499 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 653687 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 591965 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1245652 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821416518 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17449825 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1881973 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26607287 # number of memory reference insts executed -system.cpu.iew.exec_branches 83217289 # Number of branches executed -system.cpu.iew.exec_stores 9158024 # Number of stores executed -system.cpu.iew.exec_rate 1.834889 # Inst execution rate -system.cpu.iew.wb_sent 820925784 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818789455 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639951171 # num instructions producing a value -system.cpu.iew.wb_consumers 1045809475 # num instructions consuming a value +system.cpu.iew.exec_refs 26604955 # number of memory reference insts executed +system.cpu.iew.exec_branches 83223788 # Number of branches executed +system.cpu.iew.exec_stores 9155130 # Number of stores executed +system.cpu.iew.exec_rate 1.834045 # Inst execution rate +system.cpu.iew.wb_sent 820955265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818819659 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639977790 # num instructions producing a value +system.cpu.iew.wb_consumers 1045837145 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.829082 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back +system.cpu.iew.wb_rate 1.828247 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611929 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23105687 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052636 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1116569 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254077625 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.173607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.854352 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 23003299 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052918 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1114308 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254312494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.171028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.854625 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82352974 32.41% 32.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11796837 4.64% 37.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3872314 1.52% 38.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74949594 29.50% 68.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2433419 0.96% 69.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1479159 0.58% 69.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 902635 0.36% 69.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70918587 27.91% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5372106 2.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82565112 32.47% 32.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11801317 4.64% 37.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3875007 1.52% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74957575 29.47% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2434316 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480794 0.58% 69.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 899910 0.35% 70.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70920339 27.89% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5378124 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254077625 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407917143 # Number of instructions committed -system.cpu.commit.committedOps 806342485 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254312494 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407963976 # Number of instructions committed +system.cpu.commit.committedOps 806432115 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22389123 # Number of memory references committed -system.cpu.commit.loads 13975326 # Number of loads committed -system.cpu.commit.membars 473463 # Number of memory barriers committed -system.cpu.commit.branches 82187715 # Number of branches committed +system.cpu.commit.refs 22399378 # Number of memory references committed +system.cpu.commit.loads 13981992 # Number of loads committed +system.cpu.commit.membars 473513 # Number of memory barriers committed +system.cpu.commit.branches 82199908 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735283087 # Number of committed integer instructions. +system.cpu.commit.int_insts 735371295 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5372106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5378124 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078075497 # The number of ROB reads -system.cpu.rob.rob_writes 1662514782 # The number of ROB writes -system.cpu.timesIdled 1218897 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 189988611 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817926834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407917143 # Number of Instructions Simulated -system.cpu.committedOps 806342485 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407917143 # Number of Instructions Simulated -system.cpu.cpi 1.097405 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.097405 # CPI: Total CPI of All Threads -system.cpu.ipc 0.911240 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.911240 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506960736 # number of integer regfile reads -system.cpu.int_regfile_writes 976968921 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 264713842 # number of misc regfile reads -system.cpu.misc_regfile_writes 402218 # number of misc regfile writes -system.cpu.icache.replacements 1046081 # number of replacements -system.cpu.icache.tagsinuse 510.992308 # Cycle average of tags in use -system.cpu.icache.total_refs 7932749 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1046593 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.579593 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1078291467 # The number of ROB reads +system.cpu.rob.rob_writes 1662473587 # The number of ROB writes +system.cpu.timesIdled 1221266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189974911 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9825720160 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407963976 # Number of Instructions Simulated +system.cpu.committedOps 806432115 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407963976 # Number of Instructions Simulated +system.cpu.cpi 1.097821 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.097821 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910895 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910895 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1507038080 # number of integer regfile reads +system.cpu.int_regfile_writes 977032757 # number of integer regfile writes +system.cpu.fp_regfile_reads 74 # number of floating regfile reads +system.cpu.misc_regfile_reads 264726295 # number of misc regfile reads +system.cpu.misc_regfile_writes 402502 # number of misc regfile writes +system.cpu.icache.replacements 1052817 # number of replacements +system.cpu.icache.tagsinuse 510.984184 # Cycle average of tags in use +system.cpu.icache.total_refs 7916649 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1053329 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.515837 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.992308 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998032 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998032 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7932749 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7932749 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7932749 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7932749 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7932749 # number of overall hits -system.cpu.icache.overall_hits::total 7932749 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1110744 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1110744 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1110744 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1110744 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1110744 # number of overall misses -system.cpu.icache.overall_misses::total 1110744 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15035266490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15035266490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15035266490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15035266490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15035266490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15035266490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9043493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9043493 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9043493 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9043493 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9043493 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9043493 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122822 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122822 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122822 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122822 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122822 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122822 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13536.212206 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12467027488 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12467027488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116867 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116867 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116867 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116867 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.010608 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.010608 # 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miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.273668 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11065.435908 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11065.435908 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11065.435908 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11065.435908 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11065.435908 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11065.435908 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -719,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10817 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10817 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10817 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10817 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10817 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10817 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94903500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94903500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94903500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94903500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94903500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94903500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.292067 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.292067 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.292044 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.292044 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.292044 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8773.550892 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8773.550892 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8773.550892 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1844 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1844 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10048 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10048 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10048 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10048 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10048 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10048 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 91089500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 91089500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 91089500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 91089500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 91089500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 91089500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.273683 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.273683 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.273668 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.273668 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.273668 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9065.435908 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9065.435908 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 113923 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.921985 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 130116 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 113938 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.141990 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100448688500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.921985 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.807624 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.807624 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130138 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 130138 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130138 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 130138 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130138 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 130138 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 114896 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 114896 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 114896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 114896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 114896 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 114896 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1427497500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1427497500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1427497500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1427497500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1427497500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1427497500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245034 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 245034 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245034 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 245034 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245034 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 245034 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.468898 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.468898 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.468898 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.468898 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.468898 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.468898 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.257589 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.257589 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.257589 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.257589 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.257589 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 111590 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 11.995325 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 130038 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 111605 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.165163 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100439779500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 11.995325 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.749708 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.749708 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 130049 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 130049 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 130049 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 130049 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 130049 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 130049 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 112651 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 112651 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 112651 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 112651 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 112651 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 112651 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1400311500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1400311500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1400311500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1400311500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1400311500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1400311500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 242700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 242700 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 242700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 242700 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 242700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 242700 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.464157 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.464157 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.464157 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.464157 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.464157 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.464157 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12430.528801 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12430.528801 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12430.528801 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12430.528801 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35555 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35555 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 114896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 114896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 114896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 114896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 114896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 114896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1197705500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1197705500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1197705500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1197705500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.468898 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.468898 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.468898 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.468898 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10424.257589 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10424.257589 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10424.257589 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35078 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35078 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 112651 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 112651 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 112651 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 112651 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 112651 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 112651 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1175009500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1175009500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1175009500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.464157 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.464157 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.464157 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10430.528801 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1657882 # number of replacements -system.cpu.dcache.tagsinuse 511.998105 # Cycle average of tags in use -system.cpu.dcache.total_refs 19102953 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1658394 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.518947 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27815000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998105 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11010989 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11010989 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8086819 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8086819 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19097808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19097808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19097808 # number of overall hits -system.cpu.dcache.overall_hits::total 19097808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2233987 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2233987 # 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number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41382260993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41382260993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13244976 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13244976 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8404566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8404566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21649542 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21649542 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21649542 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21649542 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168667 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168667 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037806 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037806 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117865 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117865 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117865 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117865 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14242.699040 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14242.699040 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30100.225944 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30100.225944 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16217.309874 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16217.309874 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16217.309874 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 396326 # number of cycles access was blocked +system.cpu.dcache.replacements 1661569 # number of replacements +system.cpu.dcache.tagsinuse 511.994847 # Cycle average of tags in use +system.cpu.dcache.total_refs 19098471 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1662081 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.490698 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994847 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11004011 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11004011 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8089317 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8089317 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19093328 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19093328 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19093328 # number of overall hits +system.cpu.dcache.overall_hits::total 19093328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2239016 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2239016 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318822 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318822 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2557838 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2557838 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2557838 # number of overall misses +system.cpu.dcache.overall_misses::total 2557838 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31972900500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31972900500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9624592994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9624592994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41597493494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41597493494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41597493494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41597493494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13243027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13243027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8408139 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8408139 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21651166 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21651166 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21651166 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21651166 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169071 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169071 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037918 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037918 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118139 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118139 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118139 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118139 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14279.889246 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14279.889246 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30187.982617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30187.982617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16262.755301 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16262.755301 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 404649 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42512 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42429 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.322685 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.537085 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1559612 # number of writebacks -system.cpu.dcache.writebacks::total 1559612 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862458 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 862458 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26265 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 26265 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 888723 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 888723 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 888723 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 888723 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371529 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1371529 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291482 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291482 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1663011 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1663011 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1663011 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1663011 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17298488500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17298488500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8726866493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8726866493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26025354993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26025354993 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26025354993 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26025354993 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296677500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296677500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469996000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469996000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766673500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766673500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103551 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103551 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034681 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034681 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076815 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076815 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076815 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12612.557591 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12612.557591 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29939.641189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29939.641189 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15649.538694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15649.538694 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1562908 # number of writebacks +system.cpu.dcache.writebacks::total 1562908 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864676 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864676 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1666778 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1666778 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17366494500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17366494500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8784809994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8784809994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26151304494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26151304494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26151304494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26151304494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97298090500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97298090500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473113000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473113000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99771203500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99771203500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034780 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034780 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076983 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076983 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076983 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076983 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.243215 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.243215 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30039.905874 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30039.905874 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15689.734622 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15689.734622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15689.734622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15689.734622 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -946,141 +946,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113761 # number of replacements -system.cpu.l2cache.tagsinuse 64829.122340 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3920006 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 178006 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.021763 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114048 # number of replacements +system.cpu.l2cache.tagsinuse 64828.781789 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3943145 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 178083 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.142175 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50212.838916 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 12.458733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.160012 # 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