all: Update stats for memory per master and total fix.

6 files changed, 230 insertions, 63 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 7261617c5..a9da64c54 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:58
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 17:03:49
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 3dd4a07d4..bfc607b4f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -4,23 +4,48 @@ sim_seconds                                  5.157514                       # Nu
 sim_ticks                                5157514159500                       # Number of ticks simulated
 final_tick                               5157514159500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128842                       # Simulator instruction rate (inst/s)
-host_op_rate                                   253899                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1558019011                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389972                       # Number of bytes of host memory used
-host_seconds                                  3310.30                       # Real time elapsed on the host
+host_inst_rate                                 123762                       # Simulator instruction rate (inst/s)
+host_op_rate                                   243888                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1496586873                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 369148                       # Number of bytes of host memory used
+host_seconds                                  3446.18                       # Real time elapsed on the host
 sim_insts                                   426506235                       # Number of instructions simulated
 sim_ops                                     840483958                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    15959488                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1257664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 12050112                       # Number of bytes written to this memory
-system.physmem.num_reads                       249367                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      188283                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3094415                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    243851                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2336419                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       5430833                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::pc.south_bridge.ide      2798400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         6720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker         1088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1257664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          11895616                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             15959488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1257664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1257664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     12050112                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          12050112                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        43725                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker          105                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           17                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              19651                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             185869                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                249367                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          188283                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               188283                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       542587                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               243851                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2306463                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3094415                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          243851                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             243851                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2336419                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2336419                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2336419                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       542587                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              243851                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2306463                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5430833                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        167142                       # number of replacements
 system.l2c.tagsinuse                     37816.689690                       # Cycle average of tags in use
 system.l2c.total_refs                         3843284                       # Total number of references to valid blocks.
@@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000957
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001927                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.018136                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.033077                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.025337                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.882394                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.882394                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.481904                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.481904                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.dtb.walker     0.000957                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.001927                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.inst        0.018136                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.111631                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.071839                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.dtb.walker     0.000957                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.001927                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.inst       0.018136                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.111631                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.071839                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52468.724211                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15491.669972                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52077.298075                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.data 52195.198861                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52201.292100                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.data 52195.198861                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52201.292100                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -213,33 +248,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000957
 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001927                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.018135                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.033076                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.025337                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.882394                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.882394                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.481904                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.481904                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000957                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001927                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.inst     0.018135                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.data     0.111630                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.071838                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000957                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001927                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.inst     0.018135                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.data     0.111630                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.071838                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40249.342829                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40144.585482                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40010.093602                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40085.880200                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40085.880200                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     47578                       # number of replacements
 system.iocache.tagsinuse                     0.166155                       # Cycle average of tags in use
@@ -275,13 +323,21 @@ system.iocache.demand_accesses::total           47633                       # nu
 system.iocache.overall_accesses::pc.south_bridge.ide        47633                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47633                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125279.224535                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 136416.955479                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 136203.474314                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 136203.474314                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      69025534                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                11269                       # number of cycles access was blocked
@@ -309,13 +365,21 @@ system.iocache.demand_mshr_miss_latency::total   4010524860
 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4010524860                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total   4010524860                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 73254.087623                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 84410.185745                       # average WriteReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 84196.352529                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 84196.352529                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -635,11 +699,17 @@ system.cpu.icache.demand_accesses::total      9366799                       # nu
 system.cpu.icache.overall_accesses::cpu.inst      9366799                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total      9366799                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123115                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.123115                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.123115                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.123115                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.123115                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.123115                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14938.055188                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14938.055188                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14938.055188                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs      2912492                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs               289                       # number of cycles access was blocked
@@ -669,11 +739,17 @@ system.cpu.icache.demand_mshr_miss_latency::total  13093471492
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13093471492                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total  13093471492                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115814                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115814                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115814                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.115814                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115814                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.115814                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12069.918282                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12069.918282                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12069.918282                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements        10825                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        6.011393                       # Cycle average of tags in use
@@ -713,11 +789,17 @@ system.cpu.itb_walker_cache.demand_accesses::total        39097
 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        39097                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        39097                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.298946                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.298946                       # miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.298923                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.298923                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.298923                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.298923                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12681.954308                       # average ReadReq miss latency
 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12681.954308                       # average overall miss latency
 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12681.954308                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -741,11 +823,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    112719500
 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    112719500                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    112719500                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.298946                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.298946                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.298923                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.298923                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.298923                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.298923                       # mshr miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9644.861812                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9644.861812                       # average ReadReq mshr miss latency
 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9644.861812                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9644.861812                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9644.861812                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9644.861812                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.replacements       116553                       # number of replacements
 system.cpu.dtb_walker_cache.tagsinuse       13.859632                       # Cycle average of tags in use
@@ -781,11 +869,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total       253531
 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       253531                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total       253531                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.463730                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.463730                       # miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.463730                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.463730                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.463730                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.463730                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13967.432168                       # average ReadReq miss latency
 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13967.432168                       # average overall miss latency
 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13967.432168                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -809,11 +903,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1286519500
 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1286519500                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1286519500                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.463730                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.463730                       # mshr miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.463730                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.463730                       # mshr miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.463730                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.463730                       # mshr miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10942.583142                       # average ReadReq mshr miss latency
 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10942.583142                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10942.583142                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1673290                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997033                       # Cycle average of tags in use
@@ -857,13 +957,21 @@ system.cpu.dcache.demand_accesses::total     21751990                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     21751990                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21751990                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180567                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180567                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037870                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037870                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.125479                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.125479                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.125479                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.125479                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15004.833868                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33222.326506                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17127.337761                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17127.337761                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     25105497                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              3680                       # number of cycles access was blocked
@@ -905,16 +1013,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1392930500
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86600685000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total  86600685000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103449                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103449                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035203                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035203                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077103                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.077103                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077103                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077103                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13158.410391                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31623.944119                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16413.096906                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16413.096906                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
index 78474a665..c9fc9d3a5 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -995,7 +995,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1015,7 +1015,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1185,9 +1185,8 @@ zero=false
 port=system.piobus.master[0]
 
 [system.piobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=true
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 5cc55eff8..f9683d0c4 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: May/21/2012 19:39:45
+Real time: Jun/04/2012 17:25:31
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1285
-Elapsed_time_in_minutes: 21.4167
-Elapsed_time_in_hours: 0.356944
-Elapsed_time_in_days: 0.0148727
+Elapsed_time_in_seconds: 842
+Elapsed_time_in_minutes: 14.0333
+Elapsed_time_in_hours: 0.233889
+Elapsed_time_in_days: 0.00974537
 
-Virtual_time_in_seconds: 1013.41
-Virtual_time_in_minutes: 16.8902
-Virtual_time_in_hours:   0.281503
-Virtual_time_in_days:    0.0117293
+Virtual_time_in_seconds: 842.03
+Virtual_time_in_minutes: 14.0338
+Virtual_time_in_hours:   0.233897
+Virtual_time_in_days:    0.00974572
 
 Ruby_current_time: 10609379371
 Ruby_start_time: 0
 Ruby_cycles: 10609379371
 
-mbytes_resident: 269.652
-mbytes_total: 517.469
-resident_ratio: 0.521114
+mbytes_resident: 268.047
+mbytes_total: 470.199
+resident_ratio: 0.570071
 
 ruby_cycles_executed: [ 10609379372 10609379372 ]
 
@@ -123,13 +123,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 |
 Resource Usage
 --------------
 page_size: 4096
-user_time: 1013
+user_time: 841
 system_time: 0
-page_reclaims: 70791
-page_faults: 113
+page_reclaims: 69674
+page_faults: 18
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 16056
+block_outputs: 408
 
 Network Stats
 -------------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
index 4bb71c433..d6cb455f2 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May 21 2012 19:18:11
-gem5 started May 21 2012 19:18:20
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jun  4 2012 13:44:12
+gem5 started Jun  4 2012 17:11:29
+gem5 executing on zizzer
 command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5304689685500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
index c2f297e1d..b7d143468 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,23 +4,74 @@ sim_seconds                                  5.304690                       # Nu
 sim_ticks                                5304689685500                       # Number of ticks simulated
 final_tick                               5304689685500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 106822                       # Simulator instruction rate (inst/s)
-host_op_rate                                   218222                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4128199893                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 529892                       # Number of bytes of host memory used
-host_seconds                                  1284.99                       # Real time elapsed on the host
+host_inst_rate                                 163049                       # Simulator instruction rate (inst/s)
+host_op_rate                                   333085                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6301127704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 481488                       # Number of bytes of host memory used
+host_seconds                                   841.86                       # Real time elapsed on the host
 sim_insts                                   137264752                       # Number of instructions simulated
 sim_ops                                     280412254                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                  1392025556                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read             1298120352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 70902832                       # Number of bytes written to this memory
-system.physmem.num_reads                    178001662                       # Number of read requests responded to by this memory
-system.physmem.num_writes                     9866514                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      262414135                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 244711836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      13366066                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     275780201                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::pc.south_bridge.ide        35144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker       126800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        64416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        827772912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         39626426                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       100784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        45696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst        470347440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         53905938                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1392025556                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    827772912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst    470347440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1298120352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data      32173132                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data      35738580                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70902832                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          809                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker        15850                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         8052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst         103471614                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           6642662                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker        12598                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         5712                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst          58793430                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data           9050935                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             178001662                       # Number of read requests responded to by this memory
+system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data          4837067                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data          4982709                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              9866514                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         6625                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker         23903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker         12143                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           156045492                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7470074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker         18999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          8614                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            88666344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            10161940                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               262414135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      156045492                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       88666344                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          244711836                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       563860                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            6065036                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            6737167                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13366066                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       570485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker        23903                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker        12146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          156045492                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13535110                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker        18999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         8614                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           88666344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           16899107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              275780201                       # Total bandwidth to/from this memory (bytes/s)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
@@ -44,7 +95,7 @@ system.cpu0.num_func_calls                          0                       # nu
 system.cpu0.num_conditional_control_insts     17923925                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                   168469813                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          517963582                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          517963630                       # number of times the integer registers were read
 system.cpu0.num_int_register_writes         280483339                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
@@ -68,7 +119,7 @@ system.cpu1.num_func_calls                          0                       # nu
 system.cpu1.num_conditional_control_insts      8197841                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    89110416                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          273178552                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads          273178604                       # number of times the integer registers were read
 system.cpu1.num_int_register_writes         138760228                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written