diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1903 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt | 47 |
2 files changed, 960 insertions, 990 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f940daeff..171e4af9f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,143 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.140861 # Number of seconds simulated -sim_ticks 5140860798000 # Number of ticks simulated -final_tick 5140860798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136865 # Number of seconds simulated +sim_ticks 5136864535500 # Number of ticks simulated +final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170494 # Simulator instruction rate (inst/s) -host_op_rate 337025 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2148706625 # Simulator tick rate (ticks/s) -host_mem_usage 754648 # Number of bytes of host memory used -host_seconds 2392.54 # Real time elapsed on the host -sim_insts 407913764 # Number of instructions simulated -sim_ops 806343994 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2474560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +host_inst_rate 199949 # Simulator instruction rate (inst/s) +host_op_rate 395248 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2517891877 # Simulator tick rate (ticks/s) +host_mem_usage 755196 # Number of bytes of host memory used +host_seconds 2040.15 # Real time elapsed on the host +sim_insts 407925588 # Number of instructions simulated +sim_ops 806363480 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1078400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10800768 # Number of bytes read from this memory -system.physmem.bytes_read::total 14357184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1078400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1078400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9566720 # Number of bytes written to this memory -system.physmem.bytes_written::total 9566720 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory +system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168762 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149480 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149480 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 598 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 209770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2100965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2792759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 209770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 209770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1860918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1860918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1860918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 209770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2100965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4653677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224331 # Total number of read requests seen -system.physmem.writeReqs 149480 # Total number of write requests seen -system.physmem.cpureqs 389156 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14357184 # Total number of bytes read from memory -system.physmem.bytesWritten 9566720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14357184 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9566720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 64 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4099 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13135 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15567 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15643 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8814 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11838 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8497 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8701 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8403 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 10999 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8504 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8205 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11031 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224749 # Total number of read requests seen +system.physmem.writeReqs 149477 # Total number of write requests seen +system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14383936 # Total number of bytes read from memory +system.physmem.bytesWritten 9566528 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1147 # Number of times wr buffer was full causing retry -system.physmem.totGap 5140860745500 # Total gap between requests +system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136864483000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224331 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 150627 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4099 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 173172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1784 # What read queue length does an incoming req see +system.physmem.readPktSize::6 224749 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 149477 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1773 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -149,16 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6490 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see @@ -173,70 +159,69 @@ system.physmem.wrQLenPdf::19 6499 # Wh system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4794174501 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9303317001 # Sum of mem lat for all requests -system.physmem.totBusLat 1121335000 # Total cycles spent in databus access -system.physmem.totBankLat 3387807500 # Total cycles spent in bank access -system.physmem.avgQLat 21377.08 # Average queueing delay per request -system.physmem.avgBankLat 15106.13 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests +system.physmem.totBusLat 1123260000 # Total cycles spent in databus access +system.physmem.totBankLat 3389952500 # Total cycles spent in bank access +system.physmem.avgQLat 21207.34 # Average queueing delay per request +system.physmem.avgBankLat 15089.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41483.22 # Average memory access latency -system.physmem.avgRdBW 2.79 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 41297.13 # Average memory access latency +system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.79 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.88 # Average write queue length over time -system.physmem.readRowHits 193356 # Number of row buffer hits during reads -system.physmem.writeRowHits 105797 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.78 # Row buffer hit rate for writes -system.physmem.avgGap 13752566.79 # Average gap between requests -system.iocache.replacements 47574 # number of replacements -system.iocache.tagsinuse 0.128668 # Cycle average of tags in use +system.physmem.avgWrQLen 11.02 # Average write queue length over time +system.physmem.readRowHits 193727 # Number of row buffer hits during reads +system.physmem.writeRowHits 105780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes +system.physmem.avgGap 13726637.07 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.116322 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991908358000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.128668 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.008042 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.008042 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143200932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143200932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10097082160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10097082160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10240283092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10240283092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10240283092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10240283092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157536.778878 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 157536.778878 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 216119.053082 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 216119.053082 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215001.009721 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215001.009721 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 136887 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12650 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.821107 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95911989 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95911989 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7666293817 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7666293817 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7762205806 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7762205806 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105513.739274 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105513.739274 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 164090.193001 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 164090.193001 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -308,142 +293,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86195570 # Number of BP lookups -system.cpu.branchPred.condPredicted 86195570 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1107298 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81287324 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79211919 # Number of BTB hits +system.cpu.branchPred.lookups 86198193 # Number of BP lookups +system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.446828 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448232203 # number of cpu cycles simulated +system.cpu.numCycles 448153841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27444393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 425935714 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86195570 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79211919 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163577459 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4703661 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 120329 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63100618 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 50393 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9010824 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 484273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3255 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257888489 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.260624 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94737944 36.74% 36.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1567529 0.61% 37.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71915391 27.89% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 936422 0.36% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1600476 0.62% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2419747 0.94% 67.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1072144 0.42% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1374255 0.53% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82264581 31.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257888489 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192301 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950257 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31158433 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60539785 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159369860 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3262201 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3558210 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837747525 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 908 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3558210 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33896779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37429027 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10979367 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159568616 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12456490 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834117350 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5870357 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4754276 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7741 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995632267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1810669462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1810668566 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964317189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31315071 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 459232 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 466806 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28815526 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17065121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10125717 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1247966 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 991465 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828007231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1251140 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823065161 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148512 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22000890 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33478625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 198442 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257888489 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.191554 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384086 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71416188 27.69% 27.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15522620 6.02% 33.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10297220 3.99% 37.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7470539 2.90% 40.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75900478 29.43% 70.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3837629 1.49% 71.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72511548 28.12% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 780997 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151270 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257888489 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 362608 34.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553228 51.88% 85.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150521 14.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 311367 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795535215 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -472,246 +457,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17840146 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9378433 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823065161 # Type of FU issued -system.cpu.iq.rate 1.836247 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1066357 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001296 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905364388 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851269170 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818594497 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 333 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 81 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823820002 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 149 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1640065 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued +system.cpu.iq.rate 1.836572 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3087216 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23041 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11568 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1713876 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12043 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3558210 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26163339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2115746 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829258371 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 321958 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17065121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10125717 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 719121 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1615790 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11387 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11568 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 649229 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593828 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1243057 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821192043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17430508 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1873117 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26576754 # number of memory reference insts executed -system.cpu.iew.exec_branches 83195358 # Number of branches executed -system.cpu.iew.exec_stores 9146246 # Number of stores executed -system.cpu.iew.exec_rate 1.832068 # Inst execution rate -system.cpu.iew.wb_sent 820730031 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818594578 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639788924 # num instructions producing a value -system.cpu.iew.wb_consumers 1045548924 # num instructions consuming a value +system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed +system.cpu.iew.exec_branches 83197450 # Number of branches executed +system.cpu.iew.exec_stores 9146557 # Number of stores executed +system.cpu.iew.exec_rate 1.832396 # Inst execution rate +system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639795417 # num instructions producing a value +system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826273 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611917 # average fanout of values written-back +system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22806507 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052696 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1111685 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254330279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.170460 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853927 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82551524 32.46% 32.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11813015 4.64% 37.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3912372 1.54% 38.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74944552 29.47% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2436279 0.96% 69.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1482727 0.58% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 942941 0.37% 70.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70918770 27.88% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5328099 2.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254330279 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407913764 # Number of instructions committed -system.cpu.commit.committedOps 806343994 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254301568 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407925588 # Number of instructions committed +system.cpu.commit.committedOps 806363480 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22389743 # Number of memory references committed -system.cpu.commit.loads 13977902 # Number of loads committed -system.cpu.commit.membars 473467 # Number of memory barriers committed -system.cpu.commit.branches 82188680 # Number of branches committed +system.cpu.commit.refs 22390327 # Number of memory references committed +system.cpu.commit.loads 13977401 # Number of loads committed +system.cpu.commit.membars 473457 # Number of memory barriers committed +system.cpu.commit.branches 82191015 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735286834 # Number of committed integer instructions. +system.cpu.commit.int_insts 735304742 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5328099 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5333125 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078074430 # The number of ROB reads -system.cpu.rob.rob_writes 1661878047 # The number of ROB writes -system.cpu.timesIdled 1220922 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190343714 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9833486813 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407913764 # Number of Instructions Simulated -system.cpu.committedOps 806343994 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407913764 # Number of Instructions Simulated -system.cpu.cpi 1.098841 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098841 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910050 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910050 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506675506 # number of integer regfile reads -system.cpu.int_regfile_writes 976772305 # number of integer regfile writes -system.cpu.fp_regfile_reads 81 # number of floating regfile reads -system.cpu.misc_regfile_reads 264620330 # number of misc regfile reads -system.cpu.misc_regfile_writes 402287 # number of misc regfile writes -system.cpu.icache.replacements 1047202 # number of replacements -system.cpu.icache.tagsinuse 510.392599 # Cycle average of tags in use -system.cpu.icache.total_refs 7900027 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1047714 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.540251 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1078031216 # The number of ROB reads +system.cpu.rob.rob_writes 1661854677 # The number of ROB writes +system.cpu.timesIdled 1219790 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190298330 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9825572650 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407925588 # Number of Instructions Simulated +system.cpu.committedOps 806363480 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407925588 # Number of Instructions Simulated +system.cpu.cpi 1.098617 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098617 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910236 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910236 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506687590 # number of integer regfile reads +system.cpu.int_regfile_writes 976781809 # number of integer regfile writes +system.cpu.fp_regfile_reads 63 # number of floating regfile reads +system.cpu.misc_regfile_reads 264621583 # number of misc regfile reads +system.cpu.misc_regfile_writes 402234 # number of misc regfile writes +system.cpu.icache.replacements 1045798 # number of replacements +system.cpu.icache.tagsinuse 510.125014 # Cycle average of tags in use +system.cpu.icache.total_refs 7900747 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046310 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.551058 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.392599 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996861 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996861 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7900027 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7900027 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7900027 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7900027 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7900027 # number of overall hits -system.cpu.icache.overall_hits::total 7900027 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1110794 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1110794 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1110794 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1110794 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1110794 # number of overall misses -system.cpu.icache.overall_misses::total 1110794 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15299065993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15299065993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15299065993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15299065993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15299065993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15299065993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9010821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9010821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9010821 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9010821 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9010821 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9010821 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123273 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123273 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123273 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123273 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123273 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123273 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13773.090234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13773.090234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13773.090234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13773.090234 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 10781 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.125014 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7900747 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7900747 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7900747 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7900747 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7900747 # number of overall hits +system.cpu.icache.overall_hits::total 7900747 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1109320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1109320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1109320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1109320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1109320 # number of overall misses +system.cpu.icache.overall_misses::total 1109320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15268069493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15268069493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15268069493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15268069493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15268069493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15268069493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9010067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9010067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9010067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9010067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9010067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9010067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123120 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123120 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123120 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123120 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123120 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123120 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13763.449224 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13763.449224 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13763.449224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13763.449224 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12508 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 279 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 293 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.641577 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.689420 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60632 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60632 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60632 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60632 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60632 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60632 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1050162 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1050162 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1050162 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1050162 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1050162 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1050162 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12588415993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12588415993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12588415993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12588415993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12588415993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12588415993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116545 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116545 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116545 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11987.118171 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11987.118171 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60685 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60685 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60685 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60685 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60685 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60685 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048635 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1048635 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1048635 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1048635 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1048635 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1048635 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12573562493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12573562493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12573562493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12573562493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12573562493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12573562493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116385 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116385 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116385 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11990.408954 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11990.408954 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9719 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.023103 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25822 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9733 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.653036 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5104044206500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.023103 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376444 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376444 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25827 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25827 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9600 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.016014 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25681 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9614 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.671209 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103990045500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016014 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376001 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376001 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25689 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25689 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25829 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25829 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25829 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25829 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10616 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10616 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10616 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10616 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10616 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10616 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 119043500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 119043500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 119043500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 119043500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 119043500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 119043500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36443 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36443 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25691 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25691 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25691 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25691 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10488 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10488 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10488 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10488 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10488 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10488 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116654500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116654500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116654500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 116654500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116654500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 116654500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36177 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36177 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36445 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36445 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36445 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36445 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.291304 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.291304 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.291288 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.291288 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.291288 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.291288 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11213.592690 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11213.592690 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11213.592690 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.289908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.289908 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.289892 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.289892 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.289892 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.289892 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11122.663997 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11122.663997 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2031 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2031 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10616 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10616 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10616 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10616 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10616 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10616 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97811500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97811500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97811500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97811500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97811500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97811500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.291304 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.291304 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.291288 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.291288 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9213.592690 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1936 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1936 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10488 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10488 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10488 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10488 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10488 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10488 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 95678500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 95678500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 95678500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 95678500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 95678500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 95678500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.289908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.289908 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.289892 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.289892 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109067 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.961436 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 135080 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109080 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.238357 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5099784110000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.961436 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810090 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810090 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135158 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 135158 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135158 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 135158 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135158 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 135158 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110111 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110111 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110111 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110111 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110111 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110111 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1384932000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1384932000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1384932000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1384932000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1384932000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1384932000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 245269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 245269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 245269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.448940 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.448940 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.448940 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.448940 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.448940 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.448940 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12577.598968 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12577.598968 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12577.598968 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 108181 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.959012 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 134869 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.246525 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959012 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809938 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809938 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134886 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 134886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134886 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 134886 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109218 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 109218 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109218 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 109218 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109218 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 109218 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1375116000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1375116000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1375116000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1375116000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1375116000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1375116000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244104 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 244104 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -800,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 36570 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 36570 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110111 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110111 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110111 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110111 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110111 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110111 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1164710000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1164710000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1164710000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.448940 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.448940 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.448940 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10577.598968 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35252 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35252 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109218 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109218 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109218 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 109218 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109218 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 109218 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1156680000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1156680000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1156680000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447424 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447424 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10590.561995 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1659765 # number of replacements -system.cpu.dcache.tagsinuse 511.990842 # Cycle average of tags in use -system.cpu.dcache.total_refs 19082473 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1660277 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.493548 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1660118 # number of replacements +system.cpu.dcache.tagsinuse 511.992206 # Cycle average of tags in use +system.cpu.dcache.total_refs 19078637 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1660630 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.488795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.990842 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999982 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999982 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10992813 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10992813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8084535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8084535 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19077348 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19077348 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19077348 # number of overall hits -system.cpu.dcache.overall_hits::total 19077348 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2235315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2235315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318075 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318075 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553390 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553390 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553390 # number of overall misses -system.cpu.dcache.overall_misses::total 2553390 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32075751500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32075751500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9669659497 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9669659497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41745410997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41745410997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41745410997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41745410997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13228128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13228128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8402610 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8402610 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21630738 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21630738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21630738 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21630738 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168982 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037854 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037854 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14349.544248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14349.544248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30400.564323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30400.564323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16349.014838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16349.014838 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 385443 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.992206 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10987895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10987895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8085738 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8085738 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19073633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19073633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19073633 # number of overall hits +system.cpu.dcache.overall_hits::total 19073633 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317957 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317957 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2554209 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2554209 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2554209 # number of overall misses +system.cpu.dcache.overall_misses::total 2554209 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32134007500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32134007500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9664278994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9664278994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41798286494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41798286494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41798286494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41798286494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13224147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13224147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8403695 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8403695 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21627842 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21627842 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21627842 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21627842 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037835 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037835 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118098 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118098 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118098 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118098 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14369.582453 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14369.582453 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30394.924452 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30394.924452 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16364.473892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16364.473892 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 400642 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42285 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42486 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.115360 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.429977 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1561573 # number of writebacks -system.cpu.dcache.writebacks::total 1561573 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863477 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169768 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 186663 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5701045 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 968087231 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2080048452 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3054150983 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37901173 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37901173 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235111902 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235111902 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5701045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968087231 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7315160354 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8289262885 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5701045 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968087231 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7315160354 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8289262885 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187415500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187415500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308505000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308505000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495920500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495920500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026899 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.914562 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.914562 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066271 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57487.365261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56400.446095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56794.997359 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.976713 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.976713 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39394.918292 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39394.918292 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index e72c9ec7f..fbbf2dd62 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.204983 # Nu sim_ticks 5204982530500 # Number of ticks simulated final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181134 # Simulator instruction rate (inst/s) -host_op_rate 347511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8731335326 # Simulator tick rate (ticks/s) -host_mem_usage 804468 # Number of bytes of host memory used -host_seconds 596.13 # Real time elapsed on the host +host_inst_rate 107235 # Simulator instruction rate (inst/s) +host_op_rate 205734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5169140013 # Simulator tick rate (ticks/s) +host_mem_usage 810688 # Number of bytes of host memory used +host_seconds 1006.93 # Real time elapsed on the host sim_insts 107979054 # Number of instructions simulated sim_ops 207160582 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory @@ -123,26 +123,13 @@ system.physmem.readPktSize::3 298 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 512 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 48406 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 46736 # Categorize write packet sizes system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see @@ -175,7 +162,6 @@ system.physmem.rdQLenPdf::28 2 # Wh system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see @@ -208,15 +194,14 @@ system.physmem.wrQLenPdf::28 36 # Wh system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40946729 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 52545479 # Sum of mem lat for all requests +system.physmem.totQLat 40945522 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 52544272 # Sum of mem lat for all requests system.physmem.totBusLat 4050000 # Total cycles spent in databus access system.physmem.totBankLat 7548750 # Total cycles spent in bank access -system.physmem.avgQLat 50551.52 # Average queueing delay per request +system.physmem.avgQLat 50550.03 # Average queueing delay per request system.physmem.avgBankLat 9319.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 64870.96 # Average memory access latency +system.physmem.avgMemAccLat 64869.47 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s |