diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1662 |
1 files changed, 831 insertions, 831 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index c2225df75..ef4c69b34 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.167942 # Number of seconds simulated -sim_ticks 5167941639500 # Number of ticks simulated -final_tick 5167941639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.163939 # Number of seconds simulated +sim_ticks 5163939423500 # Number of ticks simulated +final_tick 5163939423500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128954 # Simulator instruction rate (inst/s) -host_op_rate 254914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633898837 # Simulator tick rate (ticks/s) -host_mem_usage 412792 # Number of bytes of host memory used -host_seconds 3162.95 # Real time elapsed on the host -sim_insts 407876198 # Number of instructions simulated -sim_ops 806280456 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2473280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory +host_inst_rate 202828 # Simulator instruction rate (inst/s) +host_op_rate 400952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2568035232 # Simulator tick rate (ticks/s) +host_mem_usage 368532 # Number of bytes of host memory used +host_seconds 2010.85 # Real time elapsed on the host +sim_insts 407858031 # Number of instructions simulated +sim_ops 806254969 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2460224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1074496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10579456 # Number of bytes read from this memory -system.physmem.bytes_read::total 14130624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1074496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1074496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9348288 # Number of bytes written to this memory -system.physmem.bytes_written::total 9348288 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38645 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1069888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10576384 # Number of bytes read from this memory +system.physmem.bytes_read::total 14109824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1069888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1069888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9320448 # Number of bytes written to this memory +system.physmem.bytes_written::total 9320448 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38441 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16789 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165304 # Number of read requests responded to by this memory -system.physmem.num_reads::total 220791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 146067 # Number of write requests responded to by this memory -system.physmem.num_writes::total 146067 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 478581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 582 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165256 # Number of read requests responded to by this memory +system.physmem.num_reads::total 220466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145632 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145632 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 570 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 207916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2047131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2734285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1808900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1808900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1808900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 478581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 207184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2048123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2732376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1804910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1804910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1804910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 570 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2047131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4543184 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 109808 # number of replacements -system.l2c.tagsinuse 64836.655656 # Cycle average of tags in use -system.l2c.total_refs 3979638 # Total number of references to valid blocks. -system.l2c.sampled_refs 173786 # Sample count of references to valid blocks. -system.l2c.avg_refs 22.899647 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 109190 # number of replacements +system.l2c.tagsinuse 64839.015299 # Cycle average of tags in use +system.l2c.total_refs 3984882 # Total number of references to valid blocks. +system.l2c.sampled_refs 173424 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.977685 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50087.148367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 11.882077 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.155165 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3382.932484 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11354.537562 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.764269 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000181 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051619 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.173256 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989329 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 103999 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8349 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1054675 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1347003 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2514026 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1610152 # number of Writeback hits -system.l2c.Writeback_hits::total 1610152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 315 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 315 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 158022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 158022 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 103999 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1054675 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1505025 # number of demand (read+write) hits -system.l2c.demand_hits::total 2672048 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 103999 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8349 # number of overall hits -system.l2c.overall_hits::cpu.inst 1054675 # number of overall hits -system.l2c.overall_hits::cpu.data 1505025 # number of overall hits -system.l2c.overall_hits::total 2672048 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989365 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2515284 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1610495 # number of Writeback hits +system.l2c.Writeback_hits::total 1610495 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 158131 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1505908 # number of demand (read+write) hits +system.l2c.demand_hits::total 2673415 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 103321 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 8437 # number of overall hits +system.l2c.overall_hits::cpu.inst 1055749 # number of overall hits +system.l2c.overall_hits::cpu.data 1505908 # number of overall hits +system.l2c.overall_hits::total 2673415 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16790 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35954 # number of ReadReq misses -system.l2c.ReadReq_misses::total 52797 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3370 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3370 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 130295 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130295 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 47 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu.inst 16718 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 35983 # number of ReadReq misses +system.l2c.ReadReq_misses::total 52753 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 3384 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3384 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 130218 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130218 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16790 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 166249 # number of demand (read+write) misses -system.l2c.demand_misses::total 183092 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 47 # number of overall misses +system.l2c.demand_misses::cpu.inst 16718 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 166201 # number of demand (read+write) misses +system.l2c.demand_misses::total 182971 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 46 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses -system.l2c.overall_misses::cpu.inst 16790 # number of overall misses -system.l2c.overall_misses::cpu.data 166249 # number of overall misses -system.l2c.overall_misses::total 183092 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2467000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu.inst 16718 # number of overall misses +system.l2c.overall_misses::cpu.data 166201 # number of overall misses +system.l2c.overall_misses::total 182971 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2414500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 890951999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1919150991 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2812882490 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 39655500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39655500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6791571999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6791571999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2467000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 887508500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1921141998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2811377498 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 38315000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 38315000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6787419499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6787419499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2414500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 890951999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8710722990 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9604454489 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2467000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 887508500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8708561497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9598796997 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2414500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 890951999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8710722990 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9604454489 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 104046 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 8355 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1071465 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1382957 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2566823 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1610152 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1610152 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 3685 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3685 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 288317 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 288317 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 104046 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 8355 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1071465 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1671274 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2855140 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 104046 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 8355 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1071465 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1671274 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2855140 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000718 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.015670 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.025998 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.914518 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.914518 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.451916 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.451916 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000718 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.015670 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.099474 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.064127 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000718 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.015670 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.099474 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.064127 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.361702 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu.inst 887508500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8708561497 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9598796997 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 103367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 8443 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1072467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1383760 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2568037 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1610495 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1610495 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3721 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3721 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 288349 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 288349 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 103367 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40872.595092 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41157.459919 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41066.020722 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40119.436202 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40119.436202 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.744403 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.744403 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40351.063830 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40872.595092 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40312.023682 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40363.427076 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40351.063830 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40872.595092 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40312.023682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40363.427076 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47571 # number of replacements -system.iocache.tagsinuse 0.197047 # Cycle average of tags in use +system.iocache.replacements 47573 # number of replacements +system.iocache.tagsinuse 0.184801 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47587 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4996693441000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.197047 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012315 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012315 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses -system.iocache.ReadReq_misses::total 906 # number of ReadReq misses +system.iocache.warmup_cycle 4996693675000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.184801 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.011550 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.011550 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47626 # number of demand (read+write) misses -system.iocache.demand_misses::total 47626 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47626 # number of overall misses -system.iocache.overall_misses::total 47626 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136049932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 136049932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6913813160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6913813160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7049863092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7049863092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7049863092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7049863092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses +system.iocache.demand_misses::total 47628 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses +system.iocache.overall_misses::total 47628 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137681932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 137681932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9939428160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9939428160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10077110092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10077110092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10077110092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10077110092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47626 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47626 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47626 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47626 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150165.487859 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150165.487859 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147984.014555 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 147984.014555 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 148025.513207 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148025.513207 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 148025.513207 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151632.083700 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 151632.083700 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212744.609589 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 212744.609589 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 211579.534979 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 211579.534979 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72537008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8981 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8076.718406 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 906 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 908 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47626 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47626 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47626 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47626 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88906000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88906000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4484057918 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4484057918 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4572963918 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4572963918 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4572963918 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4572963918 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47628 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47628 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47628 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47628 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90434000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90434000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7509668946 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7509668946 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7600102946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7600102946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98130.242826 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98130.242826 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95977.267080 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 95977.267080 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96018.223617 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 96018.223617 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99596.916300 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 99596.916300 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160737.777098 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 160737.777098 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,141 +393,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 465854401 # number of cpu cycles simulated +system.cpu.numCycles 465816448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86523106 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86523106 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1197724 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 82002674 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79454296 # Number of BTB hits +system.cpu.BPredUnit.lookups 86514848 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86514848 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1196192 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 82053392 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79452542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31142494 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427260156 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86523106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79454296 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164033620 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5133412 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 157235 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 72542740 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 65499 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9290212 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 538342 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3947 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 271874324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.102439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31181464 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427226624 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86514848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79452542 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164016210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5124580 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 155814 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 72471814 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36433 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 65503 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9296745 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 539923 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4055 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 271815204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.102878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.406830 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 108271510 39.82% 39.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1601345 0.59% 40.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71956301 26.47% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 975717 0.36% 67.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1623613 0.60% 67.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2452165 0.90% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1122687 0.41% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1426947 0.52% 69.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82444039 30.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108229721 39.82% 39.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1589699 0.58% 40.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71960202 26.47% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971866 0.36% 67.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1623537 0.60% 67.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2454126 0.90% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1122252 0.41% 69.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1424890 0.52% 69.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82438911 30.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271874324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185730 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.917154 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34951113 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69967599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159705810 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3354905 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3894897 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840212837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1268 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3894897 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37909479 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43328722 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11932417 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159774211 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15034598 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836385126 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33598 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7166437 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5990052 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 17455 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 998119194 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816357971 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816357131 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 840 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964226207 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33892980 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468339 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476044 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 32058525 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336195 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10280230 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246899 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 991215 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 830038809 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1256743 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824423080 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186157 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23985276 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36420028 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 206597 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271874324 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.032368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.413899 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 271815204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185727 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.917157 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34976255 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 69906357 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159691682 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3353316 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3887594 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840157503 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1253 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3887594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37933620 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43316590 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11886084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159761513 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15029803 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836332638 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 33622 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7171271 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5982447 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16586 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998051723 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816227596 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816227024 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 572 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964187470 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33864246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467105 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 474137 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 32047540 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17336278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10273791 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1251259 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 987046 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829985579 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1254715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824362930 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 185325 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23972130 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36446956 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 204607 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 271815204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.032807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.413784 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82559406 30.37% 30.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18414875 6.77% 37.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10591768 3.90% 41.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7608288 2.80% 43.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75794422 27.88% 71.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3619554 1.33% 73.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72418483 26.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 726775 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140753 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82518813 30.36% 30.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18405041 6.77% 37.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10590940 3.90% 41.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7611334 2.80% 43.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75787785 27.88% 71.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3621369 1.33% 73.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72414876 26.64% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 725602 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 139444 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271874324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 271815204 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 331331 32.21% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547593 53.24% 85.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 149610 14.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 330736 32.15% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 548005 53.27% 85.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150045 14.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308279 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796609033 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308450 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796558014 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -556,246 +556,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18024617 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9481151 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18020026 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9476440 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824423080 # Type of FU issued -system.cpu.iq.rate 1.769701 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1028534 # FU busy when requested +system.cpu.iq.FU_type_0::total 824362930 # Type of FU issued +system.cpu.iq.rate 1.769716 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1028786 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1922068884 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 855291159 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819794003 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 201 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 398 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825143243 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 92 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1662305 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 1921889039 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 855222885 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819729616 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825083173 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1659720 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3372855 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25441 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1870494 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3372872 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11865 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1866399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1917611 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21826 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1917615 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3894897 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28837700 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2469058 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831295552 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338895 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336195 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10280230 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 727529 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1778064 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16969 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 715653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 628490 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1344143 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822456639 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17610649 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1966440 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3887594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28830241 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2469402 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831240294 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 338803 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17336278 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10273791 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725681 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1777576 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17730 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11865 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 713088 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 629130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1342218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822392031 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17604275 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1970898 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26845315 # number of memory reference insts executed -system.cpu.iew.exec_branches 83298308 # Number of branches executed -system.cpu.iew.exec_stores 9234666 # Number of stores executed -system.cpu.iew.exec_rate 1.765480 # Inst execution rate -system.cpu.iew.wb_sent 821926439 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819794057 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639752157 # num instructions producing a value -system.cpu.iew.wb_consumers 1045352654 # num instructions consuming a value +system.cpu.iew.exec_refs 26833761 # number of memory reference insts executed +system.cpu.iew.exec_branches 83292230 # Number of branches executed +system.cpu.iew.exec_stores 9229486 # Number of stores executed +system.cpu.iew.exec_rate 1.765485 # Inst execution rate +system.cpu.iew.wb_sent 821862423 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819729668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639700217 # num instructions producing a value +system.cpu.iew.wb_consumers 1045258728 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.759765 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611996 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759770 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612002 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24913133 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050144 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1202812 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267994872 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.008567 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.862606 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24883748 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1050106 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1201289 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267943051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.009053 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.862554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95708063 35.71% 35.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12360558 4.61% 40.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3940570 1.47% 41.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74894252 27.95% 69.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2417220 0.90% 70.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1553799 0.58% 71.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1057768 0.39% 71.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70929617 26.47% 98.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5133025 1.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95668224 35.70% 35.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12347484 4.61% 40.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3939395 1.47% 41.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74898098 27.95% 69.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2419496 0.90% 70.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1554494 0.58% 71.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1057385 0.39% 71.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70928163 26.47% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5130312 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267994872 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407876198 # Number of instructions committed -system.cpu.commit.committedOps 806280456 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267943051 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407858031 # Number of instructions committed +system.cpu.commit.committedOps 806254969 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22373073 # Number of memory references committed -system.cpu.commit.loads 13963337 # Number of loads committed -system.cpu.commit.membars 471701 # Number of memory barriers committed -system.cpu.commit.branches 82186197 # Number of branches committed +system.cpu.commit.refs 22370795 # Number of memory references committed +system.cpu.commit.loads 13963403 # Number of loads committed +system.cpu.commit.membars 471705 # Number of memory barriers committed +system.cpu.commit.branches 82181312 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735221140 # Number of committed integer instructions. +system.cpu.commit.int_insts 735195017 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5133025 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5130312 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1093976833 # The number of ROB reads -system.cpu.rob.rob_writes 1666301286 # The number of ROB writes -system.cpu.timesIdled 1419086 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 193980077 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9870026331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407876198 # Number of Instructions Simulated -system.cpu.committedOps 806280456 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407876198 # Number of Instructions Simulated -system.cpu.cpi 1.142147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.142147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.875544 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.875544 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508347107 # number of integer regfile reads -system.cpu.int_regfile_writes 977902256 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 265221380 # number of misc regfile reads -system.cpu.misc_regfile_writes 402568 # number of misc regfile writes -system.cpu.icache.replacements 1070981 # number of replacements -system.cpu.icache.tagsinuse 510.788530 # Cycle average of tags in use -system.cpu.icache.total_refs 8144587 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1071493 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.601157 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1093872885 # The number of ROB reads +system.cpu.rob.rob_writes 1666184214 # The number of ROB writes +system.cpu.timesIdled 1421273 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 194001244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9862059849 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407858031 # Number of Instructions Simulated +system.cpu.committedOps 806254969 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407858031 # Number of Instructions Simulated +system.cpu.cpi 1.142104 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.142104 # CPI: Total CPI of All Threads +system.cpu.ipc 0.875577 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.875577 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508209791 # number of integer regfile reads +system.cpu.int_regfile_writes 977816443 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.misc_regfile_reads 265196274 # number of misc regfile reads +system.cpu.misc_regfile_writes 402502 # number of misc regfile writes +system.cpu.icache.replacements 1071989 # number of replacements +system.cpu.icache.tagsinuse 510.817098 # Cycle average of tags in use +system.cpu.icache.total_refs 8149627 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072501 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.598713 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.788530 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997634 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997634 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8144587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8144587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8144587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8144587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8144587 # number of overall hits -system.cpu.icache.overall_hits::total 8144587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145619 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145619 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145619 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145619 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145619 # number of overall misses -system.cpu.icache.overall_misses::total 1145619 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18957217490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18957217490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18957217490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18957217490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18957217490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18957217490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9290206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9290206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9290206 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9290206 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9290206 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9290206 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123315 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123315 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123315 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123315 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123315 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123315 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16547.576018 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16547.576018 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16547.576018 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16547.576018 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16547.576018 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3193494 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.817098 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997690 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997690 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8149627 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8149627 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8149627 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8149627 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8149627 # number of overall hits +system.cpu.icache.overall_hits::total 8149627 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1147113 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1147113 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1147113 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1147113 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1147113 # number of overall misses +system.cpu.icache.overall_misses::total 1147113 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18981109491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18981109491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18981109491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18981109491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18981109491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18981109491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9296740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9296740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9296740 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9296740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9296740 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9296740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123389 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123389 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123389 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123389 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123389 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123389 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16546.852395 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16546.852395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16546.852395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16546.852395 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3167993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 401 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7885.170370 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7900.231920 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72182 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 72182 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 72182 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 72182 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 72182 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 72182 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1073437 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1073437 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1073437 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1073437 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1073437 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1073437 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14797672994 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14797672994 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14797672994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14797672994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14797672994 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14797672994 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115545 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115545 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115545 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115545 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13785.320418 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13785.320418 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13785.320418 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13785.320418 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13785.320418 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13785.320418 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72595 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 72595 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 72595 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 72595 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 72595 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 72595 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074518 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1074518 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1074518 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1074518 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1074518 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1074518 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14814669993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14814669993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14814669993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14814669993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14814669993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14814669993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115580 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115580 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115580 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13787.270193 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13787.270193 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9807 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.044173 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 32941 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9822 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.353798 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5136134294000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.044173 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377761 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.377761 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32940 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 32940 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9931 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.048032 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 33329 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9947 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 3.350658 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5125253660500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.048032 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.378002 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.378002 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 33326 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 33326 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32943 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 32943 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32943 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 32943 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10696 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10696 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10696 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10696 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10696 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10696 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176478000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176478000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176478000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 176478000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176478000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 176478000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43636 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 43636 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 33329 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 33329 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 33329 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 33329 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10825 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10825 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10825 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10825 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10825 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10825 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 178140000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 178140000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 178140000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 178140000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 178140000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 178140000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 44151 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 44151 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43639 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 43639 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43639 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 43639 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245119 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245119 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245102 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.245102 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245102 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.245102 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16499.439043 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16499.439043 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16499.439043 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16499.439043 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16499.439043 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16499.439043 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 44154 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 44154 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 44154 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 44154 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245181 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245181 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245165 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.245165 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245165 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.245165 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16456.351039 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16456.351039 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16456.351039 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16456.351039 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,78 +804,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1799 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1799 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10696 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10696 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10696 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10696 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10696 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10696 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143761538 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143761538 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143761538 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143761538 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143761538 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143761538 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245119 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245119 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245102 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245102 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245102 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13440.682311 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13440.682311 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13440.682311 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10825 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10825 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10825 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10825 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10825 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10825 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 145034027 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 145034027 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 145034027 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 145034027 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 145034027 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 145034027 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245181 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245181 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245165 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245165 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13398.062540 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109374 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.962684 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 139077 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109389 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.271398 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5108961672000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.962684 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810168 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.810168 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139087 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 139087 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139087 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 139087 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139087 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 139087 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110364 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110364 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110364 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110364 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110364 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110364 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2009314000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2009314000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2009314000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2009314000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2009314000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2009314000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249451 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 249451 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249451 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 249451 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249451 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 249451 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442428 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442428 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442428 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442428 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442428 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442428 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18206.244790 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18206.244790 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18206.244790 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18206.244790 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 109056 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.865602 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 139886 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 109072 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.282511 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5108962066000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.865602 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866600 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.866600 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139886 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 139886 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 139886 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139886 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 139886 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110096 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 110096 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110096 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 110096 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110096 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 110096 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2001823500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2001823500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2001823500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2001823500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2001823500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2001823500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249982 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 249982 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249982 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 249982 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249982 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 249982 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.440416 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.440416 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.440416 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.440416 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.440416 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.440416 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18182.527067 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18182.527067 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18182.527067 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -884,146 +884,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35688 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35688 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110364 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110364 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110364 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110364 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110364 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110364 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1675589507 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1675589507 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1675589507 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1675589507 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442428 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442428 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442428 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442428 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15182.391967 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15182.391967 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15182.391967 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35215 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35215 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110096 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110096 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110096 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 110096 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110096 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 110096 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1668892003 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1668892003 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1668892003 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.440416 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.440416 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.440416 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15158.516231 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1671342 # number of replacements -system.cpu.dcache.tagsinuse 511.998194 # Cycle average of tags in use -system.cpu.dcache.total_refs 19219573 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1671854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.495964 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1672208 # number of replacements +system.cpu.dcache.tagsinuse 511.998155 # Cycle average of tags in use +system.cpu.dcache.total_refs 19212274 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1672720 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.485649 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.998194 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.998155 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11132776 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11132776 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8081984 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8081984 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19214760 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19214760 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19214760 # number of overall hits -system.cpu.dcache.overall_hits::total 19214760 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2269875 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2269875 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318465 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318465 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2588340 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2588340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2588340 # number of overall misses -system.cpu.dcache.overall_misses::total 2588340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48782293500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48782293500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10759861985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10759861985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 59542155485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 59542155485 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 59542155485 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 59542155485 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13402651 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13402651 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8400449 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8400449 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21803100 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21803100 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21803100 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21803100 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037910 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037910 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21491.180572 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21491.180572 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33786.638987 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33786.638987 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23003.993094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23003.993094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23003.993094 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 188390485 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 11127928 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11127928 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8079547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8079547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19207475 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19207475 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19207475 # number of overall hits +system.cpu.dcache.overall_hits::total 19207475 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2271021 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2271021 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318564 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318564 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2589585 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2589585 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2589585 # number of overall misses +system.cpu.dcache.overall_misses::total 2589585 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48812772000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48812772000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10760956984 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10760956984 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 59573728984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 59573728984 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 59573728984 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 59573728984 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13398949 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13398949 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398111 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398111 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21797060 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21797060 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21797060 # 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average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33779.576424 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23005.125912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23005.125912 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 188289984 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 47569 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 47618 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3960.362526 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3954.176656 # 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35436211009 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2475863500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2475863500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211259000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211259000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034768 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034768 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076933 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076933 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18759.244567 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18759.244567 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32385.287653 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32385.287653 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |