diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
| commit | d6283445744d5be2a9ac33f0adbc729d48e22c40 (patch) | |
| tree | 67910602fd144f50fa86b1c8a90e0e4f0e66ee90 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | cf5935445f23d0ba2f41debc50952fe45d7c9f4a (diff) | |
| download | gem5-d6283445744d5be2a9ac33f0adbc729d48e22c40.tar.xz | |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1724 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt | 188 |
2 files changed, 956 insertions, 956 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index d3e4451ad..2d55f3c33 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.172910 # Number of seconds simulated -sim_ticks 5172910256500 # Number of ticks simulated -final_tick 5172910256500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.172174 # Number of seconds simulated +sim_ticks 5172174196500 # Number of ticks simulated +final_tick 5172174196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136129 # Simulator instruction rate (inst/s) -host_op_rate 268264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1651021148 # Simulator tick rate (ticks/s) -host_mem_usage 373420 # Number of bytes of host memory used -host_seconds 3133.16 # Real time elapsed on the host -sim_insts 426513995 # Number of instructions simulated -sim_ops 840512563 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +host_inst_rate 197854 # Simulator instruction rate (inst/s) +host_op_rate 391125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2509698416 # Simulator tick rate (ticks/s) +host_mem_usage 367744 # Number of bytes of host memory used +host_seconds 2060.87 # Real time elapsed on the host +sim_insts 407751921 # Number of instructions simulated +sim_ops 806059216 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2469504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1067584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10442240 # Number of bytes read from this memory -system.physmem.bytes_read::total 13977280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1067584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1067584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9176384 # Number of bytes written to this memory -system.physmem.bytes_written::total 9176384 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1070336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10446016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13989120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1070336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1070336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9206912 # Number of bytes written to this memory +system.physmem.bytes_written::total 9206912 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16681 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 163160 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218395 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143381 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 569 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16724 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 163219 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218580 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143858 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143858 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 477460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 544 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 206380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2018639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2702015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 206380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 206380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1773931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1773931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1773931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 206941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2019657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2704688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 206941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 206941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1780085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1780085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1780085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 477460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 544 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 206380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2018639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4475945 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 106892 # number of replacements -system.l2c.tagsinuse 64846.239814 # Cycle average of tags in use -system.l2c.total_refs 3994467 # Total number of references to valid blocks. -system.l2c.sampled_refs 171328 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.314735 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 206941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2019657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4484774 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 107330 # number of replacements +system.l2c.tagsinuse 64831.864344 # Cycle average of tags in use +system.l2c.total_refs 3982185 # Total number of references to valid blocks. +system.l2c.sampled_refs 171532 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.215406 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50145.406461 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 11.508776 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.169764 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3382.865025 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11306.289787 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.765158 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000176 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50277.913573 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 9.980895 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.169682 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3388.636576 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11155.163618 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.767180 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051618 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172520 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989475 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 113294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 9300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1056563 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1345318 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2524475 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1607595 # number of Writeback hits -system.l2c.Writeback_hits::total 1607595 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 334 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 334 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 163366 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 163366 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 113294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 9300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1056563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1508684 # number of demand (read+write) hits -system.l2c.demand_hits::total 2687841 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 113294 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 9300 # number of overall hits -system.l2c.overall_hits::cpu.inst 1056563 # number of overall hits -system.l2c.overall_hits::cpu.data 1508684 # number of overall hits -system.l2c.overall_hits::total 2687841 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.051706 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.170214 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989256 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 111938 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 8555 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 1051956 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1345107 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2517556 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1612922 # number of Writeback hits +system.l2c.Writeback_hits::total 1612922 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 325 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 325 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 163659 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 163659 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 111938 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 8555 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 1051956 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1508766 # number of demand (read+write) hits +system.l2c.demand_hits::total 2681215 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 111938 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 8555 # number of overall hits +system.l2c.overall_hits::cpu.inst 1051956 # number of overall hits +system.l2c.overall_hits::cpu.data 1508766 # number of overall hits +system.l2c.overall_hits::total 2681215 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16683 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35188 # number of ReadReq misses -system.l2c.ReadReq_misses::total 51924 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2935 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2935 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 128896 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128896 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu.inst 16726 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 35201 # number of ReadReq misses +system.l2c.ReadReq_misses::total 51978 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1498 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1498 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 128962 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128962 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16683 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 164084 # number of demand (read+write) misses -system.l2c.demand_misses::total 180820 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 46 # number of overall misses +system.l2c.demand_misses::cpu.inst 16726 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 164163 # number of demand (read+write) misses +system.l2c.demand_misses::total 180940 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 44 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu.inst 16683 # number of overall misses -system.l2c.overall_misses::cpu.data 164084 # number of overall misses -system.l2c.overall_misses::total 180820 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2412500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu.inst 16726 # number of overall misses +system.l2c.overall_misses::cpu.data 164163 # number of overall misses +system.l2c.overall_misses::total 180940 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2308000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 885747500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1875717995 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2764241995 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 38348000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 38348000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6718316497 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6718316497 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2412500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 887926997 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1876685493 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2767284490 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 37648500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 37648500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6721908000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6721908000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 2308000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 885747500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8594034492 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9482558492 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2412500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 887926997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8598593493 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9489192490 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 2308000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 885747500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8594034492 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9482558492 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 113340 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 9307 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1073246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1380506 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2576399 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1607595 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1607595 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 3269 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3269 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 292262 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292262 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 113340 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 9307 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1073246 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1672768 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2868661 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 113340 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 9307 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1073246 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1672768 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020227 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821722 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821722 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440713 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.440713 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063217 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000393 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000818 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015649 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.098128 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063217 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40901.174990 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41085.727655 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 41025.538780 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40147.700170 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40147.700170 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40075.351446 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.351446 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40897.452583 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41093.153409 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41029.389072 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40272.696929 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40272.696929 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40077.631395 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40077.631395 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40901.174990 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40292.022934 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40348.194578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40897.452583 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.382001 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40351.028242 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47569 # number of replacements -system.iocache.tagsinuse 0.199376 # Cycle average of tags in use +system.iocache.replacements 47572 # number of replacements +system.iocache.tagsinuse 0.197153 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5000598404000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.199376 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012461 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012461 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.warmup_cycle 5000849406000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.197153 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012322 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012322 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 907 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses -system.iocache.demand_misses::total 47624 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses -system.iocache.overall_misses::total 47624 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135906932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 135906932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6908833160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6908833160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7044740092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7044740092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7044740092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7044740092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses +system.iocache.demand_misses::total 47627 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses +system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136172932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 136172932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6920648160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6920648160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7056821092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7056821092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7056821092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7056821092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150339.526549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150339.526549 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147877.422089 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 147877.422089 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 147924.157820 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147924.157820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 147924.157820 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150135.536935 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150135.536935 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148130.311644 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 148130.311644 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 148168.498793 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148168.498793 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 148168.498793 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -348,22 +348,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47624 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47624 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47624 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47624 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88867000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88867000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4479079912 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4479079912 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4567946912 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4567946912 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4567946912 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47627 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47627 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47627 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47627 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88977000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88977000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4490887946 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4490887946 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4579864946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4579864946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4579864946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98304.203540 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98304.203540 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95870.717295 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 95870.717295 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 95916.909793 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98100.330761 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98100.330761 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96123.457748 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 96123.457748 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 96161.104961 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,411 +393,411 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 473223088 # number of cpu cycles simulated +system.cpu.numCycles 475031565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90016360 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90016360 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1178248 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84343978 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81707122 # Number of BTB hits +system.cpu.BPredUnit.lookups 86684856 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86684856 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1176632 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 82122133 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79543196 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31356562 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 446929489 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90016360 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81707122 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169790434 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5330018 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 171751 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 104797996 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37968 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 45006 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 453 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9363044 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 536807 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5287 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 310312997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.834177 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376352 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31269539 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 428184771 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86684856 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79543196 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164289785 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5325147 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 164614 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 76824227 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 45914 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9378048 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 536886 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4957 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 276741596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.053538 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.401990 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140957479 45.42% 45.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1776597 0.57% 46.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72781994 23.45% 69.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 982988 0.32% 69.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1642902 0.53% 70.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3674853 1.18% 71.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1139478 0.37% 71.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1444103 0.47% 72.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85912603 27.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 112886536 40.79% 40.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1619655 0.59% 41.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71962795 26.00% 67.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 983886 0.36% 67.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1644119 0.59% 68.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2486257 0.90% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1139995 0.41% 69.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1450599 0.52% 70.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82567754 29.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 310312997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.190220 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.944437 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36508708 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100881020 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164105770 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4704672 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4112827 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876214899 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4112827 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40925858 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 44314017 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11153757 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 163784094 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46022444 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872421528 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10519 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35242822 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3962452 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 32001317 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1394162179 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2488413918 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2488413062 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 856 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347546247 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46615925 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 471039 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 478955 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48145791 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18923985 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10455746 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1291287 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1021115 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865765672 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1722965 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864313181 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123185 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26037339 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53671952 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 207307 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 310312997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.785295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.396376 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 276741596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.182482 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.901382 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35010017 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 74311956 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159865423 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3444346 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4109854 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 841785392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 993 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4109854 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38173067 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 41532647 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11823127 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159691932 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 21410969 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 837988743 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10561 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14331873 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3961467 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8380256 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1328629800 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2380702001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2380701417 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 584 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1282020322 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46609471 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469457 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 477289 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 33840968 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17569417 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10446486 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246814 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1007946 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 831743249 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1259421 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823989117 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123035 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26027822 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53490149 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 209479 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 276741596 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.977468 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.409448 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 102585339 33.06% 33.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23772488 7.66% 40.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 19036495 6.13% 46.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7825788 2.52% 49.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80603332 25.97% 75.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3104423 1.00% 76.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72752969 23.45% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 520222 0.17% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 111941 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 86092872 31.11% 31.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17946523 6.48% 37.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 12957239 4.68% 42.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7826219 2.83% 45.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 76249367 27.55% 72.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3109383 1.12% 73.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 71927366 25.99% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 520136 0.19% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 112491 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 310312997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 276741596 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164594 7.88% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1764434 84.50% 92.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159044 7.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 163103 18.01% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 583729 64.45% 82.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 158924 17.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 296261 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829427794 95.96% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25158656 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9430470 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 296041 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796340985 96.64% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17916922 2.17% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9435169 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864313181 # Type of FU issued -system.cpu.iq.rate 1.826439 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2088072 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002416 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041288204 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893536846 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853917717 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 410 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866104816 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1579729 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823989117 # Type of FU issued +system.cpu.iq.rate 1.734599 # Inst issue rate +system.cpu.iq.fu_busy_cnt 905756 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1925886604 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 859041376 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819484767 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 824598744 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1578458 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3631905 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20141 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12168 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2053612 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3618337 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20593 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12016 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2047079 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821470 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4399 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1917340 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4451 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4112827 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27932530 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1927286 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867488637 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 301587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18923985 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10455746 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 885039 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 975379 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15665 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12168 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 701708 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 624080 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1325788 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862427395 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24732275 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1885785 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4109854 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27168187 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1772103 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 833002670 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 300864 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17569417 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10446486 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 728436 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 974858 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15486 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12016 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 697910 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 625387 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1323297 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822095189 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17489841 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1893927 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33921373 # number of memory reference insts executed -system.cpu.iew.exec_branches 86494176 # Number of branches executed -system.cpu.iew.exec_stores 9189098 # Number of stores executed -system.cpu.iew.exec_rate 1.822454 # Inst execution rate -system.cpu.iew.wb_sent 861944484 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853917813 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669630870 # num instructions producing a value -system.cpu.iew.wb_consumers 1918703675 # num instructions consuming a value +system.cpu.iew.exec_refs 26681633 # number of memory reference insts executed +system.cpu.iew.exec_branches 83151598 # Number of branches executed +system.cpu.iew.exec_stores 9191792 # Number of stores executed +system.cpu.iew.exec_rate 1.730612 # Inst execution rate +system.cpu.iew.wb_sent 821608460 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819484817 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640296111 # num instructions producing a value +system.cpu.iew.wb_consumers 1828731330 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.804472 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back +system.cpu.iew.wb_rate 1.725117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.350131 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426513995 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840512563 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26872606 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515656 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1183314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 306215725 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.744838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.861126 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 407751921 # The number of committed instructions +system.cpu.commit.commitCommittedOps 806059216 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26839677 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1049940 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1181775 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 272647181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.956419 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.843352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 125266635 40.91% 40.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14734551 4.81% 45.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4258737 1.39% 47.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76646765 25.03% 72.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3892941 1.27% 73.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1792387 0.59% 74.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1104205 0.36% 74.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71994718 23.51% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6524786 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 98573076 36.15% 36.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13223290 4.85% 41.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4246957 1.56% 42.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 75817327 27.81% 70.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2710299 0.99% 71.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1789124 0.66% 72.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1087866 0.40% 72.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71017917 26.05% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4181325 1.53% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 306215725 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426513995 # Number of instructions committed -system.cpu.commit.committedOps 840512563 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 272647181 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407751921 # Number of instructions committed +system.cpu.commit.committedOps 806059216 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23694211 # Number of memory references committed -system.cpu.commit.loads 15292077 # Number of loads committed -system.cpu.commit.membars 781571 # Number of memory barriers committed -system.cpu.commit.branches 85505598 # Number of branches committed +system.cpu.commit.refs 22350484 # Number of memory references committed +system.cpu.commit.loads 13951077 # Number of loads committed +system.cpu.commit.membars 471695 # Number of memory barriers committed +system.cpu.commit.branches 82163258 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768332766 # Number of committed integer instructions. +system.cpu.commit.int_insts 735013406 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6524786 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4181325 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1166996622 # The number of ROB reads -system.cpu.rob.rob_writes 1738897212 # The number of ROB writes -system.cpu.timesIdled 2997983 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162910091 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9872594876 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426513995 # Number of Instructions Simulated -system.cpu.committedOps 840512563 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426513995 # Number of Instructions Simulated -system.cpu.cpi 1.109514 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.109514 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901296 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.901296 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163164515 # number of integer regfile reads -system.cpu.int_regfile_writes 1362660599 # number of integer regfile writes -system.cpu.fp_regfile_reads 96 # number of floating regfile reads -system.cpu.misc_regfile_reads 281055752 # number of misc regfile reads -system.cpu.misc_regfile_writes 403699 # number of misc regfile writes -system.cpu.icache.replacements 1072786 # number of replacements -system.cpu.icache.tagsinuse 510.225454 # Cycle average of tags in use -system.cpu.icache.total_refs 8218240 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1073298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.656997 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56932893000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.225454 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996534 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996534 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8218240 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8218240 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8218240 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8218240 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8218240 # number of overall hits -system.cpu.icache.overall_hits::total 8218240 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1144801 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1144801 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1144801 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1144801 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1144801 # number of overall misses -system.cpu.icache.overall_misses::total 1144801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18871083485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18871083485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18871083485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18871083485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18871083485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18871083485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9363041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9363041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9363041 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9363041 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9363041 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9363041 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122268 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122268 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122268 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122268 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122268 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122268 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16484.160553 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16484.160553 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16484.160553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16484.160553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16484.160553 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3261491 # number of cycles access was blocked +system.cpu.rob.rob_reads 1101286190 # The number of ROB reads +system.cpu.rob.rob_writes 1669922447 # The number of ROB writes +system.cpu.timesIdled 1659907 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 198289969 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9869314281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407751921 # Number of Instructions Simulated +system.cpu.committedOps 806059216 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407751921 # Number of Instructions Simulated +system.cpu.cpi 1.165001 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.165001 # CPI: Total CPI of All Threads +system.cpu.ipc 0.858368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.858368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2053713870 # number of integer regfile reads +system.cpu.int_regfile_writes 1297159076 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.misc_regfile_reads 265135377 # number of misc regfile reads +system.cpu.misc_regfile_writes 402339 # number of misc regfile writes +system.cpu.icache.replacements 1068223 # number of replacements +system.cpu.icache.tagsinuse 510.418027 # Cycle average of tags in use +system.cpu.icache.total_refs 8239400 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1068735 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.709488 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 57281567000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.418027 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996910 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996910 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8239400 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8239400 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8239400 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8239400 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8239400 # number of overall hits +system.cpu.icache.overall_hits::total 8239400 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1138645 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1138645 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1138645 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1138645 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1138645 # number of overall misses +system.cpu.icache.overall_misses::total 1138645 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18814976480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18814976480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18814976480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18814976480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18814976480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18814976480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9378045 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9378045 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9378045 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9378045 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9378045 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9378045 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121416 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121416 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121416 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121416 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121416 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121416 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16524.005709 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16524.005709 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16524.005709 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16524.005709 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16524.005709 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3200487 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 378 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 386 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8628.283069 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8291.417098 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69972 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69972 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69972 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69972 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69972 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69972 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074829 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1074829 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1074829 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1074829 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1074829 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1074829 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14733142991 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14733142991 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14733142991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14733142991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14733142991 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14733142991 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114795 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114795 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114795 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114795 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13707.429732 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13707.429732 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13707.429732 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13707.429732 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69787 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69787 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69787 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69787 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69787 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69787 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1068858 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1068858 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1068858 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1068858 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1068858 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1068858 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14704003987 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14704003987 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14704003987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14704003987 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14704003987 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14704003987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113975 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.113975 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113975 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.113975 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13756.742230 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13756.742230 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13756.742230 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13756.742230 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 11223 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.037503 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 31260 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 11237 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.781881 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5131387386000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.037503 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.377344 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.377344 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31468 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 31468 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 10021 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.028958 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 32291 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 10034 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 3.218158 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5136098133000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.028958 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376810 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376810 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 32310 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 32310 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31471 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 31471 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31471 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 31471 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12107 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 12107 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12107 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 12107 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12107 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 12107 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 196957000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 196957000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 196957000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 196957000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 196957000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 196957000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43575 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 43575 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 32313 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 32313 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 32313 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 32313 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10911 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10911 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10911 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10911 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10911 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10911 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183901500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183901500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183901500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 183901500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183901500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 183901500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43578 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 43578 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43578 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 43578 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.277843 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.277843 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.277824 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.277824 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.277824 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.277824 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16268.026761 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16268.026761 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16268.026761 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16268.026761 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16268.026761 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43224 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 43224 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43224 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 43224 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.252447 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.252447 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.252429 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.252429 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.252429 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.252429 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16854.687930 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16854.687930 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16854.687930 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16854.687930 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16854.687930 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,78 +806,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1700 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1700 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12107 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12107 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12107 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 12107 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12107 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 12107 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159950045 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159950045 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159950045 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159950045 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159950045 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159950045 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.277843 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.277843 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.277824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.277824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.277824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13211.369043 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13211.369043 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13211.369043 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1563 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1563 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10911 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10911 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10911 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10911 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10911 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10911 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 150559535 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 150559535 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 150559535 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 150559535 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 150559535 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 150559535 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.252447 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.252447 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.252429 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.252429 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.252429 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13798.875905 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13798.875905 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13798.875905 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 118986 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.873264 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 132191 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 119002 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.110830 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5112880781000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.873264 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.867079 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.867079 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 132191 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 132191 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 132191 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 132191 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 132191 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 132191 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 120057 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 120057 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 120057 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 120057 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 120057 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 120057 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2156991000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2156991000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2156991000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2156991000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2156991000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2156991000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 252248 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 252248 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 252248 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 252248 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 252248 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 252248 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.475948 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.475948 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.475948 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.475948 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.475948 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.475948 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17966.390964 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17966.390964 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17966.390964 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17966.390964 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17966.390964 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 116564 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.971477 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 137576 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 116580 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.180100 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5113123336000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.971477 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810717 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.810717 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137576 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 137576 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137576 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 137576 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137576 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 137576 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117614 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 117614 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117614 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 117614 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117614 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 117614 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2140596500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2140596500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2140596500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2140596500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2140596500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2140596500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255190 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 255190 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255190 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 255190 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255190 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 255190 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.460888 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.460888 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.460888 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.460888 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.460888 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.460888 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18200.184502 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18200.184502 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18200.184502 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18200.184502 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18200.184502 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,146 +886,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 34205 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 34205 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 120057 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 120057 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 120057 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 120057 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 120057 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 120057 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1794187508 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1794187508 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1794187508 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1794187508 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.475948 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.475948 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.475948 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.475948 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14944.463946 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14944.463946 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 39184 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 39184 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117614 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117614 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117614 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 117614 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117614 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 117614 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1785080011 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1785080011 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1785080011 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1785080011 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.460888 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.460888 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.460888 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.460888 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15177.444956 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15177.444956 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1672900 # number of replacements -system.cpu.dcache.tagsinuse 511.996980 # Cycle average of tags in use -system.cpu.dcache.total_refs 19011613 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673412 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.360988 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1673020 # number of replacements +system.cpu.dcache.tagsinuse 511.997654 # Cycle average of tags in use +system.cpu.dcache.total_refs 19008279 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673532 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.358181 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996980 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10933058 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10933058 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8074504 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8074504 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19007562 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19007562 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19007562 # number of overall hits -system.cpu.dcache.overall_hits::total 19007562 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2431156 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2431156 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318255 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318255 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2749411 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2749411 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2749411 # number of overall misses -system.cpu.dcache.overall_misses::total 2749411 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45213675500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45213675500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10676522982 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10676522982 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55890198482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55890198482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55890198482 # 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average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20328.062440 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20328.062440 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20328.062440 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26730982 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.997654 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10932679 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10932679 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8073031 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8073031 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19005710 # 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average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18604.415901 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33437.034617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33437.034617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20316.256654 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.256654 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20316.256654 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27551492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4911 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4916 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5443.083282 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5604.453214 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1571690 # number of writebacks -system.cpu.dcache.writebacks::total 1571690 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049439 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1049439 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22786 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22786 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1072225 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1072225 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1072225 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1072225 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381717 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1381717 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295469 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 295469 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1677186 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1677186 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1677186 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1677186 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23302977034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23302977034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9408800483 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9408800483 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32711777517 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32711777517 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32711777517 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32711777517 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85208357000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85208357000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386111000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386111000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594468000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594468000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035205 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035205 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077087 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077087 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077087 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16865.231472 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16865.231472 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31843.612978 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31843.612978 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19503.965283 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19503.965283 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1572175 # number of writebacks +system.cpu.dcache.writebacks::total 1572175 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1048961 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1048961 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22710 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22710 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1071671 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1071671 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1071671 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1071671 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381483 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1381483 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294385 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 294385 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1675868 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1675868 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1675868 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1675868 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23305790513 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23305790513 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9339566493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9339566493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32645357006 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32645357006 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32645357006 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32645357006 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96733569500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96733569500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2477085000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2477085000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99210654500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99210654500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16870.124723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16870.124723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31725.687426 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31725.687426 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19479.670837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19479.670837 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 90df3051e..fd6a73c63 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305568 # Number of seconds simulated -sim_ticks 5305568377500 # Number of ticks simulated -final_tick 5305568377500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.309130 # Number of seconds simulated +sim_ticks 5309130431000 # Number of ticks simulated +final_tick 5309130431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148548 # Simulator instruction rate (inst/s) -host_op_rate 304739 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5673062484 # Simulator tick rate (ticks/s) -host_mem_usage 518516 # Number of bytes of host memory used -host_seconds 935.22 # Real time elapsed on the host -sim_insts 138925597 # Number of instructions simulated -sim_ops 284998538 # Number of ops (including micro ops) simulated +host_inst_rate 252383 # Simulator instruction rate (inst/s) +host_op_rate 484244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12393223655 # Simulator tick rate (ticks/s) +host_mem_usage 461792 # Number of bytes of host memory used +host_seconds 428.39 # Real time elapsed on the host +sim_insts 108118332 # Number of instructions simulated +sim_ops 207445228 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 843619360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40106316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 468873856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 53484588 # Number of bytes read from this memory -system.physmem.bytes_read::total 1406451096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 843619360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 468873856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1312493216 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 107024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 51696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 833139344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 64776128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 119080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 55640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 193794504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 32074945 # Number of bytes read from this memory +system.physmem.bytes_read::total 1124153521 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833139344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 193794504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1026933848 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 32433610 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 35512400 # Number of bytes written to this memory -system.physmem.bytes_written::total 70937130 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 44442078 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 25482673 # Number of bytes written to this memory +system.physmem.bytes_written::total 72915871 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 105452420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6721793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58609232 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8980167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 179805900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 104142418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 11379014 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14885 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 6955 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 24224313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4791752 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144579988 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4872539 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4951932 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9871209 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159006406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7559287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 88373916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10080840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265089618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159006406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 88373916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247380322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 6585171 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 3512759 # Number of write requests responded to by this memory +system.physmem.num_writes::total 10144668 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 20158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 9737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 156925763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12200892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 10480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 36502118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 6041469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 211739669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 156925763 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 36502118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 193427881 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 563389 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6113126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6693420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13370317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159006406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13672414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 88373916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16774261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278459935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 8370877 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 4799783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13734052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 20158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 9740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 156925763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 20571769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 10480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 36502118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 10841251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 225473721 # Total bandwidth to/from this memory (bytes/s) system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -114,52 +114,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10611136755 # number of cpu cycles simulated +system.cpu0.numCycles 10617406972 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 90467113 # Number of instructions committed -system.cpu0.committedOps 191744891 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 172320091 # Number of integer alu accesses +system.cpu0.committedInsts 89456821 # Number of instructions committed +system.cpu0.committedOps 172956710 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 163049245 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 18433408 # number of instructions that are conditional controls -system.cpu0.num_int_insts 172320091 # number of integer instructions +system.cpu0.num_conditional_control_insts 15979073 # number of instructions that are conditional controls +system.cpu0.num_int_insts 163049245 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 529438037 # number of times the integer registers were read -system.cpu0.num_int_register_writes 286410601 # number of times the integer registers were written +system.cpu0.num_int_register_reads 506406726 # number of times the integer registers were read +system.cpu0.num_int_register_writes 269974282 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 19683230 # number of memory refs -system.cpu0.num_load_insts 14799913 # Number of load instructions -system.cpu0.num_store_insts 4883317 # Number of store instructions -system.cpu0.num_idle_cycles 10087385086.886099 # Number of idle cycles -system.cpu0.num_busy_cycles 523751668.113901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles +system.cpu0.num_mem_refs 18821806 # number of memory refs +system.cpu0.num_load_insts 12224477 # Number of load instructions +system.cpu0.num_store_insts 6597329 # Number of store instructions +system.cpu0.num_idle_cycles 9900769036.140667 # Number of idle cycles +system.cpu0.num_busy_cycles 716637935.859333 # Number of busy cycles +system.cpu0.not_idle_fraction 0.067497 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.932503 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10608184676 # number of cpu cycles simulated +system.cpu1.numCycles 10618260862 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48458484 # Number of instructions committed -system.cpu1.committedOps 93253647 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88897203 # Number of integer alu accesses +system.cpu1.committedInsts 18661511 # Number of instructions committed +system.cpu1.committedOps 34488518 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 33823915 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8156142 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88897203 # number of integer instructions +system.cpu1.num_conditional_control_insts 2426468 # number of instructions that are conditional controls +system.cpu1.num_int_insts 33823915 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 272264147 # number of times the integer registers were read -system.cpu1.num_int_register_writes 138280138 # number of times the integer registers were written +system.cpu1.num_int_register_reads 103356389 # number of times the integer registers were read +system.cpu1.num_int_register_writes 49288010 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14383325 # number of memory refs -system.cpu1.num_load_insts 9129593 # Number of load instructions -system.cpu1.num_store_insts 5253732 # Number of store instructions -system.cpu1.num_idle_cycles 10274264583.773684 # Number of idle cycles -system.cpu1.num_busy_cycles 333920092.226317 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles +system.cpu1.num_mem_refs 8339462 # number of memory refs +system.cpu1.num_load_insts 4801557 # Number of load instructions +system.cpu1.num_store_insts 3537905 # Number of store instructions +system.cpu1.num_idle_cycles 10461852949.262030 # Number of idle cycles +system.cpu1.num_busy_cycles 156407912.737971 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014730 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985270 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |