diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-10 16:19:58 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-01-10 16:19:58 -0600 |
| commit | fc6d1f33990a240f136b39c5a4a8df6efa99af71 (patch) | |
| tree | 9c84da0bf3a4a2ec42ff73d057c1e79d66cfac55 /tests/long/fs/10.linux-boot/ref/x86 | |
| parent | 407f37e15f19a2da350a94272ac7739891e935f4 (diff) | |
| download | gem5-fc6d1f33990a240f136b39c5a4a8df6efa99af71.tar.xz | |
stats: updates due to changes to ruby
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86')
3 files changed, 604 insertions, 344 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini index b553a1c5b..f745e2f55 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.sys_port_proxy.slave[0] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -55,6 +60,7 @@ oem_table_id= [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -67,6 +73,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -91,16 +98,19 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu0.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.ruby.l1_cntrl0.sequencer.slave[3] @@ -108,32 +118,37 @@ port=system.ruby.l1_cntrl0.sequencer.slave[3] [system.cpu0.interrupts] type=X86LocalApic clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system -int_master=system.piobus.slave[4] +int_master=system.piobus.slave[3] int_slave=system.piobus.master[18] pio=system.piobus.master[17] [system.cpu0.isa] type=X86ISA +eventq_index=0 [system.cpu0.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.ruby.l1_cntrl0.sequencer.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -145,6 +160,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts @@ -169,16 +185,19 @@ icache_port=system.ruby.l1_cntrl1.sequencer.slave[0] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu1.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.ruby.l1_cntrl1.sequencer.slave[3] @@ -186,70 +205,82 @@ port=system.ruby.l1_cntrl1.sequencer.slave[3] [system.cpu1.interrupts] type=X86LocalApic clk_domain=system.cpu1.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system -int_master=system.piobus.slave[5] +int_master=system.piobus.slave[4] int_slave=system.piobus.master[20] pio=system.piobus.master[19] [system.cpu1.isa] type=X86ISA +eventq_index=0 [system.cpu1.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.ruby.l1_cntrl1.sequencer.slave[2] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -257,6 +288,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 base_entries33 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 system.intel_mp_table.base_entries33 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -269,6 +301,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -280,6 +313,7 @@ stepping=0 type=X86IntelMPProcessor bootstrap=false enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=1 @@ -291,6 +325,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=2 version=17 @@ -298,16 +333,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries05] type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -318,6 +356,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -328,6 +367,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -338,6 +378,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -348,6 +389,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -358,6 +400,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -368,6 +411,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -378,6 +422,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -388,6 +433,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -398,6 +444,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -408,6 +455,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -418,6 +466,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -428,6 +477,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -438,6 +488,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -448,6 +499,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -458,6 +510,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -468,6 +521,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -478,6 +532,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -488,6 +543,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -498,6 +554,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -508,6 +565,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -518,6 +576,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -528,6 +587,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -538,6 +598,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -548,6 +609,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -558,6 +620,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -568,6 +631,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -578,6 +642,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -588,6 +653,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=2 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -597,22 +663,26 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -631,6 +701,7 @@ pio=system.piobus.master[11] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -640,13 +711,7 @@ pio=system.piobus.master[12] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -655,6 +720,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -672,6 +738,7 @@ pio=system.piobus.master[13] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -689,6 +756,7 @@ pio=system.piobus.master[14] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -706,6 +774,7 @@ pio=system.piobus.master[15] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -723,6 +792,7 @@ pio=system.piobus.master[16] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -741,6 +811,7 @@ pio=system.piobus.master[10] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -753,6 +824,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -765,6 +837,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -774,10 +847,12 @@ pio=system.piobus.master[0] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -806,6 +881,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -815,8 +891,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -828,6 +936,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -836,7 +945,7 @@ pio_latency=30000 platform=system.pc system=system config=system.piobus.master[3] -dma=system.piobus.slave[0] +dma=system.ruby.dma_cntrl0.dma_sequencer.slave[0] pio=system.piobus.master[2] [system.pc.south_bridge.ide.disks0] @@ -844,19 +953,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -864,108 +976,126 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=2 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 pio_latency=100000 system=system -int_master=system.piobus.slave[1] +int_master=system.piobus.slave[0] pio=system.piobus.master[9] [system.pc.south_bridge.keyboard] @@ -974,6 +1104,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -983,14 +1114,17 @@ pio=system.piobus.master[4] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1001,11 +1135,13 @@ pio=system.piobus.master[5] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1016,11 +1152,13 @@ pio=system.piobus.master[6] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1029,10 +1167,12 @@ pio=system.piobus.master[7] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1051,6 +1191,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1062,40 +1203,48 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.piobus.master[21] [system.piobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 default=system.pc.pciconfig.pio master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.physmem.port -slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_port system.ruby.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master +slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_port system.ruby.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master [system.ruby] type=RubySystem -children=clk_domain dir_cntrl0 dma_cntrl0 l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network profiler +children=clk_domain dir_cntrl0 dma_cntrl0 l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network +all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false mem_size=134217728 no_mem_vec=false +num_of_sequencers=2 random_seed=1234 randomization=false -stats_filename=ruby.stats [system.ruby.clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -1103,9 +1252,10 @@ type=Directory_Controller children=directory memBuffer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=3 +cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=6 +eventq_index=0 memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 peer=Null @@ -1117,6 +1267,7 @@ version=0 [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory +eventq_index=0 map_levels=4 numa_high_bit=5 size=134217728 @@ -1133,6 +1284,7 @@ basic_bus_busy_time=2 clk_domain=system.ruby.memctrl_clk_domain dimm_bit_0=12 dimms_per_channel=2 +eventq_index=0 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -1150,8 +1302,9 @@ type=DMA_Controller children=dma_sequencer buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=4 +cluster_id=0 dma_sequencer=system.ruby.dma_cntrl0.dma_sequencer +eventq_index=0 number_of_TBEs=256 peer=Null recycle_latency=10 @@ -1164,6 +1317,7 @@ version=0 type=DMASequencer access_phys_mem=true clk_domain=system.ruby.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -1180,8 +1334,9 @@ L1Dcache=system.ruby.l1_cntrl0.L1Dcache L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=0 +cluster_id=0 enable_prefetch=false +eventq_index=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 @@ -1201,6 +1356,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -1215,6 +1371,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -1227,6 +1384,7 @@ tagArrayBanks=1 [system.ruby.l1_cntrl0.prefetcher] type=Prefetcher cross_page=false +eventq_index=0 nonunit_filter=8 num_startup_pfs=1 num_streams=4 @@ -1240,6 +1398,7 @@ access_phys_mem=true clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl0.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -1249,7 +1408,7 @@ system=system using_network_tester=false using_ruby_tester=false version=0 -pio_port=system.piobus.slave[2] +pio_port=system.piobus.slave[1] slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port [system.ruby.l1_cntrl1] @@ -1259,8 +1418,9 @@ L1Dcache=system.ruby.l1_cntrl1.L1Dcache L1Icache=system.ruby.l1_cntrl1.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=1 +cluster_id=0 enable_prefetch=false +eventq_index=0 l1_request_latency=2 l1_response_latency=2 l2_select_num_bits=0 @@ -1280,6 +1440,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=3 replacement_policy=PSEUDO_LRU @@ -1294,6 +1455,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=true latency=3 replacement_policy=PSEUDO_LRU @@ -1306,6 +1468,7 @@ tagArrayBanks=1 [system.ruby.l1_cntrl1.prefetcher] type=Prefetcher cross_page=false +eventq_index=0 nonunit_filter=8 num_startup_pfs=1 num_streams=4 @@ -1319,6 +1482,7 @@ access_phys_mem=true clk_domain=system.ruby.clk_domain dcache=system.ruby.l1_cntrl1.L1Dcache deadlock_threshold=500000 +eventq_index=0 icache=system.ruby.l1_cntrl1.L1Icache max_outstanding_requests=16 ruby_system=system.ruby @@ -1328,7 +1492,7 @@ system=system using_network_tester=false using_ruby_tester=false version=1 -pio_port=system.piobus.slave[3] +pio_port=system.piobus.slave[2] slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port [system.ruby.l2_cntrl0] @@ -1337,7 +1501,8 @@ children=L2cache L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain -cntrl_id=2 +cluster_id=0 +eventq_index=0 l2_request_latency=2 l2_response_latency=2 number_of_TBEs=256 @@ -1353,6 +1518,7 @@ type=RubyCache assoc=2 dataAccessLatency=1 dataArrayBanks=1 +eventq_index=0 is_icache=false latency=15 replacement_policy=PSEUDO_LRU @@ -1366,6 +1532,7 @@ tagArrayBanks=1 type=DerivedClockDomain clk_divider=3 clk_domain=system.ruby.clk_domain +eventq_index=0 [system.ruby.network] type=SimpleNetwork @@ -1375,6 +1542,7 @@ buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 endpoint_bandwidth=1000 +eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 number_of_virtual_networks=10 @@ -1385,6 +1553,7 @@ topology=Crossbar [system.ruby.network.ext_links0] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl0 int_node=system.ruby.network.routers0 latency=1 @@ -1394,6 +1563,7 @@ weight=1 [system.ruby.network.ext_links1] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l1_cntrl1 int_node=system.ruby.network.routers1 latency=1 @@ -1403,6 +1573,7 @@ weight=1 [system.ruby.network.ext_links2] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.l2_cntrl0 int_node=system.ruby.network.routers2 latency=1 @@ -1412,6 +1583,7 @@ weight=1 [system.ruby.network.ext_links3] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dir_cntrl0 int_node=system.ruby.network.routers3 latency=1 @@ -1421,6 +1593,7 @@ weight=1 [system.ruby.network.ext_links4] type=SimpleExtLink bandwidth_factor=16 +eventq_index=0 ext_node=system.ruby.dma_cntrl0 int_node=system.ruby.network.routers4 latency=1 @@ -1430,6 +1603,7 @@ weight=1 [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=5 node_a=system.ruby.network.routers0 @@ -1439,6 +1613,7 @@ weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=6 node_a=system.ruby.network.routers1 @@ -1448,6 +1623,7 @@ weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=7 node_a=system.ruby.network.routers2 @@ -1457,6 +1633,7 @@ weight=1 [system.ruby.network.int_links3] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=8 node_a=system.ruby.network.routers3 @@ -1466,6 +1643,7 @@ weight=1 [system.ruby.network.int_links4] type=SimpleIntLink bandwidth_factor=16 +eventq_index=0 latency=1 link_id=9 node_a=system.ruby.network.routers4 @@ -1475,49 +1653,49 @@ weight=1 [system.ruby.network.routers0] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=0 virt_nets=10 [system.ruby.network.routers1] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=1 virt_nets=10 [system.ruby.network.routers2] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=2 virt_nets=10 [system.ruby.network.routers3] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=3 virt_nets=10 [system.ruby.network.routers4] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=4 virt_nets=10 [system.ruby.network.routers5] type=Switch clk_domain=system.ruby.clk_domain +eventq_index=0 router_id=5 virt_nets=10 -[system.ruby.profiler] -type=RubyProfiler -all_instructions=false -hot_lines=false -num_of_sequencers=2 -ruby_system=system.ruby - [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1528,6 +1706,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1540,6 +1719,7 @@ version= type=RubyPortProxy access_phys_mem=true clk_domain=system.clk_domain +eventq_index=0 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -1551,5 +1731,6 @@ slave=system.system_port [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats deleted file mode 100644 index b875fcf13..000000000 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats +++ /dev/null @@ -1,58 +0,0 @@ - -Profiler Stats --------------- -Ruby_current_time: 10600871471 -Ruby_start_time: 0 -Ruby_cycles: 10600871471 - -Busy Controller Counts: -L1Cache-0:12 L1Cache-1:13 -L2Cache-0:2 -Directory-0:0 -DMA-0:0 - -Busy Bank Count:0 - -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 152187620 average: 1.00011 | standard deviation: 0.0105957 | 0 152170533 17087 ] - -All Non-Zero Cycle Demand Cache Accesses ----------------------------------------- -latency: [binsize: 16 max: 175 count: 152187619 average: 3.38032 | standard deviation: 3.78105 | 149532617 2479919 181 0 78486 1293 90363 3753 944 61 2 ] -latency: LD: [binsize: 8 max: 144 count: 14921275 average: 4.75297 | standard deviation: 6.60507 | 13535742 0 1328034 25221 131 0 0 0 0 9977 145 16 20 20925 775 45 44 172 28 ] -latency: ST: [binsize: 16 max: 175 count: 9491432 average: 4.60863 | standard deviation: 10.6418 | 9141416 224288 30 0 63466 1078 57802 2705 612 33 2 ] -latency: IFETCH: [binsize: 8 max: 143 count: 126601627 average: 3.11268 | standard deviation: 1.65139 | 125785924 0 800296 97 4 0 0 0 0 3861 27 4 5 11094 188 17 12 98 ] -latency: RMW_Read: [binsize: 8 max: 143 count: 494285 average: 5.89281 | standard deviation: 8.20937 | 428799 0 43439 20640 6 0 0 0 0 992 21 1 2 363 16 1 1 4 ] -latency: Locked_RMW_Read: [binsize: 8 max: 140 count: 339500 average: 5.2378 | standard deviation: 6.75071 | 301236 0 27794 10110 10 0 0 0 0 190 1 0 0 152 6 0 0 1 ] -latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 339500 average: 3 | standard deviation: 0 | 0 0 0 339500 ] -hit latency: [binsize: 1 max: 3 count: 149532617 average: 3 | standard deviation: 0 | 0 0 0 149532617 ] -hit latency: LD: [binsize: 1 max: 3 count: 13535742 average: 3 | standard deviation: 0 | 0 0 0 13535742 ] -hit latency: ST: [binsize: 1 max: 3 count: 9141416 average: 3 | standard deviation: 0 | 0 0 0 9141416 ] -hit latency: IFETCH: [binsize: 1 max: 3 count: 125785924 average: 3 | standard deviation: 0 | 0 0 0 125785924 ] -hit latency: RMW_Read: [binsize: 1 max: 3 count: 428799 average: 3 | standard deviation: 0 | 0 0 0 428799 ] -hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 301236 average: 3 | standard deviation: 0 | 0 0 0 301236 ] -hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 339500 average: 3 | standard deviation: 0 | 0 0 0 339500 ] -miss latency: [binsize: 16 max: 175 count: 2655002 average: 24.8002 | standard deviation: 18.7757 | 0 2479919 181 0 78486 1293 90363 3753 944 61 2 ] -miss latency: LD: [binsize: 8 max: 144 count: 1385533 average: 21.8783 | standard deviation: 12.1052 | 0 0 1328034 25221 131 0 0 0 0 9977 145 16 20 20925 775 45 44 172 28 ] -miss latency: ST: [binsize: 16 max: 175 count: 350016 average: 46.6216 | standard deviation: 35.1891 | 0 224288 30 0 63466 1078 57802 2705 612 33 2 ] -miss latency: IFETCH: [binsize: 8 max: 143 count: 815703 average: 20.4881 | standard deviation: 10.9268 | 0 0 800296 97 4 0 0 0 0 3861 27 4 5 11094 188 17 12 98 ] -miss latency: RMW_Read: [binsize: 8 max: 143 count: 65486 average: 24.8348 | standard deviation: 9.75142 | 0 0 43439 20640 6 0 0 0 0 992 21 1 2 363 16 1 1 4 ] -miss latency: Locked_RMW_Read: [binsize: 8 max: 140 count: 38264 average: 22.855 | standard deviation: 7.38587 | 0 0 27794 10110 10 0 0 0 0 190 1 0 0 152 6 0 0 1 ] - -Request vs. RubySystem State Profile --------------------------------- - - - -Message Delayed Cycles ----------------------- -Total_delay_cycles: [binsize: 1 max: 13 count: 10855755 average: 0.221686 | standard deviation: 0.915908 | 10253393 1133 685 941 598385 739 87 93 74 159 8 10 6 42 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6093680 average: 0.377613 | standard deviation: 1.1709 | 5518533 548 185 218 573099 623 85 91 73 159 8 10 6 42 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 8 count: 4681410 average: 0.022308 | standard deviation: 0.296312 | 4654609 478 413 621 25188 96 2 2 1 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 5 count: 80665 average: 0.0133763 | standard deviation: 0.206119 | 80251 107 87 102 98 20 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index a8e4c360d..4656948e4 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.300436 # Nu sim_ticks 5300435735500 # Number of ticks simulated final_tick 5300435735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137756 # Simulator instruction rate (inst/s) -host_op_rate 264143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6834713129 # Simulator tick rate (ticks/s) -host_mem_usage 828636 # Number of bytes of host memory used -host_seconds 775.52 # Real time elapsed on the host +host_inst_rate 127150 # Simulator instruction rate (inst/s) +host_op_rate 243807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6308537728 # Simulator tick rate (ticks/s) +host_mem_usage 832728 # Number of bytes of host memory used +host_seconds 840.20 # Real time elapsed on the host sim_insts 106831806 # Number of instructions simulated sim_ops 204847037 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory @@ -197,9 +197,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total ticks spent queuing system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 0 # Total ticks spent in databus transfers @@ -367,6 +364,44 @@ system.piobus.respLayer3.occupancy 151500 # La system.piobus.respLayer3.utilization 0.0 # Layer utilization (%) system.piobus.respLayer4.occupancy 151500 # Layer occupancy (ticks) system.piobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.ruby.delayHist::bucket_size 2 # delay histogram for all message +system.ruby.delayHist::max_bucket 19 # delay histogram for all message +system.ruby.delayHist::samples 10855755 # delay histogram for all message +system.ruby.delayHist::mean 0.221686 # delay histogram for all message +system.ruby.delayHist::stdev 0.915908 # delay histogram for all message +system.ruby.delayHist | 10254526 94.46% 94.46% | 1626 0.01% 94.48% | 599124 5.52% 100.00% | 180 0.00% 100.00% | 233 0.00% 100.00% | 18 0.00% 100.00% | 48 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10855755 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 152187620 +system.ruby.outstanding_req_hist::mean 1.000112 +system.ruby.outstanding_req_hist::gmean 1.000078 +system.ruby.outstanding_req_hist::stdev 0.010595 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152170533 99.99% 99.99% | 17087 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152187620 +system.ruby.latency_hist::bucket_size 32 +system.ruby.latency_hist::max_bucket 319 +system.ruby.latency_hist::samples 152187619 +system.ruby.latency_hist::mean 3.380317 +system.ruby.latency_hist::gmean 3.106089 +system.ruby.latency_hist::stdev 3.781052 +system.ruby.latency_hist | 152012536 99.88% 99.88% | 181 0.00% 99.89% | 79779 0.05% 99.94% | 94116 0.06% 100.00% | 1005 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 152187619 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 149532617 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149532617 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 149532617 +system.ruby.miss_latency_hist::bucket_size 32 +system.ruby.miss_latency_hist::max_bucket 319 +system.ruby.miss_latency_hist::samples 2655002 +system.ruby.miss_latency_hist::mean 24.800173 +system.ruby.miss_latency_hist::gmean 21.990972 +system.ruby.miss_latency_hist::stdev 18.775686 +system.ruby.miss_latency_hist | 2479919 93.41% 93.41% | 181 0.01% 93.41% | 79779 3.00% 96.42% | 94116 3.54% 99.96% | 1005 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 2655002 system.ruby.l1_cntrl0.L1Dcache.demand_hits 10730814 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 525933 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11256747 # Number of cache demand accesses @@ -382,6 +417,7 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions system.ruby.l1_cntrl1.L1Dcache.demand_hits 13015879 # Number of cache demand hits system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313366 # Number of cache demand misses system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14329245 # Number of cache demand accesses @@ -397,9 +433,11 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl1.fully_busy_cycles 13 # cycles for which number of transistions == max transitions system.ruby.l2_cntrl0.L2cache.demand_hits 2431660 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 223342 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 2655002 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions system.ruby.network.routers0.percent_links_utilized 0.029766 system.ruby.network.routers0.msg_count.Control::0 850185 system.ruby.network.routers0.msg_count.Request_Control::0 42201 @@ -467,7 +505,6 @@ system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 system.ruby.dir_cntrl0.memBuffer.memArbWait 3135 # memory stalls due to arbitration system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.23% 3.23% | 9701 3.05% 6.29% | 9679 3.04% 9.33% | 9712 3.06% 12.39% | 10010 3.15% 15.54% | 9927 3.12% 18.66% | 9854 3.10% 21.76% | 9702 3.05% 24.81% | 9904 3.12% 27.93% | 9752 3.07% 30.99% | 9805 3.08% 34.08% | 9914 3.12% 37.20% | 9948 3.13% 40.33% | 9724 3.06% 43.39% | 9647 3.03% 46.42% | 8750 2.75% 49.17% | 10266 3.23% 52.40% | 9887 3.11% 55.51% | 9844 3.10% 58.61% | 9758 3.07% 61.68% | 10022 3.15% 64.83% | 9879 3.11% 67.94% | 9766 3.07% 71.01% | 9852 3.10% 74.11% | 10073 3.17% 77.28% | 9931 3.12% 80.40% | 10177 3.20% 83.61% | 10769 3.39% 86.99% | 10605 3.34% 90.33% | 10522 3.31% 93.64% | 10506 3.31% 96.95% | 9709 3.05% 100.00% # Number of accesses per bank system.ruby.dir_cntrl0.memBuffer.memBankCount::total 317877 # Number of accesses per bank - system.ruby.network.routers3.percent_links_utilized 0.006727 system.ruby.network.routers3.msg_count.Control::0 174902 system.ruby.network.routers3.msg_count.Response_Data::1 273157 @@ -716,249 +753,349 @@ system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 814 system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736 system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58608 system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888 -system.ruby.l1_cntrl0.Load | 6084593 40.78% 40.78% | 8836682 59.22% 100.00% -system.ruby.l1_cntrl0.Load::total 14921275 - -system.ruby.l1_cntrl0.Ifetch | 67803399 53.56% 53.56% | 58798232 46.44% 100.00% -system.ruby.l1_cntrl0.Ifetch::total 126601631 - -system.ruby.l1_cntrl0.Store | 5172154 48.50% 48.50% | 5492563 51.50% 100.00% -system.ruby.l1_cntrl0.Store::total 10664717 - -system.ruby.l1_cntrl0.Inv | 16151 50.12% 50.12% | 16074 49.88% 100.00% -system.ruby.l1_cntrl0.Inv::total 32225 - -system.ruby.l1_cntrl0.L1_Replacement | 823061 31.64% 31.64% | 1778014 68.36% 100.00% -system.ruby.l1_cntrl0.L1_Replacement::total 2601075 - -system.ruby.l1_cntrl0.Fwd_GETX | 12035 51.06% 51.06% | 11536 48.94% 100.00% -system.ruby.l1_cntrl0.Fwd_GETX::total 23571 - -system.ruby.l1_cntrl0.Fwd_GETS | 14011 56.35% 56.35% | 10854 43.65% 100.00% -system.ruby.l1_cntrl0.Fwd_GETS::total 24865 - -system.ruby.l1_cntrl0.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 4 - -system.ruby.l1_cntrl0.Data | 735 42.05% 42.05% | 1013 57.95% 100.00% -system.ruby.l1_cntrl0.Data::total 1748 - -system.ruby.l1_cntrl0.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00% -system.ruby.l1_cntrl0.Data_Exclusive::total 1277877 - -system.ruby.l1_cntrl0.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00% -system.ruby.l1_cntrl0.DataS_fromL1::total 24869 - -system.ruby.l1_cntrl0.Data_all_Acks | 576364 43.38% 43.38% | 752324 56.62% 100.00% -system.ruby.l1_cntrl0.Data_all_Acks::total 1328688 - -system.ruby.l1_cntrl0.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00% -system.ruby.l1_cntrl0.Ack::total 21820 - -system.ruby.l1_cntrl0.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00% -system.ruby.l1_cntrl0.Ack_all::total 23568 - -system.ruby.l1_cntrl0.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00% -system.ruby.l1_cntrl0.WB_Ack::total 1682166 - -system.ruby.l1_cntrl0.NP.Load | 278296 20.36% 20.36% | 1088636 79.64% 100.00% -system.ruby.l1_cntrl0.NP.Load::total 1366932 - -system.ruby.l1_cntrl0.NP.Ifetch | 324154 39.75% 39.75% | 491322 60.25% 100.00% -system.ruby.l1_cntrl0.NP.Ifetch::total 815476 - -system.ruby.l1_cntrl0.NP.Store | 221635 52.68% 52.68% | 199080 47.32% 100.00% -system.ruby.l1_cntrl0.NP.Store::total 420715 - -system.ruby.l1_cntrl0.NP.Inv | 5298 59.24% 59.24% | 3645 40.76% 100.00% -system.ruby.l1_cntrl0.NP.Inv::total 8943 - -system.ruby.l1_cntrl0.I.Load | 8385 45.08% 45.08% | 10216 54.92% 100.00% -system.ruby.l1_cntrl0.I.Load::total 18601 - -system.ruby.l1_cntrl0.I.Ifetch | 98 43.17% 43.17% | 129 56.83% 100.00% -system.ruby.l1_cntrl0.I.Ifetch::total 227 - -system.ruby.l1_cntrl0.I.Store | 5670 50.49% 50.49% | 5561 49.51% 100.00% -system.ruby.l1_cntrl0.I.Store::total 11231 - -system.ruby.l1_cntrl0.I.L1_Replacement | 8735 52.29% 52.29% | 7971 47.71% 100.00% -system.ruby.l1_cntrl0.I.L1_Replacement::total 16706 - -system.ruby.l1_cntrl0.S.Load | 550458 51.55% 51.55% | 517421 48.45% 100.00% -system.ruby.l1_cntrl0.S.Load::total 1067879 - -system.ruby.l1_cntrl0.S.Ifetch | 67479144 53.65% 53.65% | 58306780 46.35% 100.00% -system.ruby.l1_cntrl0.S.Ifetch::total 125785924 - -system.ruby.l1_cntrl0.S.Store | 11947 54.75% 54.75% | 9873 45.25% 100.00% -system.ruby.l1_cntrl0.S.Store::total 21820 - -system.ruby.l1_cntrl0.S.Inv | 10719 46.81% 46.81% | 12178 53.19% 100.00% -system.ruby.l1_cntrl0.S.Inv::total 22897 - -system.ruby.l1_cntrl0.S.L1_Replacement | 351460 38.96% 38.96% | 550743 61.04% 100.00% -system.ruby.l1_cntrl0.S.L1_Replacement::total 902203 - -system.ruby.l1_cntrl0.E.Load | 1120786 29.13% 29.13% | 2726694 70.87% 100.00% -system.ruby.l1_cntrl0.E.Load::total 3847480 - -system.ruby.l1_cntrl0.E.Store | 80619 48.39% 48.39% | 85992 51.61% 100.00% -system.ruby.l1_cntrl0.E.Store::total 166611 - -system.ruby.l1_cntrl0.E.Inv | 57 70.37% 70.37% | 24 29.63% 100.00% -system.ruby.l1_cntrl0.E.Inv::total 81 - -system.ruby.l1_cntrl0.E.L1_Replacement | 168208 15.18% 15.18% | 940222 84.82% 100.00% -system.ruby.l1_cntrl0.E.L1_Replacement::total 1108430 - -system.ruby.l1_cntrl0.E.Fwd_GETX | 208 58.92% 58.92% | 145 41.08% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETX::total 353 - -system.ruby.l1_cntrl0.E.Fwd_GETS | 1001 46.45% 46.45% | 1154 53.55% 100.00% -system.ruby.l1_cntrl0.E.Fwd_GETS::total 2155 - -system.ruby.l1_cntrl0.M.Load | 4126668 47.87% 47.87% | 4493715 52.13% 100.00% -system.ruby.l1_cntrl0.M.Load::total 8620383 - -system.ruby.l1_cntrl0.M.Store | 4852283 48.31% 48.31% | 5192057 51.69% 100.00% -system.ruby.l1_cntrl0.M.Store::total 10044340 - -system.ruby.l1_cntrl0.M.Inv | 77 25.33% 25.33% | 227 74.67% 100.00% -system.ruby.l1_cntrl0.M.Inv::total 304 - -system.ruby.l1_cntrl0.M.L1_Replacement | 294658 51.36% 51.36% | 279078 48.64% 100.00% -system.ruby.l1_cntrl0.M.L1_Replacement::total 573736 - -system.ruby.l1_cntrl0.M.Fwd_GETX | 11827 50.94% 50.94% | 11391 49.06% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETX::total 23218 - -system.ruby.l1_cntrl0.M.Fwd_GETS | 13010 57.29% 57.29% | 9700 42.71% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GETS::total 22710 - -system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4 - -system.ruby.l1_cntrl0.IS.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00% -system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1277877 - -system.ruby.l1_cntrl0.IS.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00% -system.ruby.l1_cntrl0.IS.DataS_fromL1::total 24869 - -system.ruby.l1_cntrl0.IS.Data_all_Acks | 349794 38.93% 38.93% | 548696 61.07% 100.00% -system.ruby.l1_cntrl0.IS.Data_all_Acks::total 898490 - -system.ruby.l1_cntrl0.IM.Data | 735 42.05% 42.05% | 1013 57.95% 100.00% -system.ruby.l1_cntrl0.IM.Data::total 1748 - -system.ruby.l1_cntrl0.IM.Data_all_Acks | 226570 52.67% 52.67% | 203628 47.33% 100.00% -system.ruby.l1_cntrl0.IM.Data_all_Acks::total 430198 - -system.ruby.l1_cntrl0.SM.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00% -system.ruby.l1_cntrl0.SM.Ack::total 21820 - -system.ruby.l1_cntrl0.SM.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00% -system.ruby.l1_cntrl0.SM.Ack_all::total 23568 - -system.ruby.l1_cntrl0.M_I.Ifetch | 3 75.00% 75.00% | 1 25.00% 100.00% -system.ruby.l1_cntrl0.M_I.Ifetch::total 4 - -system.ruby.l1_cntrl0.M_I.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00% -system.ruby.l1_cntrl0.M_I.WB_Ack::total 1682166 - -system.ruby.l2_cntrl0.L1_GET_INSTR 815703 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETS 1385690 0.00% 0.00% -system.ruby.l2_cntrl0.L1_GETX 431947 0.00% 0.00% -system.ruby.l2_cntrl0.L1_UPGRADE 21820 0.00% 0.00% -system.ruby.l2_cntrl0.L1_PUTX 1682166 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement 95350 0.00% 0.00% -system.ruby.l2_cntrl0.L2_Replacement_clean 12864 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Data 174902 0.00% 0.00% -system.ruby.l2_cntrl0.Mem_Ack 110230 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data 23018 0.00% 0.00% -system.ruby.l2_cntrl0.WB_Data_clean 2155 0.00% 0.00% -system.ruby.l2_cntrl0.Ack 1666 0.00% 0.00% -system.ruby.l2_cntrl0.Ack_all 6687 0.00% 0.00% -system.ruby.l2_cntrl0.Unblock 24869 0.00% 0.00% -system.ruby.l2_cntrl0.Exclusive_Unblock 1731643 0.00% 0.00% -system.ruby.l2_cntrl0.MEM_Inv 4032 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15306 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETS 32147 0.00% 0.00% -system.ruby.l2_cntrl0.NP.L1_GETX 127449 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GET_INSTR 800365 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETS 82791 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_GETX 1783 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L1_UPGRADE 21820 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement 268 0.00% 0.00% -system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6335 0.00% 0.00% -system.ruby.l2_cntrl0.SS.MEM_Inv 3 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GET_INSTR 28 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETS 1245730 0.00% 0.00% -system.ruby.l2_cntrl0.M.L1_GETX 279143 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement 94921 0.00% 0.00% -system.ruby.l2_cntrl0.M.L2_Replacement_clean 6421 0.00% 0.00% -system.ruby.l2_cntrl0.M.MEM_Inv 1897 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETS 24865 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_GETX 23571 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L1_PUTX 1682166 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement 161 0.00% 0.00% -system.ruby.l2_cntrl0.MT.L2_Replacement_clean 108 0.00% 0.00% -system.ruby.l2_cntrl0.MT.MEM_Inv 116 0.00% 0.00% -system.ruby.l2_cntrl0.M_I.Mem_Ack 110230 0.00% 0.00% -system.ruby.l2_cntrl0.M_I.MEM_Inv 1897 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.WB_Data 229 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.Ack_all 48 0.00% 0.00% -system.ruby.l2_cntrl0.MT_I.MEM_Inv 116 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.WB_Data 75 0.00% 0.00% -system.ruby.l2_cntrl0.MCT_I.Ack_all 33 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack 1395 0.00% 0.00% -system.ruby.l2_cntrl0.I_I.Ack_all 6335 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack 271 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.Ack_all 271 0.00% 0.00% -system.ruby.l2_cntrl0.S_I.MEM_Inv 3 0.00% 0.00% -system.ruby.l2_cntrl0.ISS.Mem_Data 32147 0.00% 0.00% -system.ruby.l2_cntrl0.IS.Mem_Data 15306 0.00% 0.00% -system.ruby.l2_cntrl0.IM.Mem_Data 127449 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.L1_GETS 119 0.00% 0.00% -system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 23603 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETS 38 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1708040 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data 22711 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 2155 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IIB.Unblock 3 0.00% 0.00% -system.ruby.l2_cntrl0.MT_IB.WB_Data 3 0.00% 0.00% -system.ruby.l2_cntrl0.MT_SB.Unblock 24866 0.00% 0.00% -system.ruby.dma_cntrl0.ReadRequest 814 0.00% 0.00% -system.ruby.dma_cntrl0.WriteRequest 46736 0.00% 0.00% -system.ruby.dma_cntrl0.Data 814 0.00% 0.00% -system.ruby.dma_cntrl0.Ack 46736 0.00% 0.00% -system.ruby.dma_cntrl0.READY.ReadRequest 814 0.00% 0.00% -system.ruby.dma_cntrl0.READY.WriteRequest 46736 0.00% 0.00% -system.ruby.dma_cntrl0.BUSY_RD.Data 814 0.00% 0.00% -system.ruby.dma_cntrl0.BUSY_WR.Ack 46736 0.00% 0.00% -system.ruby.dir_cntrl0.Fetch 174902 0.00% 0.00% -system.ruby.dir_cntrl0.Data 97441 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Data 175365 0.00% 0.00% -system.ruby.dir_cntrl0.Memory_Ack 142512 0.00% 0.00% -system.ruby.dir_cntrl0.DMA_READ 814 0.00% 0.00% -system.ruby.dir_cntrl0.DMA_WRITE 46736 0.00% 0.00% -system.ruby.dir_cntrl0.CleanReplacement 12789 0.00% 0.00% -system.ruby.dir_cntrl0.I.Fetch 174902 0.00% 0.00% -system.ruby.dir_cntrl0.I.DMA_READ 463 0.00% 0.00% -system.ruby.dir_cntrl0.I.DMA_WRITE 45071 0.00% 0.00% -system.ruby.dir_cntrl0.ID.Memory_Data 463 0.00% 0.00% -system.ruby.dir_cntrl0.ID_W.Memory_Ack 45071 0.00% 0.00% -system.ruby.dir_cntrl0.M.Data 95425 0.00% 0.00% -system.ruby.dir_cntrl0.M.DMA_READ 351 0.00% 0.00% -system.ruby.dir_cntrl0.M.DMA_WRITE 1665 0.00% 0.00% -system.ruby.dir_cntrl0.M.CleanReplacement 12789 0.00% 0.00% -system.ruby.dir_cntrl0.IM.Memory_Data 174902 0.00% 0.00% -system.ruby.dir_cntrl0.MI.Memory_Ack 95425 0.00% 0.00% -system.ruby.dir_cntrl0.M_DRD.Data 351 0.00% 0.00% -system.ruby.dir_cntrl0.M_DRDI.Memory_Ack 351 0.00% 0.00% -system.ruby.dir_cntrl0.M_DWR.Data 1665 0.00% 0.00% -system.ruby.dir_cntrl0.M_DWRI.Memory_Ack 1665 0.00% 0.00% +system.ruby.delayVCHist.vnet_0::bucket_size 2 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::max_bucket 19 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6093680 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.377613 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 1.170905 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5519081 90.57% 90.57% | 403 0.01% 90.58% | 573722 9.42% 99.99% | 176 0.00% 100.00% | 232 0.00% 100.00% | 18 0.00% 100.00% | 48 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6093680 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4681410 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.022308 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.296312 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4654609 99.43% 99.43% | 478 0.01% 99.44% | 413 0.01% 99.45% | 621 0.01% 99.46% | 25188 0.54% 100.00% | 96 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4681410 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 80665 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.013376 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.206106 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 80251 99.49% 99.49% | 107 0.13% 99.62% | 87 0.11% 99.73% | 102 0.13% 99.85% | 98 0.12% 99.98% | 20 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 80665 # delay histogram for vnet_2 +system.ruby.LD.latency_hist::bucket_size 16 +system.ruby.LD.latency_hist::max_bucket 159 +system.ruby.LD.latency_hist::samples 14921275 +system.ruby.LD.latency_hist::mean 4.752970 +system.ruby.LD.latency_hist::gmean 3.589856 +system.ruby.LD.latency_hist::stdev 6.605068 +system.ruby.LD.latency_hist | 13535742 90.71% 90.71% | 1353255 9.07% 99.78% | 131 0.00% 99.78% | 0 0.00% 99.78% | 9977 0.07% 99.85% | 161 0.00% 99.85% | 20945 0.14% 99.99% | 820 0.01% 100.00% | 216 0.00% 100.00% | 28 0.00% 100.00% +system.ruby.LD.latency_hist::total 14921275 +system.ruby.LD.hit_latency_hist::bucket_size 1 +system.ruby.LD.hit_latency_hist::max_bucket 9 +system.ruby.LD.hit_latency_hist::samples 13535742 +system.ruby.LD.hit_latency_hist::mean 3 +system.ruby.LD.hit_latency_hist::gmean 3.000000 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535742 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13535742 +system.ruby.LD.miss_latency_hist::bucket_size 16 +system.ruby.LD.miss_latency_hist::max_bucket 159 +system.ruby.LD.miss_latency_hist::samples 1385533 +system.ruby.LD.miss_latency_hist::mean 21.878333 +system.ruby.LD.miss_latency_hist::gmean 20.732609 +system.ruby.LD.miss_latency_hist::stdev 12.105161 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1353255 97.67% 97.67% | 131 0.01% 97.68% | 0 0.00% 97.68% | 9977 0.72% 98.40% | 161 0.01% 98.41% | 20945 1.51% 99.92% | 820 0.06% 99.98% | 216 0.02% 100.00% | 28 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1385533 +system.ruby.ST.latency_hist::bucket_size 32 +system.ruby.ST.latency_hist::max_bucket 319 +system.ruby.ST.latency_hist::samples 9491432 +system.ruby.ST.latency_hist::mean 4.608634 +system.ruby.ST.latency_hist::gmean 3.286947 +system.ruby.ST.latency_hist::stdev 10.641770 +system.ruby.ST.latency_hist | 9365704 98.68% 98.68% | 30 0.00% 98.68% | 64544 0.68% 99.36% | 60507 0.64% 99.99% | 645 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 9491432 +system.ruby.ST.hit_latency_hist::bucket_size 1 +system.ruby.ST.hit_latency_hist::max_bucket 9 +system.ruby.ST.hit_latency_hist::samples 9141416 +system.ruby.ST.hit_latency_hist::mean 3 +system.ruby.ST.hit_latency_hist::gmean 3.000000 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9141416 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9141416 +system.ruby.ST.miss_latency_hist::bucket_size 32 +system.ruby.ST.miss_latency_hist::max_bucket 319 +system.ruby.ST.miss_latency_hist::samples 350016 +system.ruby.ST.miss_latency_hist::mean 46.621557 +system.ruby.ST.miss_latency_hist::gmean 35.718714 +system.ruby.ST.miss_latency_hist::stdev 35.189147 +system.ruby.ST.miss_latency_hist | 224288 64.08% 64.08% | 30 0.01% 64.09% | 64544 18.44% 82.53% | 60507 17.29% 99.82% | 645 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 350016 +system.ruby.IFETCH.latency_hist::bucket_size 16 +system.ruby.IFETCH.latency_hist::max_bucket 159 +system.ruby.IFETCH.latency_hist::samples 126601627 +system.ruby.IFETCH.latency_hist::mean 3.112677 +system.ruby.IFETCH.latency_hist::gmean 3.036493 +system.ruby.IFETCH.latency_hist::stdev 1.651388 +system.ruby.IFETCH.latency_hist | 125785924 99.36% 99.36% | 800393 0.63% 99.99% | 4 0.00% 99.99% | 0 0.00% 99.99% | 3861 0.00% 99.99% | 31 0.00% 99.99% | 11099 0.01% 100.00% | 205 0.00% 100.00% | 110 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126601627 +system.ruby.IFETCH.hit_latency_hist::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist::samples 125785924 +system.ruby.IFETCH.hit_latency_hist::mean 3 +system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125785924 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 125785924 +system.ruby.IFETCH.miss_latency_hist::bucket_size 16 +system.ruby.IFETCH.miss_latency_hist::max_bucket 159 +system.ruby.IFETCH.miss_latency_hist::samples 815703 +system.ruby.IFETCH.miss_latency_hist::mean 20.488102 +system.ruby.IFETCH.miss_latency_hist::gmean 19.592998 +system.ruby.IFETCH.miss_latency_hist::stdev 10.926819 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 800393 98.12% 98.12% | 4 0.00% 98.12% | 0 0.00% 98.12% | 3861 0.47% 98.60% | 31 0.00% 98.60% | 11099 1.36% 99.96% | 205 0.03% 99.99% | 110 0.01% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 815703 +system.ruby.RMW_Read.latency_hist::bucket_size 16 +system.ruby.RMW_Read.latency_hist::max_bucket 159 +system.ruby.RMW_Read.latency_hist::samples 494285 +system.ruby.RMW_Read.latency_hist::mean 5.892815 +system.ruby.RMW_Read.latency_hist::gmean 3.949942 +system.ruby.RMW_Read.latency_hist::stdev 8.209372 +system.ruby.RMW_Read.latency_hist | 428799 86.75% 86.75% | 64079 12.96% 99.72% | 6 0.00% 99.72% | 0 0.00% 99.72% | 992 0.20% 99.92% | 22 0.00% 99.92% | 365 0.07% 100.00% | 17 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494285 +system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 +system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 +system.ruby.RMW_Read.hit_latency_hist::samples 428799 +system.ruby.RMW_Read.hit_latency_hist::mean 3 +system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428799 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428799 +system.ruby.RMW_Read.miss_latency_hist::bucket_size 16 +system.ruby.RMW_Read.miss_latency_hist::max_bucket 159 +system.ruby.RMW_Read.miss_latency_hist::samples 65486 +system.ruby.RMW_Read.miss_latency_hist::mean 24.834820 +system.ruby.RMW_Read.miss_latency_hist::gmean 23.926046 +system.ruby.RMW_Read.miss_latency_hist::stdev 9.751416 +system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64079 97.85% 97.85% | 6 0.01% 97.86% | 0 0.00% 97.86% | 992 1.51% 99.38% | 22 0.03% 99.41% | 365 0.56% 99.97% | 17 0.03% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65486 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 16 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 159 +system.ruby.Locked_RMW_Read.latency_hist::samples 339500 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.237800 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.760975 +system.ruby.Locked_RMW_Read.latency_hist::stdev 6.750711 +system.ruby.Locked_RMW_Read.latency_hist | 301236 88.73% 88.73% | 37904 11.16% 99.89% | 10 0.00% 99.90% | 0 0.00% 99.90% | 190 0.06% 99.95% | 1 0.00% 99.95% | 152 0.04% 100.00% | 6 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339500 +system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301236 +system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 +system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 301236 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 16 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 159 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38264 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.855033 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.295821 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 7.385872 +system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 37904 99.06% 99.06% | 10 0.03% 99.09% | 0 0.00% 99.09% | 190 0.50% 99.58% | 1 0.00% 99.58% | 152 0.40% 99.98% | 6 0.02% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 38264 +system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.latency_hist::samples 339500 +system.ruby.Locked_RMW_Write.latency_hist::mean 3 +system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339500 +system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339500 +system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 +system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339500 +system.ruby.L1Cache_Controller.Load | 6084593 40.78% 40.78% | 8836682 59.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 14921275 +system.ruby.L1Cache_Controller.Ifetch | 67803399 53.56% 53.56% | 58798232 46.44% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126601631 +system.ruby.L1Cache_Controller.Store | 5172154 48.50% 48.50% | 5492563 51.50% 100.00% +system.ruby.L1Cache_Controller.Store::total 10664717 +system.ruby.L1Cache_Controller.Inv | 16151 50.12% 50.12% | 16074 49.88% 100.00% +system.ruby.L1Cache_Controller.Inv::total 32225 +system.ruby.L1Cache_Controller.L1_Replacement | 823061 31.64% 31.64% | 1778014 68.36% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2601075 +system.ruby.L1Cache_Controller.Fwd_GETX | 12035 51.06% 51.06% | 11536 48.94% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23571 +system.ruby.L1Cache_Controller.Fwd_GETS | 14011 56.35% 56.35% | 10854 43.65% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 24865 +system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 +system.ruby.L1Cache_Controller.Data | 735 42.05% 42.05% | 1013 57.95% 100.00% +system.ruby.L1Cache_Controller.Data::total 1748 +system.ruby.L1Cache_Controller.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1277877 +system.ruby.L1Cache_Controller.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 24869 +system.ruby.L1Cache_Controller.Data_all_Acks | 576364 43.38% 43.38% | 752324 56.62% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1328688 +system.ruby.L1Cache_Controller.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00% +system.ruby.L1Cache_Controller.Ack::total 21820 +system.ruby.L1Cache_Controller.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 23568 +system.ruby.L1Cache_Controller.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1682166 +system.ruby.L1Cache_Controller.NP.Load | 278296 20.36% 20.36% | 1088636 79.64% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1366932 +system.ruby.L1Cache_Controller.NP.Ifetch | 324154 39.75% 39.75% | 491322 60.25% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815476 +system.ruby.L1Cache_Controller.NP.Store | 221635 52.68% 52.68% | 199080 47.32% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 420715 +system.ruby.L1Cache_Controller.NP.Inv | 5298 59.24% 59.24% | 3645 40.76% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8943 +system.ruby.L1Cache_Controller.I.Load | 8385 45.08% 45.08% | 10216 54.92% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 18601 +system.ruby.L1Cache_Controller.I.Ifetch | 98 43.17% 43.17% | 129 56.83% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 227 +system.ruby.L1Cache_Controller.I.Store | 5670 50.49% 50.49% | 5561 49.51% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11231 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8735 52.29% 52.29% | 7971 47.71% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 16706 +system.ruby.L1Cache_Controller.S.Load | 550458 51.55% 51.55% | 517421 48.45% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1067879 +system.ruby.L1Cache_Controller.S.Ifetch | 67479144 53.65% 53.65% | 58306780 46.35% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 125785924 +system.ruby.L1Cache_Controller.S.Store | 11947 54.75% 54.75% | 9873 45.25% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 21820 +system.ruby.L1Cache_Controller.S.Inv | 10719 46.81% 46.81% | 12178 53.19% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 22897 +system.ruby.L1Cache_Controller.S.L1_Replacement | 351460 38.96% 38.96% | 550743 61.04% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 902203 +system.ruby.L1Cache_Controller.E.Load | 1120786 29.13% 29.13% | 2726694 70.87% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3847480 +system.ruby.L1Cache_Controller.E.Store | 80619 48.39% 48.39% | 85992 51.61% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166611 +system.ruby.L1Cache_Controller.E.Inv | 57 70.37% 70.37% | 24 29.63% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 81 +system.ruby.L1Cache_Controller.E.L1_Replacement | 168208 15.18% 15.18% | 940222 84.82% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1108430 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 208 58.92% 58.92% | 145 41.08% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 353 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 1001 46.45% 46.45% | 1154 53.55% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2155 +system.ruby.L1Cache_Controller.M.Load | 4126668 47.87% 47.87% | 4493715 52.13% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8620383 +system.ruby.L1Cache_Controller.M.Store | 4852283 48.31% 48.31% | 5192057 51.69% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10044340 +system.ruby.L1Cache_Controller.M.Inv | 77 25.33% 25.33% | 227 74.67% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 304 +system.ruby.L1Cache_Controller.M.L1_Replacement | 294658 51.36% 51.36% | 279078 48.64% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 573736 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11827 50.94% 50.94% | 11391 49.06% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23218 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13010 57.29% 57.29% | 9700 42.71% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 22710 +system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1277877 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 24869 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 349794 38.93% 38.93% | 548696 61.07% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898490 +system.ruby.L1Cache_Controller.IM.Data | 735 42.05% 42.05% | 1013 57.95% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1748 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 226570 52.67% 52.67% | 203628 47.33% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 430198 +system.ruby.L1Cache_Controller.SM.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 21820 +system.ruby.L1Cache_Controller.SM.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 23568 +system.ruby.L1Cache_Controller.M_I.Ifetch | 3 75.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Ifetch::total 4 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1682166 +system.ruby.L2Cache_Controller.L1_GET_INSTR 815703 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1385690 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 431947 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 21820 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1682166 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95350 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 12864 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 174902 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 110230 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23018 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2155 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1666 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 6687 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 24869 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1731643 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 4032 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15306 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 32147 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 127449 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 800365 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 82791 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1783 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 21820 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 268 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6335 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 28 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1245730 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 279143 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 94921 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6421 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1897 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 24865 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23571 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1682166 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 161 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 108 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 116 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 110230 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1897 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 229 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 48 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 116 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 75 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 33 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1395 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 6335 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 271 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 271 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 32147 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 15306 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 127449 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 119 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23603 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 38 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708040 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22711 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2155 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 24866 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest 814 0.00% 0.00% +system.ruby.DMA_Controller.WriteRequest 46736 0.00% 0.00% +system.ruby.DMA_Controller.Data 814 0.00% 0.00% +system.ruby.DMA_Controller.Ack 46736 0.00% 0.00% +system.ruby.DMA_Controller.READY.ReadRequest 814 0.00% 0.00% +system.ruby.DMA_Controller.READY.WriteRequest 46736 0.00% 0.00% +system.ruby.DMA_Controller.BUSY_RD.Data 814 0.00% 0.00% +system.ruby.DMA_Controller.BUSY_WR.Ack 46736 0.00% 0.00% +system.ruby.Directory_Controller.Fetch 174902 0.00% 0.00% +system.ruby.Directory_Controller.Data 97441 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 175365 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142512 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% +system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 12789 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 174902 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 463 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45071 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 463 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45071 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95425 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 351 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1665 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 12789 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 174902 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95425 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 351 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 351 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1665 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1665 0.00% 0.00% ---------- End Simulation Statistics ---------- |